USPatent applicationPatented

Liquid crystal display device having light isolation structure

Granted 8 Apr 2003 · 1 office action

Life of the application

10 dated events
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Abstract

A reflective liquid crystal display (LCD) device includes a wall substantially extending between a peripheral portion of a first metal layer (pixel metal layer) formed in the peripheral region of the device with a light shield portion of a second metal layer formed in the pixel region of the device. The structure prevents light from reaching the substrate in the peripheral region of the device. Portions of the second metal layer formed in the peripheral region of the device may therefore be used for signal routing.

Description

4 parts
›FIELD OF TECHNOLOGY

This invention pertains to the field of liquid crystal display (LCD) devices, such as liquid crystal on silicon (LCOS) devices, and more particularly to light shielding in such devices.

›BACKGROUND AND SUMMARY

Reflective LCD devices are well known. Examples of such devices, and in particular active matrix devices, are shown in U.S. Pat. Nos. 6,023,309 and 6,052,165. With reference to the following description, familiarity with conventional features of such devices will be assumed, so that only features bearing on the present invention will be described.

FIG. 1 shows a portion of typical prior-art reflective LCD device 100 . The reflective LCD device 100 may generally be divided into a pixel region 100 a (active region) and a peripheral region 100 b . The pixel region 100 a includes an array of pixel elements and the peripheral region 100 b includes driver circuits 105 for supplying driving signals to each of the pixel elements.

The LCD device 100 comprises, in relevant part, a silicon substrate 110 , an insulating layer 112 , a liquid crystal layer 114 , a transparent electrode 116 , such as indium-tin-oxide (ITO), and a glass layer 118 . A reflective mirror (pixel) metal layer 120 is provided beneath the liquid crystal layer 114 on the insulating layer 112 . The mirror metal layer 120 includes a plurality of individual reflective pixel electrodes 120 a in the pixel region 100 a , with light transmissive regions 122 being located between the pixel electrodes 120 a.

Also provided in the insulating layer 112 and between the mirror metal layer 120 and the substrate 110 are at least three metal layers 124 , 128 and 130 . In the pixel region 100 a , the metal layers 128 and 130 form mutually-orthogonal row and column lines, which may be connected to gate and source electrodes of MOS transistors (not shown in FIG. 1) for pixel elements fabricated in the underlying substrate 110 . In the peripheral region 100 b , the metal layers 128 and 130 form signal routing lines used for routing various signals of the driver circuits 105 . Also, metal plugs or vias 132 are provided for connecting various portions of first, second, third and fourth metal layers 120 , 124 , 128 , 130 with each other.

In addition, the metal layer 124 is provided to prevent light entering the device, such as through the transmissive regions 122 between the pixel electrodes 120 a , from reaching the substrate 110 where it might induce leakage currents or otherwise interfere with proper device operation. Note that while portions of metal layers 128 or 130 may incidentally block a small portion of light entering the device, the structure of FIG. 1 requires a separate metal layer 124 to be dedicated to provide the required degree of light blocking in the peripheral region 100 b . This is due to the fact that light trapped between the two metal layers 120 and 124 can propagate over long distances due to multiple reflections between the layers.

While this prior-art solution is satisfactory for blocking light from reaching the substrate 110 in the peripheral region 100 b , it requires the additional dedicated metal layer 124 in the peripheral region 100 b . However, the area required for the driver circuits 105 could be reduced if the metal layer 124 could also be used for routing driver circuitry signals in the peripheral region 100 b , instead of being dedicated only to light blocking.

Accordingly, it would be desirable to accomplish the light-blocking function of the dedicated metal layer in the peripheral region of the prior art devices without using a separate dedicated metal layer in this region. Other and further objects and advantages will appear hereinafter.

Therefore, in one aspect, the invention provides a liquid crystal display (LCD) which blocks light in the peripheral driver circuit region of the device without providing a dedicated metal layer in this region for this purpose.

Accordingly, an LCD device is provided having a pixel region and a peripheral region adjacent to the pixel region, comprising a substrate, a first metal layer above the substrate including an array of pixel electrodes in the pixel region and a peripheral portion in the peripheral region, a second metal layer beneath the array of pixel electrodes, and a wall disposed between the second and first metal layers along an edge of the pixel region and extending upward to the peripheral portion of the first metal layer.

›BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a simplified cross-sectional view of a portion of a prior-art liquid crystal display (LCD) device having a separate dedicated light blocking layer in the peripheral region; and

FIG. 2 shows a simplified cross-sectional view of a portion of one embodiment of an LCD device having a light-blocking structure in accordance with one or more aspects of the invention.

›DETAILED DESCRIPTION

FIG. 2 shows a simplified cross-sectional view of a portion of a reflective LCD device 200 in accordance with one or more aspects of the invention. For clarity and simplicity, those portions of the device relating to the present invention are illustrated. The reflective LCD device 200 may generally be divided into a pixel region 200 a (active region) and a peripheral region 200 b . The pixel region 200 a includes an array of pixel elements, and the peripheral region 200 b includes driver circuits 205 for supplying driving signals to each of the pixel elements.

The LCD device 200 comprises, in relevant part, a silicon substrate 210 on which are successively provided an insulating layer 212 , a liquid crystal layer 214 , a transparent electrode 216 , such as indium-tin-oxide (ITO), and a glass layer 218 . A first metal layer (pixel metal layer) 220 is provided on the insulating layer 212 beneath the liquid crystal layer 214 . The first metal layer 220 includes a plurality of individual reflective pixel electrodes 220 a formed in the pixel region 200 a , and a peripheral portion 220 b formed in the peripheral region 200 b of the LCD device 200 . Light transmissive regions 222 are located between the pixel electrodes 220 a . Preferably, the peripheral portion 220 b of the first metal layer 220 is substantially continuous in the peripheral region 200 b.

Also, a second metal layer 224 is provided between the first metal layer 220 and the substrate 210 . The second metal layer 224 includes a light shield portion 224 a in the pixel region 200 a , and signal routing lines 224 b in the peripheral region 200 b . A light-blocking partition or wall 226 is provided extending substantially between the light shield portion 224 a of the second metal layer 224 and the peripheral portion 220 b of the first metal layer 220 . Beneficially, the wall 226 is provided on or near an edge of the light shield portion 224 a , at a border between the pixel region 200 a and the peripheral region 200 b . Preferably, the wall 226 is continuously formed around the entire pixel region 200 a . Also, preferably, the wall 226 extends vertically to connect the light shield portion 224 a of the second metal layer 224 to the peripheral portion 220 b of the first metal layer 220 . Additionally, third and fourth metal layers 228 and 230 are provided between the second metal layer 224 and the substrate 210 . Also, metal plugs or vias 132 are provided for connecting various portions of first, second, third and fourth metal layers 120 , 124 , 128 , 130 with each other.

An operation of various pertinent elements of the embodiment will now be described.

In the pixel region 200 a , the third and fourth metal layers 228 and 230 form mutually-orthogonal row and column lines which may be connected to gate and source electrodes of MOS transistors (not shown in FIG. 2) for each pixel element fabricated in the underlying substrate 210 . In the peripheral region 200 b , the third and fourth metal layers 228 and 230 are used for routing various signals of the driver circuits 205 .

Beneficially, the first metal layer 220 is a mirror (pixel) metal layer, such that the peripheral portion 220 b substantially blocks light that directly impinges on the peripheral region 200 b from reaching the substrate 210 in the peripheral region 200 b . Similarly, the light shield portion 224 a of the second metal layer 224 operates together with the pixel electrodes 220 a and the third metal layer 228 to substantially block light that directly impinges on the pixel region 200 a from reaching the substrate 210 in the pixel region 200 a.

Meanwhile, the wall 226 operates together with the light shield portion 224 a of the second metal layer 224 and the peripheral portion 220 b of the first metal layer 220 to form a light shield structure that substantially blocks light (such as light that might enter the pixel region 200 a through the light transmissive regions 222 ) from being directed or reflected onto the substrate 210 in the peripheral region 200 b of the device 200 . Therefore, the portion of the second metal layer 224 in the peripheral region 200 a does not need to be dedicated to blocking light and instead can be used to form signal routing lines 224 b for routing signals of the driver circuits, together with the third and fourth metal layers 228 and 230 . Accordingly, the area required for the driver circuitry, and therefore the total device size, may be reduced. In that case, more devices may be patterned on a wafer and the yield may be increased.

In one embodiment, the wall 226 has a height of approximately 1 μm so as to extend vertically between and connect the first metal layer 220 and the second metal layer 224 . In that case, the thickness of the wall 226 may be approximately 0.6 μm.

In one preferred embodiment, the wall 226 is formed by patterning a vertically-extending hole in the insulating layer 212 and depositing a light-blocking material therein prior to depositing the first metal layer 220 . Also, beneficially, the wall 226 may be formed of Tungsten. In this case, the light blocking wall 226 is formed of the same material as the vias 232 in the insulating layer 212 , thus requiring no additional processing steps.

However, other light blocking materials and methods of fabrication may be used. In an alternative embodiment, an additional layer of opaque insulating material (e.g., TiN) is used to from the light blocking wall 226 . In that case, a voltage potential or electrical signal present on the light shield portion 224 a of the second metal layer 224 may be different from a voltage potential or electrical signal present on the peripheral portion 220 b of the first metal layer 220 . Thus, for example, when it is convenient to ground the light shield portion 224 a of the second metal layer 224 , the peripheral portion 220 b of the first metal layer 220 may be isolated from ground to prevent an undesirable electrical short from occurring.

While the present invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in detail may be made without departing from the scope of the invention as defined by the claims.

Claims as granted

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Classifications

8 codes
IPC · International Patent Classification
Section G — Physics
  • G02F1/1345
  • G02F1/1335
  • G02F1/1362
USPC · US Patent Classification
349/44349/151349/111349/152349/110

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File wrapper

⤢ drag to zoomApr 2001Jul 2001Oct 2001Jan 2002Apr 2002Jul 2002Oct 2002Jan 2003Apr 2003USPTOApplicantNon-final rejectionResponse after non-finalNotice of allowance
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Pendency
2.0 y
725 days filing → grant
Office actions
1
non-final + final
Responses
1
no RCE
Examiner
Robert H. Kim
art unit 2871 · TC 2800
Citations: 5 back · 8 forward

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