Ripple canceling, soft switching isolated DC/DC converters with reduced voltage stress synchronous rectification

1. Field of the Invention

The present invention relates to the field of switching DC to DC converters.

2. Prior Art

DC to DC switching converters of various types are well known in the prior art. Such converters may be used to convert one DC voltage to a second DC voltage which, depending on the converter, may be higher or lower than the first voltage. Switching converters provide a voltage step-up capability not found in linear regulators, and offer higher efficiency than linear regulators in most voltage step-down applications, particularly where the output voltage of the converter is substantially less than the input voltage to the converter. However, switching converters of usual design tend to create significant electrical noise in the form of current ripple on both the converter input and the converter output. This requires substantial capacitance coupled to the input and to the output to keep the voltage ripple on the input supply and on the output voltage within the desired tolerances. While switching converter controllers are generally integrated devices, preferably with limited external devices needed for the complete controller, relatively large filter capacitors on the converter input and output only increases converter cost and board space required for the operative converter.

The present invention, among other things, provides a way of substantially reducing the input ripple and the output ripple in a DC to DC switching converter.

Ripple canceling, soft switching isolated DC/DC converters with reduced voltage stress synchronous rectification. The converters include interleaved switching converters providing power to a node supplying power to a zero volt switching bi-phase power conversion stage driving synchronous rectifiers feeding an output filter. In one embodiment, the interleaved converters are boost mode converters operating in continuous conduction mode boost converters. Various embodiments are disclosed.

FIG. 1 is a diagram of a preferred embodiment of the present invention.

FIG. 2 is a diagram of an alternate embodiment of the present invention.

An exemplary embodiment of the present invention may be seen in FIG. 1 . This embodiment of the converter is controlled by an integrated circuit controller IC 1 , which among other things, controls transistors Q 1 and Q 2 through resistors R 4 and R 5 , respectively, and controls transistors Q 3 and Q 4 through resistors R 7 and R 8 , respectively. The input voltage Vin is coupled to node 1 through the series combination of inductor L 1 and diode D 1 , and is also connected to node 1 through the series combination of inductor L 2 and diode D 2 . In normal operation, node 1 will be at a higher DC voltage than the input voltage Vin, capacitor C 2 providing ripple reduction on the node 1 voltage.

The gates of transistors Q 1 and Q 2 are driven by the integrated circuit IC 1 through resistors R 4 and R 5 , the transistors themselves in this embodiment being n-channel transistors. (The resistors R 4 and R 5 provide damping for any high frequency ringing that might otherwise occur from the gate capacitance and the gate lead inductance.) When transistor Q 1 is turned on by the voltage on terminal BG 1 of the integrated circuit IC 1 going high, the current I 2 in inductor L 2 will increase at a rate given by the equation di 2 /dt=Vin/L 2 , during which time diode D 2 is back-biased. When the voltage on terminal BG 1 goes low, transistor Q 1 will turn off. Now the voltage on node 1 (V node1 ) will decrease the current I 2 through inductor L 2 at a rate given by the equation di 2 /dt=−(V node1 −Vin−V D2 )/L 2 , where V D2 equals the forward conduction voltage across diode D 2 and the minus sign indicates a decreasing current I 2 . The foregoing equation will apply unless, or until, the current in inductor L 2 decreases to zero, after which diode D 2 will become back-biased and further current flow in inductor L 2 will stop.

In the typical operation of the exemplary embodiment of the present invention, transistor Q 1 will be turned on again before the current in inductor L 2 goes to zero, and accordingly, the combination of inductor L 2 , diode D 2 , smoothing capacitor C 2 and transistor Q 1 will operate as a continuous conduction mode boost converter. The switching of transistor Q 1 is pulse-width modulated by the integrated circuit IC 1 responsive to the output of the converter Vout through a feedback circuit to be described, providing a feedback signal on terminal FB of the integrated circuit IC 1 for comparison with a reference voltage generated within the integrated circuit IC 1 .

Inductor L 1 , diode D 1 , capacitor C 2 and transistor Q 2 similarly provide a continuous conduction mode boost converter so that the two boost converters are operating in parallel. By operating the boost converters in an interleaved manner, preferably at a fixed frequency, the ripple current on the input line is greatly reduced, allowing the use of a much smaller capacitor C 1 for input current ripple reduction purposes.

Node 1 is connected to the center tap of the primary winding of power output transformer T 1 , with the ends of the primary winding being coupled to ground through resistor R 10 and transistors Q 3 and Q 4 , respectively. The gates of transistors Q 3 and Q 4 are driven from terminals DCG 1 and DCG 2 of the integrated circuit through resistors R 7 and R 8 , respectively, the resistors providing damping for any high frequency ringing that might otherwise occur from the gate capacitance and the gate lead inductance.

Resistor R 10 is a relatively low-valued sense resistor for alternately sensing the current through transistors Q 3 and Q 4 , the operation of the two transistors having an approximately 50% duty cycle and being out of phase so that both transistors are not on at the same time. The voltage across resistor R 10 is coupled to the current limit input terminal ILIM of the integrated circuit through resistor R 9 , the combination of resistor R 9 and capacitor C 5 providing noise reduction on the voltage across the resistor R 10 .

A secondary winding of transformer T 1 has its first and second ends coupled through inductors L 3 and L 4 to the output Vout, through n-channel transistors Q 5 and Q 6 , respectively, to the output ground, and to the gates of transistors Q 6 and Q 5 , respectively. Capacitor C 9 provides ripple reduction on the output voltage Vout. The cross-coupling of the gate drive for transistors Q 5 and Q 6 makes the transistors operate as synchronous rectifying MOS devices feeding the output LC filter to obtain the desired DC voltage output Vout. Also, the switching of transistor Q 3 and Q 4 with an approximate 50% duty cycle provides zero volt switching of the bi-phase output power conversion stage, which may be either push-pull or a full bridge that drives the main power converter transformer T 1 primary. The zero volt switching is easily achieved by the transformer magnetizing and leakage inductance energy, together with the fixed approximately 50% duty cycle operation. In particular, the center tap of the primary winding of transformer T 1 will be at the voltage of node 1 . When one of transistors Q 3 and Q 4 is on, that end of the primary winding will be nearly at the circuit ground potential, while the other end of the transformer primary will be nearly at twice the voltage of node 1 . When the on transistor turns off, the primary winding voltages will tend to reverse to try to maintain the primary winding current. However the transformer magnetizing and leakage inductance energy will limit the speed at which the voltages will tend to reverse, allowing the switching on of the other transistor as the voltage on the respective transformer lead crosses zero volts. In the embodiment disclosed, the zero volt switching is accomplished by timing of the relative switching of transistors Q 3 and Q 4 , though in an alternate embodiment, switching based on the sensing of the zero volt condition can also be done. Inductors L 3 and L 4 provide output current doubling, though as an alternative, a center tapped secondary winding may be used on transformer T 1 , as in the embodiment of FIG. 2 to be described.

The output voltage Vout is coupled back through an opto-coupler IC 2 to provide a feedback signal to the feedback terminal FB of the integrated circuit IC 1 . In particular, the photodiode of the opto-coupler IC 2 is driven by a network comprising resistors R 11 -R 15 , capacitor C 10 and IC 3 , a precision shunt regulator. In particular, the voltage on the cathode of the shunt regulator may freely increase until the regulation voltage determined by the values of resistors R 13 and R 14 is reached. Below the regulation voltage, there will be no current through resistors R 11 and R 15 , and accordingly no voltage across or current through the photodiode of the opto-coupler IC 2 . When the regulation voltage of the shunt regulator is reached, however, the cathode voltage of the regulator will become clamped, with further increases in the output voltage Vout providing a voltage drop across resistor R 15 , and thus a voltage across the photodiode of the opto-coupler to turn on the phototransistor in the opto-coupler to draw current through the feedback terminal FB, the phototransistor and resistor R 16 in an amount dependent upon the strength of the feedback signal. The feedback signal is used to control the pulse width modulation of the alternate boost converters, formed in part by transistors Q 1 and Q 2 .

Transformer T 1 in the exemplary embodiment also has another secondary winding coupled through diode D 3 to a circuit comprising resistors R 2 and R 6 and capacitors C 3 and C 4 . Resistor R 2 is a rather large valued resistor. When the input Vin is first applied, the small current through resistors R 2 and R 6 begin to charge capacitors C 3 and C 4 . Once these capacitors reach an adequate voltage, the pulse width modulator and the switching of transistors Q 3 and Q 4 starts. While in a preferred embodiment, the current through resistor R 2 is not adequate to sustain the operation of the integrated circuit (IC 1 ), the voltage induced in the third winding of the transformer T 1 as rectified by diode D 3 will sustain operation. Alternatively, the third winding could be eliminated and the integrated circuit power VCC supplied through a lower valued resistor for resistor R 2 . This is not preferred however, as Vin in many applications will be large compared to VCC, so that the power loss through such a resistor would be large compared to the use of the third winding to provide a more efficient source for VCC.

Also included in the integrated circuit of FIG. 1 is an under voltage shutdown circuit of conventional design responsive to the voltage on the UVSD terminal as determined by the ratio of the resistors R 1 and R 3 , and a soft start circuit to limit the duty cycle of the boost converters on the application of power.

In the embodiment of FIG. 1, the use of the current doubling inductors L 3 and L 4 together with the approximately 50% duty cycle of transistors Q 3 and Q 4 in the power conversion stage of the circuit result in the output ripple of the converter from the alternate operation of the transistors Q 5 and Q 6 substantially canceling, grossly reducing the size of the output capacitor C 9 required for final ripple reduction. Also the zero volt switching readily attainable for transistors Q 3 and Q 4 reduces the power loss in the transistors, and the interleaving of the boost converters greatly reduces the input current ripple, thereby reducing the required size of the input current reducing capacitor C 1 . Synchronizing the turn on of transistors Q 3 and Q 4 with the trailing edge (turn off) of transistors Q 1 and Q 2 , respectively further reduces ripple in the circuit.

Now referring to FIG. 2, an alternate embodiment using a center tapped secondary winding on transformer T 1 may be seen. In this case, the inductor L 5 is coupled to the center tap of the secondary, with the ends of the secondary being coupled through transistors Q 5 and Q 6 , respectively, to the low side of the output Vout (output ground), and to the gates of transistors Q 6 and Q 5 , respectively.

The foregoing disclosure of preferred embodiments of the present invention is for purposes of illustration and explanation and not for purposes of limitation of the invention, as various alternate embodiments will be apparent to those skilled in the art. By way of but one other alternate embodiment, the interleaved switching converters may be interleaved buck converters instead of the interleaved boost converters of the embodiment described in detail herein. Thus, while certain exemplary embodiments have been described in detail and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention is not to be limited to the specific arrangements and constructions shown and described, but instead is to be defined by the full scope of the following claims, since various other modifications will occur to those of ordinary skill in the art.