Circuit for voltage to linear duty cycle conversion

1. Field of the Invention

This invention relates to circuits which convert voltage input to duty cycle output and more particularly to such a circuit in which the output varies linearly with the input.

2. Description of the Prior Art

Voltage-to-frequency or voltage-to-duty cycle conversion is often desired because the frequency or duty cycle is less susceptible to noise than an analog voltage. In some cases, the frequency or duty cycle is received by a microprocessor and converted in software to a voltage variable for use within the microprocessor. The use within the microprocessor is greatly simplified if the frequency or duty cycle is linearly proportional to the original input voltage. However, since voltage-to-frequency conversion circuits tend to be overly complex and expensive, a voltage-to-duty cycle conversion is preferred and, accordingly, the need for a simple, linear and inexpensive voltage-to-duty cycle converter has existed.

The present invention provides a low cost and simple voltage-to-duty cycle conversion that is linear with input voltage. The present invention provides a circuit that operates on the input voltage in a predetermined manner to create an output that varies along a first ramp from a first voltage to a second voltage and then back along a second ramp from the second voltage back to the first voltage. This output is presented to a hysteresis comparator to create a periodic pulse train the duty cycle of which is linearly proportional to the input voltage. The values of certain circuit components can be changed so as to change the slope of the ramps and thus the relationship between the output duty cycle and the input voltage. In accordance with the present invention, the linear relationship will, nevertheless, be maintained.

FIG. 1 shows a simplified block diagram of the basic functions of the present invention;

FIG. 2 shows the operation of the hysteresis comparator of FIG. 1;

FIG. 3 shows an example of the variation of Vo with time for one Vin value; and

FIG. 4 shows a schematic diagram of one preferred embodiment of the present invention.

In FIG. 1, Vin represents an input voltage that is to be converted to a duty cycle. Vin may be produced by a microprocessor, may be produced manually, or may be variable with some condition such as pressure or temperature. In any event, Vin is shown being applied to a first input of a box 11 that produces an output voltage Vo on a line 12 that is shown connected to a Hysteresis Comparator 14 that, in turn, produces an output Q on a line 16 that is fed back to a second input of Box 11 . Box 11 is designed to operate with its two inputs, Vin and Q, to produce an output the slopes of which are given by the equations:  Vo  t = K1 - K2  ( Vin )    if     Q = 1 ( 1 )  Vo  t = K1 - K2  ( Vin )    - K3    if     Q = 0 ( 2 )

Where K 1 , K 2 and K 3 are constants with K 1 >(K 2 )(Vin) and, K 3 >K 1 −(K 2 )(Vin). Q will be either a low voltage (logical 0) or a high voltage (logical 1), depending on Vo, as will be seen in FIG. 2 . In FIG. 2, the value of Q is plotted against values of Vo. It is seen that starting with Q being “1” at Vo=H 1 , Q remains a “1” until Vo reaches a value H 2 , at which point Q changes to a value of “0”. Vo then starts becoming smaller until it reaches the value of H 1 , at which point Q again changes back to a value of “1” and Vo begins increasing again. An example of the variation of Vo with time is shown in FIG. 3 where it is seen that the value of Vo varies in a triangle-wave fashion between the values of H 1 and H 2 . The slopes of the triangle wave are dependent on the value Vin and on the values of a variety of circuit components as will be explained in connection with FIG. 4 . Assuming Q is a value of 1, the voltage Vo increases along ramp 20 for a time T 1 until it reaches the value H 2 . As seen in FIG. 2, Q then changes to a 0 and Vo then decreases during a time T 2 along a ramp 22 until it reaches a value H 1 . Now Q becomes 1 again and Vo increases along a ramp 24 and the operation repeats. In FIG. 3 it has been assumed that Vin does not change significantly during the cycle and, as a matter of fact, in most operations, the frequency of the up and down ramps is far greater than any change in Vin.

The linearity of the resulting duty cycle with Vin may be shown by the following mathematical analysis:

From equations (1) and (2) and FIG. 2, H2 - H1 T1 = K1 - K2  ( Vin ) 

 and, ( 3 ) H1 - H2 T2 = K1 - K2  ( Vin ) - K3 ( 4 )

Therefore, T1 = H2 - H1 K1 - K2  ( Vin ) 

 and, ( 5 ) T2 = H1 - H2 K1 - K2  ( Vin ) - K3 ( 6 )

Now, the duty cycle is given by T1 T1 + T2 ( 7 )

Which, by substitution of the values in equations (5) and (6) can be simplified to: 1 - K1 - K2  ( Vin ) K3 ( 8 )

which shows that the duty cycle is linear with respect to Vin since all of the other elements are constant.

FIG. 4 shows one preferred embodiment of the present invention. In FIG. 4, a conversion circuit 100 is shown with the input voltage Vin first connected to a terminal 102 of a voltage follower circuit 104 . Voltage follower circuit 104 is shown as an operational amplifier 106 , having its non-inverting input terminal connected to Vin and its output terminal connected by a line 108 to its inverting input terminal so as to cause the output voltage on a line 110 , to be the same as the input voltage Vin, as is well known in the art. The output terminal of the voltage follower circuit 104 is connected by line 110 to an input terminal 112 of the conversion circuit 100 . It should be understood that, if the output impedance of the device that produces Vin does not affect the conversion circuit 100 , then the voltage follower circuit 104 is not needed and Vin at terminal 102 may be connected directly to the input terminal 112 of the conversion circuit 100 . In either event, input terminal 112 receives the voltage Vin and presents it through a resistor R 1 , identified by reference numeral 114 , to a junction 116 . The current through resistor 114 is designated IR 1 and flows in the direction of the arrow adjacent thereto. Junction 116 is connected by a line 118 to an inverting integrating amplifier circuit 120 , which is shown as an operational amplifier 122 having an inverting input terminal at a pin 5 , a non-inverting input terminal at a pin 6 , and an output at a pin 7 . The inverting input terminal at pin 5 is connected to line 118 and the non-inverting input terminal at pin 6 is connected by a line 124 to a junction point 126 between a resistor R 4 , identified by reference numeral 128 , connected to a source of voltage Vs and a resistor R 5 , identified by reference numeral 130 , connected to a reference voltage or ground. Amplifier 122 has its output terminal at pin 7 connected by a line 132 through a feedback capacitor C 1 , identified by reference numeral 134 , and then by a line 136 to the inverting input terminal at pin 5 of amplifier 122 . The current through capacitor 134 is designated IC 1 and may flow in either of the directions shown by the arrow adjacent thereto. As so connected, inverting integrating amplifier 120 will operate in accordance with equations (1) and (2) to produce the desired output voltage on a line 140 connected to the output terminal at pin 7 from amplifier 122 , as will be explained. While in the preferred embodiment an inverting integrating amplifier 120 , using the operational amplifier 122 , the reference voltage at junction 126 and the feedback capacitor 134 , has been employed, other circuits may be used to perform the operations of equations (1) and (2).

The output of amplifier 122 on line 140 is connected to a hysteresis comparator 142 having an operational amplifier 144 with its inverting input terminal at a pin 9 connected to line 140 and its non-inverting input terminal at a pin 10 connected by a line 146 to a junction point 148 between a first resistor R 3 identified by reference numeral 150 , connected to the source of voltage V s and a second resistor R 3 , identified by reference numeral 152 , connected to the reference voltage or ground. The output of amplifier 144 , from its output terminal at a pin 8 , is connected by a line 154 through a third resistor R 3 , identified by reference numeral 156 , to junction point 148 . The output terminal at pin 8 is also connected to a junction 158 providing the system output at a terminal 160 . Hysteresis comparator 142 is well known in the art to produce an output of either a first or second value depending on the input thereto. The output at terminal 160 is a pulse train having a duty cycle that varies linearly with the input voltage Vin. Junction 158 is also connected by a line 162 to a switch circuit 164 which employs a PNP transistor 166 having its emitter connected by a line 168 to a junction 170 connected to the voltage source Vs and its collector connected by a line 172 through a resistor R 2 , identified by reference numeral 174 , to junction 116 and its base connected to a junction 176 between a resistor R 6 , identified by reference numeral 178 , connected to line 162 and a resistor R 7 , identified by reference numeral 180 , connected to junction 170 . The current through resistor 174 is designated IR 2 and flows in the direction shown by the arrow adjacent thereto. Switch 164 operates in accordance with the output at junction 158 to turn transistor 166 on and off so as to apply the voltage Vs through resistor 174 .

It will be noted that the resistors 128 and 130 create a voltage at pin 6 of amplifier 122 . Resistors 128 and 130 along with Vs are chosen so that the voltage Vin cannot exceed the voltage at pin 5 . It is seen that when Q is high and switch 164 is off, current flows through R 1 and C 1 but not R 2 . When Q is low and switch 164 is on, current flows through R 1 , R 2 , and C 1 . In each case, the voltage at pin 7 changes at a constant rate between the two voltages H 1 and H 2 as seen in FIG. 3 . The result is that the output on pin 8 of amplifier 144 is a pulse train the duty cycle of which is a linear function of the input voltage Vin. The voltage at pin 5 is preferably the voltage that will create a 100% duty cycle on pin 8 . A 0% duty cycle on pin 8 is created when the currents IR 1 and IR 2 through resistors 114 and 174 are the same when Q is low and switch 164 is on. The values for R 1 and R 2 are set so that when switch 164 is on, the current IR 2 is flowing through R 2 is greater than the current IR 1 flowing through R 1 . This causes current to flow from pin 5 to pin 7 through capacitor C 1 and decreases the voltage at pin 7 . R 6 and R 7 are used to bias switch 164 so that switch 164 turns off when the voltage at junction 158 is high and turns on when the voltage at junction 158 is low. R 7 is not needed if the voltage at junction 158 is high enough to turn transistor 166 off.

In the following analysis, although it is not required, it will be assumed for simplicity, that the three resistors 150 , 152 and 156 connected to junction point 148 of the hysteresis comparator 142 are equal. For this reason they have all been designated R 3 in FIG. 4 . Also, the voltages at pins 5 , 6 , 7 , 8 , 9 , and 10 are defined as V 5 , V 6 , V 7 , V 8 , V 9 , and V 10 respectively. As explained above, the voltage Vin will be assumed constant for any of the following calculations, which, for all practical purposes, is true.

The equations for the switching points of the Hysteresis Comparator 142 are as follows: ( Vs )     1 2  R3 1 2  R3 + R3 = 1 3  Vs ( 9 )

when V 8 is high, and, ( Vs )  R3 R3 + 1 2  R3 = 2 3  Vs ( 10 )

when V 8 is low.

V 6 is always equal to [Vs][R 5 /(R 4 +R 5 )] from the voltage divider, and, since the inputs to an operational amplifier connected in this manner are equal, V 5 is also equal to [Vs][R 5 /(R 4 +R 5 )]. When switch 164 is off, which occurs when the voltage V 8 is high, then IR 2 =0 since Vs is not applied to R 2 . Also, at this time, IC 1 =IR 1 since there is no current through R 2 . When switch 164 is on, which occurs when voltage V 8 is low, IR 2 =(Vs−V 5 )/R 2 from Ohm's law. Of course, IC 1 =(C)(dVC 1 /dt) and V 7 =VC 1 +V 5 =VC 1 +[Vs][R 5 /(R 4 +R 5 )].

To determine the duty cycle of the output, V 8 , times T 1 and T 2 can be calculated independently. To calculate the time T 1 , that is, the time when V 8 is high (see FIG. 2) which is also the time it takes for V 7 to change from ⅓Vs to ⅔Vs from equations (9) and (10), along ramp 20 of FIG. 3 consider:

V 7 =VC 1 +V 5   [11]

In FIG. 4, positive current flow in C 1 is from right to left i.e. from pin 7 to pin 5 .

IR 1 is constant since Vin has been presumed constant and IR 2 is constant because V 8 does not change during the time T 1 . Of course, Δ     V7 = Δ     VC1 = IC1 C1  ( T1 ) ( 12 )

for a capacitor, and, T1 = Δ     V7  ( C1 ) IC1 = ( 2 3  Vs - 1 3  Vs )  C1 IC1 = 1 3  Vs  ( C1 ) IR1 - IR2 = 1 3  Vs  ( C1 ) V5 - Vin R1 - 0 ( 13 ) T1 = 1 3  Vs  ( C1 )  ( R1 ) V5 - Vin ( 14 )

Note that T 1 >0 if and only if, Vin<V 5 .

To calculate the time T 2 , that is, the time when V 8 is low (see FIG. 2) which is also the time it takes for V 7 to change from ⅔Vs back to ⅓Vs from equations (9) and (10), along ramp 22 of FIG. 3 consider:

Equation (12) is still valid, so, Δ     V7 = Δ     VC1 = IC1 C1  ( T2 ) 

 and, ( 15 ) T2 = Δ     V7  ( C1 ) IC1 = ( 1 3  Vs - 2 3  Vs )  C1 IC1 = - 1 3  Vs  ( C1 ) IR1 - IR2 = - 1 3  Vs  ( C1 ) V5 - Vin R1 - Vs - V5 R2 

 so, ( 16 ) T2 = - 1 3  Vs  ( C1 )  ( R1 )  ( R2 ) ( V5 - Vin )  R2 - ( Vs - V5 )  R1 ( 17 )

Note that T 2 >0 if, and only if Vin>V 5 +(V 5 −Vs)(R 1 /R 2 ).

Finally, to show that the relationship between the duty cycle and Vin is linear, consider: T1 T1 + T2 = 1 3  Vs  ( C1 )  ( R1 ) V5 - Vin 1 3  Vs  ( C1 )  ( R1 ) V5 - Vin + - 1 3  Vs  ( C1 )  ( R1 )  ( R2 ) ( V5 - Vin )  R2 - ( Vs - V5 )  R1 ( 18 )

which simplifies to: T1 T1 + T2 = 1 - V5  ( R2 ) ( Vs - V5 )  R1 + Vin  ( R2 ) ( Vs - V5 )  R1 ( 19 )

Therefore, the relationship between the duty cycle and the input voltage is seen to be linear as desired. It is also seen that while changing the values in equation (19) may change the slopes of the triangular wave of FIG. 3 so that the duty cycle is changed, the duty cycle remains linear with input voltage.

The following is one list of component values that have been found to provide satisfactory operation for the circuit of FIG. 4 :

Vin=0 volts to 10 volts

Vs=15 volts

R 1 =47.5 KΩ

R 2 =10 KΩ

R 3 =10 KΩ

R 4 =10 KΩ

R 5 =40.2 KΩ

R 6 =10 KΩ

R 7 =1 KΩ

C 1 =0.1 μF

While the component values used above provide satisfactory operation, other component values may be used.

It is seen that we have provided a voltage-to-duty cycle converter that is linear and is simple and inexpensive to implement. The circuit has a small number of components and only two operational amplifiers are needed. Since the duty cycle is linear with respect to the input voltage, the amount of software needed to calculate the value of the input voltage is minimized. The capacitor C 1 is used in both the charging and discharging modes of operation and the value of the capacitor C 1 does not effect the output duty cycle so that variation in its value does not change the function of the circuit.

Many changes, modifications, and substitution may occur to those of ordinary skill in the art. For example, circuits for implementing the operations of equations (1) and (2) other than an inverting integrating amplifier may be devised and the specific circuit for implementing the hysteresis converter may have other forms. Also, alternate component values may be employed without departing from the spirit of the present invention. Therefore, the structures used in describing the preferred embodiments of the present invention are not to be considered as the only ones that may be used to provide a satisfactory linear voltage-to-duty cycle converter in accordance with the teachings herein. The following claims define the scope of the present invention.