USPatent applicationPatented

Mixed mode control for ballast circuit

Granted 14 May 2002 · no office action yet

Assignee: Koninklijke Philips N.V.

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Inventors: Ihor Wacyk, Qiong Li · Examiner: Don Wong · AU 2821 · TC 2800

Application· this page
9812439
filed 20 Mar 2001
Publication
Not published
not published
Patent
US 6,388,398
granted 14 May 2002

Life of the application

5 dated events
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Abstract

A ballast system in which mixed-mode gate signals are used to control the ballast circuit so as to produce a more straight ballast lines such than only a single solution exists between ballast lines and lamp lines over the whole operating range, whereby a stable of lamp performance is achieved. In a preferred embodiment, symmetric and asymmetric modes are arranged alternatively in every other switching cycle to produce mixed-mode PWM gate signals.

Description

5 parts
›TECHNICAL FIELD

This invention relates to a ballast, and more particularly, to an improved apparatus and method for controlling a ballast to drive various types of lamps and produce stable performance of the lamps over a large operating range.

›BACKGROUND OF THE INVENTION

A ballast is a device with a switched mode circuit and is often used to drive lamps, especially high intensity discharge (HID) lamps. As an example, a ballast may be implemented as a half-bridge ballast circuit 1 shown in FIG. 1 . Switches 11 and 12 are turned on and off by applying appropriate gate voltages thereon for producing a stable driving voltage to the lamp or lamps 10 .

The gate voltages are activated and deactivated by gate signals sent from a controller 2 which generates the gate signals and sends them to the ballast circuit 1 . This is illustrated in FIG. 2, which shows a general block diagram for a ballast circuit 1 . In all the circuits for a specific operation, a fixed single-mode gate signal pattern is generated at each switching cycle by the controller 2 and sent to the ballast circuit 1 for controlling the on or off state of the switches 11 and 12 . Pulse width modulation (PWM) or frequency modulation has been used in ballast circuits to regulate the power delivered to the lamp. Two major pulse width modulation (PWM) patterns used are symmetric mode (FIG. 3 a ) and asymmetric mode (FIG. 3 b ). Either way, only a single mode is used. The single-mode control is simple and effective for most of the applications.

As competition increases in the market, more and more functionality and capacities are required in a single ballast circuit, such as universal line input and larger range of load. These requirements are difficult to meet using single mode control. For example, in a universal lamp dimmable ballast system, a single mode PWM control is very difficult to stabilize due to the large variations of lamp characteristics for different temperatures and lamp types. This is explained in more detail with reference to FIGS. 4 a and 4 b, the diagrams of the impedance lines of the ballast and the lamps.

A stable system requires only one single stable solution between the ballast lines and the lamp lines over the whole lamp operation range. However, this sometimes can not be achieved with a single mode control. As shown in FIG. 4 a, the ballast lines with fixed duty cycles in symmetric mode control and two types of lamp lines are superimposed. Multiple solutions are shown with one particular duty cycle, which are marked as points A, B and C on the impedance line of lamp type T5-14W. In FIG. 4 b, which shows the same case but in asymmetric mode control, two solutions, marked as points A and B on the impedance line of lamp type T5-80W, are shown with one particular duty cycle. Thus, an oscillation between the two solutions will occur.

In view of the above, there exists a need in the art for a universal ballast system that solves the instability problem as stated above so that all the lamps may perform stably over the whole lamp operation range.

›SUMMARY OF THE INVENTION

The above problem of the prior art is overcome in accordance with the teachings of the present invention, which relates to a ballast system with a novel control technique. The controller for the ballast circuit generates and transmits gate signals that are of mixed modes. In particular, the gate signals are of a first mode in some switching cycles to cause the ballast circuit to produce concave ballast impedance curves, and are of a second mode in other switching cycles to cause the ballast circuit to produce convex ballast impedance curves. Combinations of these two modes results in relatively straight ballast curves, especially at a lower voltage region, whereby only a single solution exists between the ballast lines and lamp lines over the whole operation range.

Preferably, the gate signals are pulse width modulation (PWM) signals, and the first mode is symmetric mode while the second mode is asymmetric mode, which are arranged alternatively in every other one of the switching cycles.

›BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the present invention can be understood more clearly by reading the following detailed description of a preferred embodiment with reference to the accompanying drawings in which:

FIG. 1 is a half-bridge ballast circuit diagram;

FIG. 2 is a general block diagram for the ballast circuit in FIG. 1 and the controller;

FIG. 3 a shows symmetric mode PWM gate signals;

FIG. 3 b shows asymmetric mode PWM gate signals;

FIG. 4 a shows ballast lines and lamp lines in symmetric mode control;

FIG. 4 b shows ballast lines and lamp lines in asymmetric mode control;

FIG. 5 shows mixed symmetric and asymmetric mode gate signals as incorporated in the present invention;

FIG. 6 shows the implementation block diagram of the mixed mode PWM gate signals as in FIG. 5; and

FIG. 7 shows the ballast lines and lamp lines with mixed symmetric and asymmetric mode control with the gate signals in FIG. 5 .

›DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

As can be seen from FIGS. 4 a and 4 b for the ballast circuit under single-mode control, the symmetric mode control produces concave ballast curves. The curves are too flat and irregularly curved in the low voltage region. The asymmetric mode control produces convex ballast lines as in FIG. 4 b, but the curves are steeper in the low voltage region. Multiple solutions exist in this low voltage region on both sets of curves as shown.

According to the present invention, different modes are combined together to produce a mixed-mode control which will result in flat ballast line curves such that only a single solution exists between ballast lines and lamp lines over the entire operation range.

As a preferred embodiment, a mixed-mode control is generated by alternating symmetric mode and asymmetric mode every other switching cycle, such as shown in FIGS. 5 and 6. The symmetric mode and asymmetric mode are arranged in an alternative pattern in switching cycles. The ballast curves resulting from such mixed-mode control is shown in FIG. 7, and only a single solution exists for both lamp type T5-80W and lamp type T5-14W. The characteristics of ballast lines can be improved since the lamp “sees” only the average effect at these high frequencies.

The controller 2 in FIG. 6 can be implemented by using discrete hardware, programmable logic device or software in a microprocessor for producing mixed-mode gate signals.

Even though FIGS. 5-7 illustrates a specific pattern of mixed-mode control, it shall be understood that other patterns of mixed-mode control are also possible as long as they result in a single solution between ballast lines and lamp lines over the whole operating range. For example, an alternating duty pattern can also achieve similar effects. Furthermore, the gate signals are not limited to pulse width modulation (PWM) signals, and the component modes are also not limited to symmetric and asymmetric modes. Therefore, the scope of the invention is solely determined by the accompanying claims.

Claims as granted

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Classifications

8 codes
IPC · International Patent Classification
Section H — Electricity
  • H05B41/282
  • H05B41/24
  • H05B41/392
USPC · US Patent Classification
315/307315/247315/246315/194315/224

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File wrapper

⤢ drag to zoomApr 2001Jul 2001Oct 2001Jan 2002Apr 2002Jul 2002USPTOApplicantNotice of allowance
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Pendency
1.1 y
420 days filing → grant
Office actions
0
none on record
Examiner
Don Wong
art unit 2821 · TC 2800
Citations: 3 back · 6 forward

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