Solid state circuit breaker with current overshoot protection

Many computer mainframes in use distribute power through a high-voltage bus from a centralized bulk power supply to one or more low-voltage, DC to DC converters located near associated components such as microprocessor boards and memory boards. By using localized DC to DC converters, the converters themselves may be constructed smaller as they need not contain energy storage elements (e.g., input capacitors) for voltage regulation and isolation from a utility power supply. Furthermore, the use of a high voltage distribution bus to feed localized, low-voltage DC to DC converters minimizes resistive power losses on the voltage busses. For example, a 1000 watt, high-density multichip module (MCM) operating at a supply voltage of 2 volts will draw 500 amperes (A) of current. Therefore, the distribution resistance on the low voltage bus will dissipate 250,000 W/Ω (since power dissipated =I 2 R). In contrast, the same amount of power distributed across a 350 volt bus is dissipated at only 8 W/Ω, a difference of over 30,000 times less power lost.

In the event that one of the localized DC to DC converters in a computer system should happen to fail, the server and high voltage bus could be overloaded. An overload on the common high voltage bus, in turn, can affect other components dependent thereupon. Accordingly, a means is typically employed to prevent an electrical overload of a common high voltage bus. Specifically, an electronic or solid state circuit breaker (SSCB) connected to an active bus, such as a computer bus, will interrupt or limit the flow of current through the bus when it is sensed that the current exceeds a predefined value (i.e., a fault condition). A current sensing device may provide an input to a differential amplifier for comparison with a reference voltage. If an overcurrent condition is detected for a certain period of time, the output of the differential amplifier (coupled with a timing circuit) causes a shutdown latch or circuit to turn off a power transistor, thereby disconnecting the bus from the load circuitry.

However, in the event of a sudden fault, such as experienced during a short circuit condition, the resulting fault current can quickly overshoot the desired maximum value before a typical SSCB can respond in time to thereafter limit the current. Because of this, the SSCB may itself be damaged, in addition to an overload of the common bus.

In an exemplary embodiment of the invention, a solid state circuit breaker is disclosed for use in connection with a voltage bus, the voltage bus supplying electrical current to a load. The solid state circuit breaker includes a current controller for controlling the magnitude of current supplied by the voltage bus. A first current sensor senses the magnitude of the electrical current supplied by the voltage bus, the first current sensor having an output in communication with the current sensor. An inductor is included within the first current sensor, the inductor providing a back electromotive force on the voltage bus. The back electromotive force is proportional to the rate of change of current flowing through the voltage bus.

In one embodiment, the first current sensor further includes a differential amplifier, the differential amplifier having an inverting input terminal connected to the voltage bus and a non-inverting terminal connected to a first reference voltage. The differential amplifier further has an output connected to the current controller, wherein the differential amplifier provides a signal to the current controller, causing the current controller to limit the magnitude of current flowing through the voltage bus when the differential amplifier senses an increase in current flowing through the voltage bus during an overcurrent condition.

Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:

FIG. 1 is a schematic diagram of an existing solid state circuit breaker (SSCB);

FIG. 2 is a current versus time waveform illustrating the performance of the SSCB shown in FIG. 1;

FIG. 3 is a schematic diagram of an improved SSCB in accordance with an embodiment of the invention; and

FIG. 4 is a current versus time waveform diagram illustrating the performance of the SSCB shown in FIG. 3 .

Referring initially to FIG. 1, a existing solid state circuit breaker (SSCB) 10 is illustrated. SSCB 10 is shown connected in series with a load 12 fed by a high-voltage DC voltage bus 14 , which may provide a supply voltage of about 350 volts DC. The SSCB 10 features a current controller 11 , comprising an n-channel, enhancement mode power MOSFET (FET) Q1 having a source terminal connected to current sensing resistor R S , and a drain terminal connected to load 12 . The gate of Q1 is connected to the output of a buffer element 16 , which provides a driving voltage to the gate of Q1 in response to an input signal applied thereto. Field effect transistors such as depicted by Q1 are commonly used in SSCBs due to their low “on” resistances, which help to maintain good efficiency.

A first current sensor 18 includes a differential amplifier 20 having a noninverting terminal (+) connected to a first reference voltage, V1 REF . The inverting terminal (−) of the differential amplifier is connected to the source terminal of Q1 and R S though resistor 22 . The output of differential amplifier 20 is fed to an overcurrent timer 24 , as well as to the input of buffer element 16 , through resistor 26 . In addition, the output of differential amplifier 20 is also fed back to the inverting terminal (−) thereof through a zener diode 28 . Finally, a shutdown latch 30 receives an input signal from the overcurrent timer 24 and has an output connected to the input of buffer element 16 through diode 32 .

During normal operation of the SSCB 10 in FIG. 1, Q1 is fully turned on as a result of a high output state of differential amplifier 20 . Differential amplifier 20 is in a high output state during normal operation, since the current flowing through Rs is less than the set threshold level of differential amplifier 20 as determined by V1 REF /R s .

Typically, V1 REF is on the order of a few tenths of a volt in order to minimize the power lost in R S . Zener diode 28 regulates the output voltage of differential amplifier 20 , keeping it in the linear region and preventing it from saturating, thereby allowing differential amplifier 20 to quickly respond to an overload condition. Furthermore, zener diode 28 limits the gate voltage applied to Q1 . In doing so, zener diode 28 thus limits the amount of charge that must be removed from the gate of Q1 in order to turn Q1 off during an overload.

In the event that an overload condition occurs, an increased current initially flows through R S which triggers a change (decrease) in the output voltage of differential amplifier 20 . As a result, differential amplifier 20 adjusts the gate voltage of Q1 in order to maintain the fault current at the desired value determined by V1 REF /R S . For example, the desired maximum fault current value may be about 12.5 amperes (A). At the same time, overcurrent timer 24 is triggered to begin timing the duration that the overcurrent condition exists. If the overcurrent condition continues to exist after a predetermined or “hold” period, the overcurrent timer 24 will send a signal to shutdown latch 30 , which then completely shuts off Q1 by providing a path from the gate of Q1 to ground through diode 32 .

One problem with the above described SSCB 10 , however, arises in the situation where a severe overload condition occurs, such as a short circuit. In such a case, the resulting fault current will actually exceed the maximum desired value for a certain period of time due to the finite time delay inherent in the SSCB 10 , which delay prevents an instantaneous response. A resulting current overshoot could then damage the voltage bus 14 or the SSCB 10 itself.

By way of example, FIG. 2 illustrates a current waveform 34 generated in response to a sudden short circuit condition when the voltage bus 14 is protected by the SSCB 10 shown in FIG. 1 . Prior to t=0 seconds, no current is flowing though load 12 or bus 14 , as the bus 14 is disconnected from load. Then, at t=0 seconds, a short circuit condition is introduced on bus 14 and through SSCB 10 . As is evident from viewing FIG. 2, a large current spike 36 results immediately upon the short circuit condition. Although the graph shown in FIG. 2 only goes up to 70 amperes (A), the actual peak value of the current spike was approximately 81.2 A. After approximately t=8 μs, the fault current drops to a steady state value of approximately 12.5 A, as defined by V1 REF /R S . Finally, after the overcurrent timer 24 has detected a fault level amount of current for a predetermined period of time, it sends a signal to shutdown latch 30 to completely turn off Q1 at about t=128 μs.

Because of the inherent delay in the response of the first current sensor 18 , and in particular differential amplifier 20 , the SSCB 10 and voltage bus 14 sustained a current spike of about 81 amperes for a duration of nearly 8 μs, before differential amplifier 20 was able to regulate the fault current at the desired level. This condition is undesirable and can potentially result in damage to the voltage bus 14 or SSCB 10 , as explained earlier.

Accordingly, in response to the aforementioned drawbacks, an improved SSCB 40 in accordance with an embodiment of the invention is shown in FIG. 3 . For ease of description, like elements appearing in FIG. I and FIG. 3 are shown with the same reference numerals and component designations. In addition to the elements previously described, SSCB 40 further includes a second current sensor 42 having a voltage comparator 44 connected in parallel with differential amplifier 20 . Specifically, voltage comparator 44 has an inverting terminal (−) connected to the inverting terminal (−) of differential amplifier 20 , and an output connected to the input of buffer element 16 . However, voltage comparator 44 has its non-inverting terminal (+) connected to a second reference voltage, V2 REF , which is approximately twice the value of V1 REF . Thus configured, voltage comparator 44 is an amplifier which operates in the saturation region.

An inductor, L S , is connected between Q1 and R S . The inductance value of L S is preferably on the order of about 20 nanohenries (nH), which is roughly equivalent to the inductance of an inch of wire. Accordingly, this inductance value may be attained by appropriately increasing the length of the associated printed circuit board wiring trace. Alternatively, a powdered-iron toroid core having a single turn can provide sufficient inductance. Finally, a third current sensor 46 includes bipolar transistor Q2 having its base terminal connected the source terminal of Q1, while the collector of Q2 is connected to the gate of Q1. The emitter of Q2 is connected to ground so that the gate of Q1 is pulled to ground whenever Q2 is switched on. Q2 is switched on when its base to emitter voltage V BE exceeds a threshold value of approximately 0.7 volts.

With the configuration of the SSCB 40 as shown in FIG. 3, an improved current limiting function is realized. Inductor L S , resisting any sudden changes in current, provides a back electromotive force proportional to the rate of change of current ( di/dt ). As such, differential amplifier 20 will begin to reduce the gate voltage at Q1, even before the current level reaches the programmed threshold, if a sudden increase in current is detected. However, in the event that the rate of current increase exceeds V 2 REF/L S , then the voltage comparator 44 will act more quickly than differential amplifier 20 to adjust the gate voltage at Q1 and hold the fault current to the desired value. Finally, for yet an even faster rate of current change that exceeds V BE /L S , Q2 will immediately turn on and pull the gate of Q1 to ground.

Referring now to FIG. 4, the performance of the SSCB 40 in accordance with the schematic in FIG. 3 is illustrated. Once again, a short circuit condition is introduced into high-voltage bus 14 at t=0 seconds. This time, however, the resulting current spike 48 has peaked at about 16.4 amperes for approximately 2 μs. Immediately thereafter, the current is completely pinched off since the back electromotive force created by the current spike 48 through L S drives V BE of Q2 to its threshold value, turning Q2 on and Q1 off. At approximately t=10 μs, the current begins to rise to the desired fault current level. Because there is no longer a rapid change in current through L S, the voltage thereacross will drop until Q2 is switched off. At the same time, differential amplifier 20 and/or voltage comparator 44 will have had the opportunity to regulate the input voltage applied to Q1 for operation in the linear region. Thus, as Q2 is turned off, Q1 will turn on again, but will only conduct current to the extent allowed by amplifier 20 .

A smooth rise in current is seen after Q1 is turned on in its linear region. At about t=28 μs, the current reaches a steady state value of about 12.5 A (again, defined by V1 REF /R S ), until the overcurrent timer 24 causes the shutdown latch 30 to completely cut off Q1 at about t=140 μs.

It will readily be appreciated that by adding the second & third current sensors 42 , 46 , while at the same time improving the response performance of the first current sensor 18 with inductor L S , the presently disclosed SSCB 40 provides improved protection against the high current transients associated with severe faults such as short circuit conditions. While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.