Switch mode power supply

Typically, a switch mode power supply includes a main switching transistor coupled to a primary winding of a main power transformer. Output supply voltages are developed from voltages developed in secondary windings of the transformer. When the transistor is conductive, a current pulse is developed in the primary winding of the transformer and in the main switching transistor. A voltage is also developed in a current sensing resistor coupled in series with the main switching transistor. The voltage developed in the current sensing resistor is coupled to a comparator transistor. During a given conduction interval of the transistor, a latch that includes the comparator transistor is triggered when the current sensing resistor voltage exceeds a threshold voltage of the comparator transistor. An output of the latch is coupled to the control electrode of the transistor for controlling the turn off instant of the transistor on a current pulse-by-current pulse basis.

In one prior art zero voltage switching (ZVS) power supply, a resonant voltage pulse is produced when the transistor is turned off. The latch maintains the transistor turned off, during a portion of the resonant voltage pulse that follows the instant when the main switching transistor turns off. At the end of a trailing edge of the resonant voltage pulse, when the voltage across the transistor is at or close to zero volts, the transistor is turned on again to provide ZVS power supply. It may be desirable to sustain the main switching transistor in the turned off state, during the aforementioned portion of the resonant voltage, without using a latch for simplifying the circuitry.

A switch mode power supply, embodying an inventive feature includes a source of an input supply voltage and a supply inductance coupled to the input supply voltage source. A capacitance is coupled to the supply inductance to form a tuned, resonstant circuit. A first switching transistor is responsive to a first control signal for generating in a given peroid a pulse in the suppy inductance that is coupled to a load and for generating a resonant pulse in the capacitance. The first control signal turns on the first switching transistor at an end of the resonant pulse for providing zero voltage switching and to turn off the first switching transistor in the given period. The first control signal is generated in accordance with a capacitive current in the capacitance, during the resonant pulse, for maintaining the first switching transistor turned off during a portion of the resonant pulse.

FIG. 1 illustrates a schematic diagram showing an exemplary embodiment of the circuit of the invention; and

FIGS. 2 a - 2 f illustrate waveforms useful for explaining the operation of the circuit of FIG. 1

FIG. 1 illustrates a tuned SMPS 100 , embodying aspects of the invention. In FIG. 1, an N-type, metal oxide semiconductor (MOS) main switching power transistor Q 3 has a drain electrode coupled through a primary winding L 1 of a transformer T 1 to a terminal 20 of an input supply, direct current (DC) voltage RAW B+.

A source electrode of transistor Q 3 is coupled to a ground potential via a current sensor or sampling resistor R 12 . A damper diode D 6 formed integrally with transistor Q 3 and operating as a switch is effectively coupled in parallel with transistor Q 3 to form a bidirectional switch 22 . A resonant capacitor C 6 is coupled to winding L 1 to form, with an inductance of winding L 1 , a resonant circuit 21 when switch 22 is non-conductive.

A secondary winding L 2 of transformer T 1 is coupled to an anode of a peak rectifying diode D 8 for generating an output voltage VOUT in a filter capacitor C 10 that is coupled to a cathode of diode D 8 . Voltage VOUT is coupled to a load circuit 302 . An error amplifier 23 is responsive to voltage VOUT and to a reference voltage, not shown, for controlling a current Ie in a photo transistor Q 1 of photo-coupler IC 1 that includes a light emitting diode D 9 . An emitter electrode of transistor Q 1 is coupled to the base of a switching transistor Q 2 that controls the turn off of transistor Q 3 . A collector voltage V 4 of transistor Q 1 is developed in a filter capacitor C 11 . Emitter current le of opto-coupler IC 1 is indicative of a difference between voltage VOUT and a reference voltage, not shown, of error amplifier 23 . Thus, current le produces a controlling bias voltage at the base of transistor Q 2 .

FIGS. 2 a - 2 f illustrate waveforms useful for explaining the operation of the circuit of FIG. 1 . Similar symbols and numerals in FIGS. 2 a - 2 f and 1 indicate similar items or functions.

Transistor Q 2 of FIG. 1 has its base electrode coupled via a resistor R 11 to a junction terminal 60 between the source electrode of transistor Q 3 and current sensor resistor R 12 . Transistor Q 2 is turned on at a time t 0 of FIG. 2 a when a ramping up source-drain current ID in transistor Q 3 of FIG. 1 produces a sufficiently large voltage at terminal 60 to exceed the base-emitter forward voltage of transistor Q 2 . Transistor Q 3 is turned off when transistor Q 2 becomes conductive. A resistor R 14 is coupled between the emitter and collector of transistor Q 1 for biasing the base-emitter of transistor Q 2 . The level of current ID required to turn on transistor Q 2 in a given cycle is controllable by current le in a negative feedback manner.

A secondary winding L 3 of transformer T 1 produces a voltage V 3 that is AC-coupled via a capacitor C 4 to a resistor R 8 to produce a voltage VR 8 of FIG. 2 e . Voltage VR 8 is coupled to the base of transistor Q 3 of FIG. 1 to generate a positive gate-source voltage VGS. Positive drive voltage VGS turns on transistor Q 3 in a manner to provide a zero voltage switching (ZVS) power supply. The advantages of a ZVS power supply are described in U.S. Pat. No. 5,877,946, issued Mar. 2, 1999, entitled A FORWARD CONVERTER WITH AN INDUCTOR COUPLED TO A TRANSFORMER WINDING, in the name of W. V. Fitzgerald (the Fitzgerald patent). Voltage VGS maintains transistor Q 3 turned on until transistor Q 2 is turned on. AC-coupled voltage V 3 is also rectified by a diode D 2 to generate supply voltage V 4 for producing current le.

A resistor R 9 , coupled between the source of voltage RAW B+ and a terminal 30 of resistor R 8 , produces a voltage that turns on transistor Q 3 , when voltage RAW B+ is turned on, thus providing start up. When voltage VGS on the gate electrode of transistor Q 3 exceeds a threshold voltage of MOS transistor Q 3 , transistor Q 3 conducts, causing a drain voltage VD of transistor Q 3 to decrease. As a result, voltage V 3 becomes positive and reinforces voltage VGS for maintaining transistor Q 3 fully turned on in a positive feedback manner.

During an interval t 1 -t 10 of a given period T of FIG. 2 a , current ID of conductive transistor Q 3 of FIG. 1 is up-ramping. Consequently, a corresponding non-resonant current pulse portion of a current lL 1 in winding L 1 is up-ramping and stores magnetic energy in the inductance associated with winding L 1 of transformer T 1 . At time t 10 of FIG. 2 a , a base voltage VBQ 2 of FIG. 2 d of transistor Q 2 of FIG. 1, containing an up-ramping portion derived from the voltage across resistor R 12 , exceeds the forward voltage of transistor Q 2 and turns on transistor Q 2 . Consequently, gate electrode voltage VGS of FIG. 2 b is reduced to near zero volts and turns off transistor Q 3 of FIG. 1, as indicated before.

When transistor Q 3 is turned off, drain voltage VD of FIG. 2 f increases in a resonant manner. Capacitor C 6 of FIG. 1 limits the rate of increase of voltage VD such that transistor Q 3 becomes completely non conductive before voltage VD increases appreciably above zero voltage.

In an inventive feature, a positive capacitive current iC 6 in capacitor C 6 , that occurs when voltage VD increases, is coupled to resistor R 12 for developing a positive voltage pulse 20 of voltage VR 1112 of FIG. 2 c . Positive voltage pulse 20 is applied via resistor R 11 of FIG. 1 to the base of transistor Q 2 for maintaining transistor Q 2 conductive. As a result immediately afterwards current ID of FIG. 2 a becomes zero. After current iC 6 of FIG. 1 has decreased to a magnitude that and is unable to maintain transistor Q 2 conductive, decreasing voltage V 3 produces a negative portion VR 8 NEG of voltage VR 8 of FIG. 2 e that maintains transistor Q 3 of FIG. 1 turned off.

Resonant circuit 21 that includes capacitor C 6 and winding L 1 undergoes a half cycle of oscillation, during interval t 10 -t 30 of FIG. 2 f , when transistor Q 3 of FIG. 1 is turned off. The decrease in voltage VD prior to time t 40 of FIG. 2 f , causes voltage VGS of FIG. 2 b to become positive.

At time t 30 of FIG. 2 f , voltage VD reverses polarity, causing damper diode D 6 of FIG. 1 to turn on for clamping voltage VD of FIG. 2 f to approximately zero volts. Thus, resonant circuit 21 of FIG. 1 exhibits a half cycle of oscillation. After time t 30 of FIG. 2 b , voltage VGS of FIG. 2 b becomes increasingly more positive, because of the aforementioned change in polarity of voltage V 3 of FIG. 1 .

Negative feedback regulation of voltage VOUT is achieved by varying current le. When Voltage VOUT is larger than the reference voltage, not shown, of amplifier 23 , current Ie increases voltage VBQ 2 . Consequently, the peak value of current ID in transistor Q 3 and the power delivered to load circuit 302 are reduced. On the other hand, when voltage VOUT is smaller than the reference voltage, not shown, of amplifier 23 , current le is decreases. Consequently, the peak value of current ID in transistor Q 3 and the power delivered to the load circuit, not shown, are increased. Thus, the control circuit of transistor Q 3 provides duty cycle modulation of current ID in transistor Q 3 , in accordance with voltage VBQ 2 .

Tuned SMPS 100 operates in a current mode control, on a current-pulse by current-pulse control basis. The current pulse of current ID during interval t 1 -t 10 of FIG. 2 a , flowing in transistor Q 3 of FIG. 1, terminates at time t 10 of FIG. 2 a when the threshold level of transistor Q 3 of FIG. 1 is reached, as explained before.

If a fault condition situation occurs, for example when transistor Q 1 is disconnected, the current in resistor R 14 will maintain base voltage VBQ 2 at a predetermined positive voltage bias. Consequently, the peak value of current ID in transistor Q 3 and the power delivered to load circuit 302 would be limited. Thereby, advantageously, protection is provided.