CMOS current amplifier

The present application claims priority of U.S. provisional patent application No. 60/185,499 filed Feb. 28, 2000.

The present invention relates to current amplifiers.

Current amplifiers are widely used in signal detection/processing systems. For instance, sensors may provide very weak currents proportional to the physical variables acquired. Such current signals may need to be amplified for further processing in electronic circuits.

Two approaches are commonly used.

The first approach consists in using current mirrors. The amplification is performed using large transistors aspect ratios, Dell'Ova et al. (U.S. Pat. No. 5,867,066) describe a circuit which uses current mirrors in one embodiment of their invention. Unfortunately, such designs suffer from great limitations; their implementation requires large silicon surfaces to accommodate large transistors. Such large silicon surfaces produce consequently large parasitic capacitances, increasing delay and power dissipation. Moreover, such current amplifiers usually can not function correctly at weak-current levels.

A second approach consists in employing cascaded transimpedance and transconductance amplifiers. This approach may provide a higher current gain than the first approach. Unfortunately, in most of the existing current amplifiers of this kind, circuit structures are usually complex, involving amplifiers, multiple current sources and current mirrors. As explained with the first approach, current mirrors may be dysfunctional with weak currents. Furthermore, in many reported current amplifiers, a four-level cascoding structure is often used. In each cascoding structure, the transistors are usually set in a saturation mode. It may be difficult to meet such requirements if the supply voltage is low.

Consequently, there is a need for an efficient current amplifier operating at weak current levels.

It is another object of the present invention to provide a current amplifier which operates with low current signals, in the pico/nano ampere range.

It is an object of the present invention to provide a current amplifier which dissipates low power, e.g. in the range of 0.5 mW, while having a high current gain as well as a high gain-bandwidth product for signals which may be low current signals, in pico/nano ampere range.

Yet another aspect of the present invention is to provide such current amplifier which may be implemented on a small silicon surface, e.g. in CMOS.

According to one aspect of the invention, there is provided a method for converting a time-variable voltage signal into a time-variable output current signal using at least one transistor, the method comprising the steps of receiving the time-variable voltage signal; transmitting the time-variable voltage signal to the drain of a transistor, the transistor being maintained in a linear voltage-current operating mode; converting the time-variable voltage signal into a time-variable current signal using the transistor; and adding the time-variable current signal to a substantially fixed current signal generated by a substantially fixed current source to provide an output time-variable current signal.

According to another aspect of the invention, there is provided a converter for converting a time-variable voltage signal into a time-variable current signal, the converter comprising a first transistor for receiving the time-variable voltage signal and providing a shifted time-variable voltage signal; a second transistor which is maintained in a linear current-voltage operating zone, the second transistor receiving the shifted time-variable voltage signal and providing an intermediary time-variable current signal, the intermediary time-variable current signal being proportional to the time-variable voltage signal; a substantially fixed current source; an output, the output receiving a substantially fixed current signal from the substantially fixed current source and the intermediary time-variable current signal to provide a time-variable current signal, wherein the linear current-voltage operating zone of the second transistor and the substantially fixed current source ensures an efficient current amplification.

The invention will be better understood by way of the following detailed description of a preferred embodiment with reference to the appended drawings, in which:

FIG. 1 a is an electrical schematic which shows a prior art voltage signal to current signal converter;

FIG. 1 b is an electrical circuit schematic which shows one embodiment of the present invention;

FIG. 1 c is a block diagram which shows a bidirectional current amplifier;

FIG. 2 is an electrical circuit schematic diagram which shows one embodiment of the present invention;

FIG. 3 a is a graph which shows the output voltage versus the control gate voltage for the CMOS-inverter-like first stage for various operation modes of the NMOS and PMOS transistors of the stage;

FIG. 3 b shows the state of each transistor of the first stage for each zone;

FIG. 4 is a graph which shows the output voltage of the first stage versus the input current over the operating range;

Now referring to FIG. 1 a, there is shown a prior art voltage to current converter. An input voltage v INT is converted into an output current i OUT using transistor T 3 .

Unfortunately, such converter does not provide a linear response for any voltage due to its non-linear voltage-to-current transfer characteristic, Such converter may also have difficulties to work with low voltage.

Now referring to FIG. 1 b, there is shown one embodiment of the present invention. Transistor T 3 transmits a voltage variation v INT into a voltage variation v do . Furthermore, transistor T 5 is maintained in a linear voltage-current mode. Transistor T 5 converts such v do variation into a current variation. Transistor T 5 is maintained in a linear voltage-current mode which ensures an efficient voltage to current conversion which overcomes the limitations from the prior art.

As shown in FIG. 1 c, a bidirectional current signal amplifier may amplify positive as well as negative current signals. An input 26 receives the current signal to amplify; the output 34 provides the amplified current signal. A control element allows a user as well as a microcontroller or any type of computing means to set the control signals 28 , 32 , 36 .

Now referring to FIG. 2, there is shown one embodiment of the present invention. This embodiment of the present invention comprises a transimpedance stage 6 and a transconductance stage 8 . The transimpedance stage 6 converts a current into an intermediate voltage v INT . The transconductance stage 8 converts the intermediate voltage v INT into an output current i OUT .

More precisely, the first stage 6 comprises a NMOS transistor T 2 and a PMOS transistor T 1 . The source of the transistor T 1 is connected to a supply voltage source V dd . The drain of transistor T 1 is connected to the drain of transistor T 2 . The source of transistor T 2 is connected to the ground. The bias of the transistors T 1 and T 2 are controlled by their common gate voltage V TH1 28 . The input current signal i IN is injected into or pulled out of the drain of transistor T 1 and transistor T 2 .

Now referring to FIG. 3 a , there is shown the intermediate voltage V INT versus the control gate voltage V TH1 of the first stage of one embodiment of the present invention.

If the input current of this first stage is equal to zero, this first stage of the current amplifier is, in fact, a CMOS inverter. Such a CMOS inverter operates in 5 different regions as illustrated in FIG. 3 b.

Applying the threshold voltage V TH1 of the inverter at the common gate 28 makes the two transistors, T 1 and T 2 , operate simultaneously in the saturation region and their common drain voltage V INT is equal to the threshold voltage as shown in FIG. 3 a . This is the biasing condition of the first stage of the current amplifier.

If an input current i IN is injected into the first stage 6 , and i IN is small enough, the intermediate voltage v INT of the first stage 6 will be changed to V TH1 −v d , wherein v d is equal to i IN ·r d , r d being the resistance from a drain point of view. In this embodiment of the present invention, r d is approximately equal to the product r dSN ·r dSP /(r dSN +r dSP ), r dSN and r dSP being the drain-to-source resistances of transistors T 2 and T 1 , respectively. As r d may be a few hundred of mega-ohms, v INT is highly sensitive to i IN .

Now referring back to FIG. 2, and according to one embodiment of the present invention, the second stage 8 comprises two NMOS transistors T 3 and T 5 and two PMOS transistors T 4 and T 6 . The source 24 of transistor T 5 is connected to the ground. The drain 22 of transistor T 5 is connected to the source of transistor T 3 . The drain of transistor T 3 is connected to the common drain of transistor T 4 and T 6 . The source of transistor T 4 is connected to the voltage supply source V dd . Both gates of transistors T 4 and T 5 are connected together, at which a bias voltage V TH2 is applied. The value of V TH2 is chosen to drive T 4 and T 5 in the saturation region in case of 22 and 20 being shorted. The input of the second stage 8 is applied at the gate of transistor T 3 . Transistor T 3 operates as a source follower and transfers the input voltage signal from node v INT to node v DO . This results in a low voltage level at the drain of T 5 and it is, therefore, driven in the triode region. Transistor T 5 converts a variation v do into a variation i n . It will be appreciated that the conversion of v do into a variation of i n is performed efficiently as the drain-to-source resistance of transistor T 5 operating in the triode region is small. Transistor T 4 provides an almost constant current is i p , i p =I p . Transistor T 6 operates, in the preferred embodiment of the present invention, in the saturation mode. Transistor T 6 ensures a high output impedance of the current amplifier as well as a stabilization of the signal from following stages.

When the input current i IN is zero at the input 26 of the first stage 6 , the input 30 of the second stage 8 has a voltage v D equal to V TH1 , transistor T 4 generates a current I P , the current of transistor T 5 is i N =I N =I P . The output current is equal to i OUT =I OUT =I P −I N according to Kirchhoff's current law. If the input current is non-zero at the input of the first stage 6 , and as previously explained, the output of the first stage v IN will be equal to V TH1 −v d , the drain of transistor T 5 will encounter a variation of −v do . The current which flows though the drain of transistor T 5 will be equal to i N =I N −i n wherein i n =v do /r dSN5 , where r dSN5 is the drain-to-source resistance of transistor T 5 operating in the triode mode. The output current i OUT is equal to i P −i N and by definition is equal to i out +I OUT . The output signal current i out is equal to i out =v do /r dSN5 . v do is equal to kr d i in wherein k=v do /v d . The gain from the current amplifier is therefore A i =k·r d /r dSN5 , which is far more important than 1. It will be appreciated that this current amplifier is capable of operating with bi-directional current signal.