Ultra-fast voltage drive

Cross reference is made to commonly assigned U.S. patent application Ser. No. 09/772,770 entitled “Enhanced Voltage Drive Circuit for HDD Write Drive,” filed herewith and the teachings incorporated herein by reference.

The present invention is generally related to mass media drive controllers, including HDD drives, and more particularly to an ultra-fast voltage drive for a write drive control circuit controlling the head of the drive.

The coil current waveform characteristics that are important in a HDD voltage write driver circuit are depicted at 10 in FIG. 1 . In particular, the current rise time, overshoot, undershoot, and settling time are of particular interest. Desired characteristics for the coil current waveform are a fast rise time and settling time, a controllable amount of overshoot, and very little undershoot. By achieving these characteristics, a hard disk drive storage capacity can be improved.

A conventional voltage source based write coil driver circuit is shown at 20 in FIG. 2. A coil is modeled as LS, and is connected to four transistors via coil node HX and node HY. The connection of the four transistors to the coil is known conventionally as an H-bridge. The coil is typically referred to as the head. The H-bridge controls the direction of the coil current I w , known as a coil current reversal, to responsively create magnetic flux changes through the coil.

One limitation of this conventional voltage source based write coil driver 20 is the differential transient voltage generated at nodes HX and HY conventionally known as (TRTF), driving a current reversal. This limitation can be appreciated in conventional circuit 20 shown in FIG. 2, whereby the voltage of one node can be momentarily pulled down, such as node HX, to near the second voltage rail V ee using transistor Q 1 . However, and disadvantageously, there is no circuit to pull up the other node, such as node HY. Thus, the voltage at each node can go no higher than established that are expressed by the following equation:

V node =V cc −( V be +RS×I w ).

The coil current I w has a nominal current of about 40 milliamps with control signals QL or {overscore (QL)}. However, during current reversal of the coil, transistors Q 1 or Q 2 are temporarily turned on to “boost” normal current and decrease the differential voltage TRTF. It can be appreciated that transistors Q 1 and Q 2 bypass half of the matched impedance resistors RS during this “boost,” however, the other series resistor RS is still in the current path. Thus, the above equation represents the maximum voltage that one node can attain when the other node is pulled down close to V ee .

There is desired an improved circuit that improves the speed of a rail-to-rail drive circuit, and which includes drive circuit providing a rail-to-rail drive voltage to large PMOS FETs pulling-up a voltage at nodes HX and HY.

The present invention achieves technical advantages as a rail-to-rail ultra-fast voltage drive circuit providing a rail-to-rail drive voltage to a subsequent drive circuit, such as a HDD write driver control circuit. The voltage drive circuit has a pair of serially connected output transistors driven by a control circuit such that an output voltage defined at an output node between the two output transistors is driven fast rail-to-rail.

This control circuit preferably comprises three serially connected FETs coupled between the voltage rails, whereby the middle FET controls the voltage at the output node. The other two FETs are coupled to a respective voltage rail, and each have their gates connected to the opposing rail. This gate xying arrangement reduces the number and size of the devices required in this control circuit, and further speeds up the rail-to-rail voltage swings of the drive circuit.

FIG. 1 is a waveform diagram of a conventional coil current waveform characteristics including the rise time associated with a current reversal of a drive circuit;

FIG. 2 is a schematic diagram of a conventional HDD drive circuit;

FIG. 3 is a schematic diagram of the present invention including the ultra-fast voltage drive circuit finding advantages with a HDD write coil driver circuit;

FIG. 4 is a detailed schematic diagram of the ultra-fast voltage drive circuit illustrated in FIG. 2 providing an output voltage at an output node that quickly swings from rail-to-rail, that is, from V cc to GND;

FIG. 5 is a signal diagram of the output voltage swing at node N 1 ; and

FIG. 6 is a signal diagram of the output voltage swing at node N 1 without using FETs M 5 , M 6 and M 7 .

Referring now to FIG. 3, there is illustrated generally at 30 a write driver control circuit 31 and a pair of ultra-fast voltage drive circuits 40 controlled by a control circuit shown at 50 . Each of these ultra-fast voltage drive circuits 40 , shown in detail in FIG. 4, provide an ultra-fast, rail-to-rail drive voltage to the large PMOS boost FETs shown at 32 , thereby achieving the advantages of getting maximum voltage swing from the PMOS devices 32 , with a very quick voltage swing from one rail to the other.

For more detailed understanding of the HDD drive circuit shown at 31 , cross-reference is made to commonly assigned co-pending patent application Attorney's Docket number TI-32302 entitled “Enhanced Voltage Drive Circuit for HDD Write Driver,” filed herewith and the teachings incorporated herein by reference.

Turning now to FIG. 4, there is shown at 40 one of the PMOS voltage drive circuits seen too include a pair of serially connected bipolar output transistors Q 3 and Q 4 having an output node N 1 defined therebetween. This output node N 1 is connected to the gate of the respective voltage pull-up FET, either M 1 or M 2 , as shown in FIG. 3 . Transistor Q 4 is a Schottky transistor to obtain a low V cesat . Control circuit 50 , during a current reversal, selectively controls one of the voltage drive circuits 40 to drive the gate of the respective M 1 or M 2 FET hard. As described in the co-pending patent application, during a current reversal, transistors Q 1 and M 2 will be on with the other transistors Q 2 and M 1 off, and for the next current reversal, transistors Q 2 and M 1 will be on, with the other transistors Q 1 and M 2 being off. The respective “boost” FETs shown at 32 , when on, will pull the voltage at the corresponding node HX or HY high to V cc , with the other corresponding node is being pulled low near V ee by the other transistor Q 1 or Q 2 that is on.

Referring back to FIG. 4, the PMOS drive circuit 40 is seen to include a control circuit 42 comprised of three serially connected FETs shown as M 5 , M 6 , and M 7 , with the middle or second FET M 6 residing therebetween. The node defined between FETs M 5 and M 6 is tied to the output node N 1 , with the node defined between FETs M 6 and M 7 being connected to the base of output bipolar Schottky transistor Q 4 . The source of FET M 7 is seen to be tied to the second lower voltage rail having potential GND. The source of the FET M 5 is connected to the upper voltage rail V cc via FET M 10 .

Also shown is that the gate of FET M 5 is connected to the lower voltage rail GND, with the gate of FET M 7 being connected to the positive voltage rail V cc . FET M 5 , therefore, is controlled by source voltage, not gate, and switches faster because FET M 7 is always on. Advantageously, this transistor arrangement reduces the switching time for a rail-to-rail voltage swing, and also reduces the number of components required.

Advantageously, FET M 6 and M 7 , when on, form a resistive divider to drive transistor Q 4 . Transistor Q 4 is a Schottky device to obtain low V cesat . Controls the output voltage swing at the output node N 1 . Specifically, a control circuit generally shown at 44 has a first output shown as control line 46 being connected to the base of the first output transistor Q 3 , and source of transistor M 5 , and a second, complementary, output single line 48 being connected to the gate of control FET M 6 . Control line 46 operates such that a logic “high” signal provided on signal line 46 turns on output transistor Q 3 and FET M 5 , whereby the complementary logic “low” signal on output single line 48 keeps control FET M 6 off and consequently keeps transistor Q 4 off due to transistor M 7 . Similarly, a logic “low” on control line 46 shuts transistor Q 3 and M 5 off, with a complementary logic “high” signal on control line 48 turning control FET M 6 on, thereby turning on the output transistor Q 4 temporarily through the resistor divider. Transistor Q 3 and Q 4 are used to drive the output node, N 1 , hard with large current sourcing and sinking capabilities but unable to drive rail-to-rail. Q 4 can't pull node N 1 all the way to GND, and transistor Q 3 can't pull node N 1 all the way to VCC. FET M 5 is used to pull node N 1 up to V cc toward the end of the transition, while FETS M 6 and M 7 are used to pull node N 1 to GND at the end of the opposite transition.

V cc Voltage Provided to Output Node N 1

When a logic “high” signal is provided to the input signal line shown at 49 , the control circuit 44 provides a logic “high” to control line 46 such that output transistor Q 3 is on, which initially pulls the output voltage at output node N 1 to within approximately 0.7 volts of the first rail V cc . A logic “low” is provided on output control line 48 such that control FET M 6 is “off.” Advantageously, FET M 5 becomes “on” before Q 3 stops providing drive current to complete the Vcc rail swing.

GND Rail Provided to Output Node N 1

When a logic “low” signal is provided to input line 49 , a logic “low” output signal is provided to output line 46 , and logic “high” signal is provided to output line 48 . Thus, output transistor Q 3 is responsively in the “off” state, control FET M 6 is in the “on” state, and output transistor Q 4 is in the on state and pulls down the output voltage at node N 1 to within 0.4 volts of the lower rail GND. Advantageously, since FET M 7 is in the “on” state, FET M 7 will pull the voltage at the output node N 1 completely to the lower rail GND, such as zero volts.

Notably, if a conventional control circuit including only output transistors Q 3 and Q 4 were provided, FETs M 5 and M 6 could be deleted. However, this is counter to the goal of the present invention of which is to drive the gates of the large PMOS of FETs 32 rail-to-rail, quickly, and providing strong driving capabilities. The combination and configuration of the three drive FETs M 5 , M 6 , and M 7 are used to controllably and quickly drive the output node N 1 rail-to-rail, that is from V cc to GND and back again as a function of the control signal provided to the input line 49 . Again, FET M 7 is always in the “on” state and FET M 5 is controlled by its source to minimize the number and size of the devices required in this circuit 40 . Rather, only the middle FET M 6 and node 46 is selectively controlled to responsively effect the control of output transistors Q 3 and Q 4 , whereby FETs M 5 and M 6 -M 7 complete either the pull-up or the pull-down of voltage at the output node N 1 .

Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.