Stray-insensitive, leakage-independent image sensing with reduced sensitivity to device mismatch and parasitic routing capacitance

The invention relates generally to electronic circuitry and its operation and, more particularly, to the structure, control and operation of CMOS image sensing circuitry.

CMOS image sensors are emerging as a viable alternative to CCD sensors due to the low power consumption and high integration capability of CMOS circuitry. However, CMOS imaging sensors also have various problems. One example is the so-called fixed-pattern-noise (FPN) caused by device mismatches and/or process nonuniformities. A mismatch occurs at each pixel site, and at each column read-out.

An example of a known CMOS imaging sensor is shown in FIG. 9 . The key blocks are: Pixel Block; Column Block; and Chip Output Block. The pixel Block (one for each pixel) includes the following: Photodiode PD; NMOS Transistor N 1 ; and Switches RES and SEL. The Column Block (one for each column of Pixels) includes the following: Capacitors C 1 and C 2 ; PMOS Transistor P 1 ; Switches CDS and COL; and Current sources IPIXEL and ICOL. The Chip Output Block (one for the whole chip) includes the following: PMOS Transistor P 2 ; Switch CHIP; and Current Source ICHIP.

The operation of the Pixel Block is as follows: Node IN is connected to switch RES, the cathode of photodiode PD, and the gate of NMOS transistor N 1 . Initially switch RES is closed and the voltage on node IN is VRES. Then switch RES is opened. There will be a finite charge on node IN dependent on the voltage VRES, the capacitance of photodiode PD, and the gate capacitance of NMOS transistor N 1 . The photodiode current causes the charge on node IN to be discharged and the voltage on node IN decreases. Generally imagers have a fixed integration time or period. The voltage on node IN at the end of the integration period is referred to herein as VPD.

The voltage on node IN is read out using NMOS transistor N 1 and Switch SEL, the Column Block circuit, and the Chip Output Block circuit.

FIG. 10 summarizes the position of the switches during the Integration Period and the Pixel Readout, which enables the FPN to be suppressed.

During the Integration Period, RES and SEL are open. During the Pixel Readout, the following occurs.

Readout Step 1 : RES and SEL are open, CDS, COL, and CHIP are closed to reset the Column and Chip Blocks. The voltage across C 1 will be zero. The voltage across C 2 is VP 1 gs, which is the gate to source voltage of PMOS transistor P 1 .

Readout Step 2 : SEL is closed and COL is opened. The voltage across C 1 becomes VPD−VN 1 gs (VN 1 gs=gate to source voltage of NMOS transistor N 1 ). The voltage across C 2 remains VP 1 gs.

Readout Step 3 : CDS and CHIP are opened. The voltage across C 1 remains VPD−VN 1 gs. The voltage across C 2 remains VP 1 gs.

Readout Step 4 : RES and COL are closed. The source voltage of N 1 becomes VRES−VN 1 gs. The voltage across C 1 remains VPD−VN 1 gs. Thus the gate voltage of P 1 becomes (VRES−VN 1 gs)−(VPD−VN 1 gs)=VRES−VPD. The source voltage of P 1 becomes (VRES−VPD)−VP 1 gs. The voltage across C 2 remains VP 1 gs. Thus the gate voltage of P 2 becomes (VRES−VPD)−VP 1 gs+VP 1 gs=VRES−VPD. The readout voltage OUT is VRES−VPD+VP 2 gs where VP 2 gs is the gate to source voltage of PMOS transistor P 2 . PMOS transistor P 2 is a common device used for the readout of all pixels.

Both VN 1 gs and VP 1 gs terms are canceled in this Sequential Correlated Double Sampling Technique. The N 1 and P 1 Vt terms, which are embedded in the VN 1 gs and VP 1 gs, are also canceled. Thus the effect of CMOS Vt mis-matches are suppressed with the above technique and the Fixed Pattern Noise is greatly reduced.

Readout Step 5 : CHIP is closed. The readout voltage OUT equals VP 2 gs. The rest of the switches are opened. The pixel has been reset for the next Integration Period. The system is ready for the next pixel readout.

The above description is a readout operation for one pixel. During the Integration Period for one pixel, the Column Block and Chip Output Blocks are being used for Readout of other pixels.

Some problems with the CMOS imaging sensor of FIG. 9 include the disadvantageous effect of parasitic routing capacitance caused by capacitors C 2 (thousands of them in a complete pixel array) driving the transistor P 2 , and the fact that the capacitors are typically poly/n-well capacitors which disadvantageously tend to be stray-sensitive and also suffer from a leakage problem.

It is desirable in view of the foregoing to provide for CMOS image sensing that avoids the aforementioned problems associated with known CMOS imaging sensors.

According to the invention, a single capacitor can be used for both readout and reduction of device mismatches. Such dual-purpose use of a single capacitor is facilitated by a switching arrangement. The switching arrangement connects the capacitor to a low impedance node during charge storage, thereby advantageously providing the stored charge with a stray-insensitive, leakage independent characteristic. Also, the column readout line is driven by the low impedance node, thereby advantageously reducing parasitic routing capacitance.

FIG. 1 illustrates pertinent portions of exemplary embodiments of an imaging sensor according to the invention.

FIG. 2 is a timing diagram which illustrates an example of the control and operation of the imaging sensor of FIG. 1 .

FIG. 3 illustrates a reset state of the imaging sensor of FIG. 1 .

FIG. 4 illustrates a read-out state of the imaging sensor of FIG. 1 .

FIG. 5 illustrates pertinent portions of further exemplary embodiments of an imaging sensor according to the invention.

FIG. 6 is a timing diagram which illustrates exemplary signals which can be used to control operations of the imaging sensor of FIG. 5 .

FIG. 7 illustrates a sampling state of the imaging sensor of FIG. 5 .

FIG. 8 illustrates a read-out state of the imaging sensor of FIG. 5 .

FIG. 9 and 10 illustrate a known CMOS imaging sensor arrangement.

FIG. 1 illustrates pertinent portions of exemplary embodiments of a CMOS imaging sensor according to the invention. The imaging sensor of FIG. 1 includes a pixel circuit 11 and a column read-out circuit 13 . The imaging sensor of FIG. 1 includes a plurality of circuit nodes designated as n 1 , n 2 , n 3 , n 4 , n 5 , n 6 and n 7 . The column read-out circuit 13 includes a poly/n-well capacitor C coupled between nodes n 5 and n 6 , and a buffer coupled between nodes n 4 and n 7 . The pixel circuit 11 includes a photodiode PD as is conventionally used in CMOS imaging sensors.

The imaging sensor of FIG. 1 further includes a switching arrangement including a plurality of switches for selectively interconnecting various nodes in the imaging sensor. Each switch of the switching arrangement is controlled by one of a plurality of control signals designated in FIG. 1 as Φ 1 , Φ 2 , Φ 3 , Φ 4 and Φ 5 . These control signals are also illustrated in the timing diagram of FIG. 2 . The timing diagram of FIG. 2 , taken in conjunction with FIGS. 1 , 3 and 4 , illustrates an example of the control and operation of the imaging sensor of FIG. 1 .

Referring now to FIGS. 1-3 , when Φ 1 (reset), Φ 3 (row select) and Φ 4 (hold) are high in FIG. 2 , the corresponding switches in FIG. 1 are closed, and the remaining switches controlled by Φ 2 and Φ 5 are open. Thus, at this time, the imaging sensor of FIG. 1 has the circuit configuration illustrated in FIG. 3 . At this time, the voltage across the capacitor C is:

ΔV c =V ref −( V ref −V gs,M +V off,M +V off,buf )

where V gs,M represents the gate-source voltage of the NMOS driver M, V off,M represents the DC offset of the driver M, and V off,buf represents the DC offset of the buffer.

When Φ 4 (hold) goes low and Φ 5 (column select) goes high after exposure, the sensor of FIG. 1 assumes the circuit configuration illustrated in FIG. 4 . In this configuration, the output voltage is given by:

V out = ⁢ V p ⁢   ⁢ h - V gs , M + V off , M + V off , buf + Δ ⁢   ⁢ V c = ⁢ V p ⁢   ⁢ h - V gs , M + V off , M + V off , buf + V ref - ⁢ ( V ref - V gs , M + V off , M + V off , buf ) = ⁢ V p ⁢   ⁢ h

where V ph is the voltage across the photodiode PD.

It can be seen from the foregoing that all of the mismatch offsets are stored in the capacitor C during the reset phase, and are then cancelled out in the read-out phase. That is, the operation illustrated in FIGS. 1-4 uses the reset phase, as controlled by Φ 1 to store the mismatch information into the capacitor, and the mismatch information is then cancelled out during the read-out phase controlled by Φ 4 and Φ 5 . This means that the operation described above with respect to FIGS. 1-4 can read-out only one row of the image sensor array at one exposure time. Accordingly, in applications that have a particularly long exposure time, the embodiments of FIGS. 1-4 might not be able to read out the whole image sensor array as quickly as desired.

FIG. 5 illustrates pertinent portions of exemplary embodiments of a CMOS imaging sensor according to the invention which can provide faster operation than the imaging sensor of FIG. 1 . The image sensor of FIG. 5 includes generally the same circuit elements as FIG. 1 , but has a differently designed arrangement of switches for controlling interconnection of the circuit elements. The sensor of FIG. 5 includes nodes n 11 , n 21 , n 31 and n 41 , and each of the switches in the FIG. 5 switching arrangement is controlled by one of a plurality of control signals Φ 11 , Φ 21 , Φ 31 and Φ 41 . The image sensor of FIG. 5 also utilizes two voltage references, V ref1 and V ref2 , to increase the output signal swing range.

FIG. 6 is a timing diagram which illustrates the signals Φ 11 , Φ 21 , Φ 31 and Φ 41 which control the image sensor of FIG. 5 . As shown in FIG. 6 , the image signal is read-out by operation of Φ 41 (column select) during the second pulse of Φ 11 (reset).

Referring now to FIGS. 5 and 6 , during the sampling phase, when Φ 21 (sample) and Φ 31 (row select) both go high, the image sensor of FIG. 5 assumes the circuit configuration illustrated by FIG. 7 . In FIG. 7 , the voltage across capacitor C is given by:

Δ V c =V ref2 −( V ph −V gs,M +V off,M +V off,buf ).

During the read-out phase, with Φ 11 , Φ 31 and Φ 41 all high, the image sensor of FIG. 5 assumes the circuit configuration illustrated in FIG. 8 . In this configuration, the output voltage is given by:

V out = V ref1 - V gs , M + V off , M + Δ ⁢   ⁢ V c + V odd , buf = V ref1 + V ref2 - V p ⁢   ⁢ h .

Again, the offset mismatch does not appear in the output voltage V out , which is read-out during the reset phase. Therefore, different rows of an image sensor array can partly share the exposure time illustrated in FIG. 6 .

In view of the foregoing discussion, it will be evident to workers in the art that the imaging sensor embodiments of FIGS. 1-8 are: insensitive to parasitic routing capacitance because the output nodes n 7 and n 41 are low-impedance nodes; low power sensors because they provide a true column-parallel read-out; leakage and stray insensitive although using a poly/n-well capacitor, because the n-well is connected to a low-impedance node during charge storage. Moreover, and assuming that the capacitors C within a given sensor array are well matched, charge-injection and clock-feedthrough do not present a problem because they are common-mode signals to all pixels of the array.

Although exemplary embodiments of the invention are described above in detail, this does not limit the scope of the invention, which can be practiced in a variety of embodiments.