Demodulator circuit and method of tuning

This invention is related, in general, to demodulation circuits and, more specifically, to Frequency Modulation (FM) and Frequency-Shift Keying (FSK) demodulation circuits.

Many portable communication products utilize circuits that can perform well in a low power environment. The communication products have a front-end receiver designed for cellular or personal communications service (PCS) that converts a Radio Frequency to Intermediate Frequency (RF-to-IF). The information encoded in the signal received in a two-way communication link by the receiver in these handheld devices is recovered using demodulator circuits. The receiver typically integrates Low Noise Amplifiers (LNAs), quadrature phase shift networks and mixers for down converting the received signal from RF to IF and a demodulator for producing the recovered output signal. The recovered signal is proportional to the deviation of the frequency of the received signal relative to the center frequency of an oscillator found in the demodulator circuit. The receiver may operate in the 800-900 MHz cellular band and the 1800-1900 MHz PCS band, as well as other frequency bands.

A problem associated with most prior art FM demodulator circuits is the variation in output amplitude and bandwidth with process and temperature. One type of demodulator, i.e., the quadrature demodulator, generates an output signal having an amplitude that varies with the gain and bandwidth that varies with a phase shift network and with the input signal level. Another type of demodulator, i.e., the phase-locked loop demodulator, generates an output signal having an amplitude that varies with the input signal level, as well as capacitor values and resistor values that determine the gain of the VCO. Prior art injection-locked demodulators also generate an output signal that varies in amplitude depending upon capacitor and resistor values. The bandwidth of these types of prior art demodulators is not constant, but varies either with component values or the loop filter, or both.

Hence, there exists a need for a demodulation circuit that produces a recovered output signal that is less sensitive to amplitude variations in the received input signal and has a well-defined locking range and bandwidth.

The sole FIGURE is a circuit diagram of an integrated demodulator circuit.

The sole FIGURE is a circuit diagram for an integrated demodulator circuit 10 integrated on a semiconductor wafer. Demodulator circuit 10 is used in portable communication products having a front-end receiver that converts a Radio Frequency to Intermediate Frequency (RF-to-IF). Demodulator circuit 10 includes an oscillator 12 having transistors 18 and 20 connected as a differential transistor pair. The collector of transistor 18 is coupled through a current source 24 and the collector of transistor 20 is coupled through a current source 26 to a power conductor that receives the operating voltage V cc . Current sources 24 and 26 conduct equal currents and track changes in the currents conducted by current sources 28 and 44 such as to provide a constant average Direct Current (DC) voltage on a capacitor 22 . Capacitor 22 is connected between the collectors of transistor 18 and 20 . Current sources 24 and 26 both conduct a current that is labeled in the FIGURE as the sum of two current, i.e., current (I 0 +I B ). The emitters of transistors 18 and 20 are connected together and further coupled to the ground power conductor through a controlled current source 28 . Current source 28 provides the tail current of 2 I 0 for oscillator 12 . An Automatic Frequency Control (AFC) signal is supplied at input terminal 36 for adjusting the current 2 I 0 that is conducted by current source 28 .

Demodulator circuit 10 also includes an injection circuit 14 having differential connected transistors 40 and 42 . Injection circuit 14 is also referred to as a variable gain amplifier. The collector of transistor 40 is connected to the collector of transistor 18 and the collector of transistor 42 is connected to the collector of transistor 20 . The emitters of transistors 40 and 42 are connected together and further coupled through a controlled current source 44 to the ground power conductor. The AFC signal also adjusts the tail current 2 I B that is conducted by current source 44 .

A phase detector 16 in demodulator circuit 10 includes transistors 46 and 48 that form one differential transistor pair and transistors 56 and 58 that form another differential transistor pair. The commonly connected collectors of transistors 46 and 58 are coupled through a resistor 54 to the power conductor receiving the operating voltage V CC . The commonly connected collectors of transistors 48 and 56 are coupled through a resistor 55 to the power conductor receiving the operating voltage V CC . A signal V 0 supplied at terminals 38 is the differential signal generated by the current I D in resistors 54 and 55 . Resistors 54 and 55 each have resistance values of R L /2. The emitters of transistors 46 and 48 are connected together and further connected to the collector of a transistor 50 . The emitters of transistors 56 and 58 are connected together and further connected to the collector of a transistor 60 . Transistors 50 and 60 form a differential transistor pair having commonly connected emitters that are coupled through a current source 52 that conducts a current of 2 I D to the ground power conductor. The base terminals of transistors 40 and 50 are connected to each other, the base terminals of transistors 42 and 60 are connected to each other, and further connected to terminals 34 for receiving the signal IF.

Oscillator 12 includes a hysteretic comparator 30 coupled for comparing the differential signals generated across capacitor 22 . Comparator 30 has first and second outputs for supplying a differential output signal. One differential signal is supplied to the base terminal of transistor 18 in oscillator 12 and to the base terminals of transistors 46 and 56 in phase detector 16 . The other differential signal is supplied to the base terminal of transistor 20 in oscillator 12 and to the base terminals of transistors 48 and 58 in phase detector 16 .

In operation, the differential output signals provided to comparator 30 causes the comparator output to change state when the voltage at a first input reaches an upper trip value and the voltage at the second input reaches a lower trip value. The hysteresis in comparator 30 maintains that output state until the voltage at a first input reaches the lower trip value and the voltage at the second input reaches the upper trip value. Upon reaching these new trip values, the output of comparator 30 switches to the opposite state and maintains that opposite state until the input voltages of comparator 30 again cycle to the opposite trip values.

The output state of comparator 30 is fed back to transistors 18 and 20 of oscillator 12 and to transistors 46 , 48 , 56 and 58 of phase detector 16 . Phase detector 16 compares the phase of the output state with the phase of the input signal IF. The signal IF has a modulated input frequency, and normally, the signal IF and the output state have a quadrature relationship with respect to each other, i.e., the phase of the signal IF differs from the phase of the output state by 90°. Phase detector 16 generates an output signal V 0 having an average value of zero when the signal IF is in quadrature with the output state. On the other hand, when the input signal IF is not in quadrature with the output state, phase detector 16 generates an output signal V 0 having a non-zero value. Another circuit (not shown) receives the non-zero signal V 0 and adjusts the AFC signal presented back to demodulator circuit 10 that bring the signal IF and the output state into a quadrature relationship.

The signal V 0 provided at terminals 38 is determined as follows:

V 0 =R L I O ( I D /I B )(Δ f/f C )

where R L is the equivalent resistance at output terminals 38 , I O is a current in oscillator 12 , I D is a current in phase detector 16 , I B is a current in injection circuit 14 , Δf is the frequency deviation from the nominal carrier frequency, and f C is the nominal carrier frequency.

It should be pointed out that the current I B tracks the current I O and the product of R L I D is a function of an accurate voltage reference. Therefore, the output amplitude of the signal V 0 is a well-defined output amplitude.

The bandwidth of demodulator circuit 10 is given by:

B= 2/π( I B /I 0 ) f C

Again, with the current I B tracking the current I O the bandwidth of demodulator circuit 10 is well-defined as a simple function of the nominal carrier frequency f C and the locking range is given by the product of (2/π) B, where B is the bandwidth.

By now it should be appreciated that a demodulator circuit has been described that provides a well-defined locking range, bandwidth, and baseband output amplitude.