Demodulator and method for second harmonic cancellation

This invention is related, in general, to signal conversion and, more specifically, to signal conversion using a demodulator circuit.

Portable communication products require circuits that can perform well in a low power environment. A reduction of power supply voltages allows for fewer battery cells, reducing the size and weight of the portable equipment. However, the lower power constraint adversely affects the performance of standard RF circuitry. Circuits are needed that can achieve the design goals for noise figure, linearity and power consumption for portable communications products.

In a two-way communication link, the receiver in the portable communication products includes low-noise amplifiers and mixers. The receiver down-converts the received signal in frequency from the Radio Frequency (RF) range to the Intermediate Frequency (IF) range. The output signal generated by the mixer has a frequency that is the difference between the frequency of the received RF signal and the frequency of a local oscillator signal, thus converting the received RF signal to an IF signal.

A demodulator receives the IF signal, demodulates it to baseband and filters the baseband signal. Demodulation usually involves passing the signal through a frequency-dependant phase shift circuit, then comparing the output signal with the original signal in a phase detector or multiplier. The nominal phase shift is 90 degrees, so the nominal output signal from the phase detector is a square wave at twice the input frequency and commonly referred to as the harmonic. Deviations in input frequency produce deviations from phase quadrature which show up as changes in the mark-to-space ratio of the output signal which can be filtered to provide the baseband signal.

However, filtering the unwanted harmonic signal can be difficult under conditions where the amplitude of the unwanted signal is greater than the amplitude of the wanted signal. Accordingly, a need exists for a demodulator in a receiver circuit that generates an output signal having the modulation information while cancelling the unwanted harmonic information.

FIG. 1 is a block diagram of an integrated injection-locked demodulator circuit that cancels the twice-IF signal while retaining the modulation information; and

FIG. 2 is a plot of waveforms for the demodulator circuit of FIG. 1 .

FIG. 1 is a block diagram of an integrated injection-locked demodulator circuit 10 having harmonic cancelling. Demodulator circuit 10 can be used for personal communications service or in a cellular phone, among other uses. Demodulator circuit 10 receives a differential signal IF at input terminal 12 and generates a signal OUT at terminal 32 that cancels the twice-IF signal while retaining the modulation information of the IF signal. Demodulator circuit 10 includes an oscillator circuit 14 having an input connected to terminal 12 for receiving the signal IF and an output for supplying the signal OSC. Oscillator circuit 14 has another input for receiving an Automatic Frequency Control (AFC) signal.

A phase shift circuit 18 has an input connected to the output of oscillator circuit 14 for receiving the signal OSC. Phase shift circuit 18 generates an output signal OSC SHIFTED that is phase shifted by 90° from the signal OSC. Demodulator circuit 10 further includes a multiplier 22 having inputs connected for receiving the signals OSC and OSC SHIFTED. Multiplier 22 generates a signal 2 IF that has a frequency that is two times the frequency of the signal OSC. A multiplier circuit 24 receives the signals IF and OSC and generates an output signal PD. A summing circuit 30 receives the signals PD and 2 IF and provides a summed output signal OUT at terminal 32 .

FIG. 2 is a plot of the signal IF and the waveforms generated by the circuits shown in demodulator circuit 10 of FIG. 1 . In FIG. 2 the horizontal axis represents time and the vertical axis represents signal amplitude. Referring to FIGS. 1 and 2, waveform 34 illustrates the signal IF received by demodulator circuit 10 at input terminal 12 . Waveform 36 corresponds to the signal OSC generated by oscillator circuit 14 in response to receiving the signal IF. Waveform 38 corresponds to the signal OSC SHIFTED generated by phase shift circuit 18 in response to receiving the signal OSC. Waveform 40 corresponds to the signal 2 IF generated by multiplier 22 in response to receiving the signals OSC and OSC SHIFTED. The lines labeled t 0 , t 2 , t 3 , and t 5 in FIG. 2 show several of the times at which transitions of the signal 2 IF occur. Waveform 42 corresponds to the signal PD generated by multiplier circuit 24 in response to receiving the signal IF. The lines labeled t 1 and t 4 show several of the times at which transitions of the signal PD occur. Waveform 44 corresponds to the signal OUT generated by summing circuit 30 in response to receiving the signals PD and 2 IF.

In operation, demodulator circuit 10 receives the baseband signal IF (waveform 34 in FIG. 2 ). Oscillator circuit 14 is frequency locked to the signal IF to generate the signal OSC (waveform 36 in FIG. 2) and phase shift circuit 18 uses the signal OSC to generate the quadrature signal OSC SHIFTED (waveform 38 in FIG. 2 ). When the free-running frequency of oscillator circuit 14 is tuned to the frequency of the signal IF, the signal OSC has a quadrature relationship with respect to the signal IF. In other words, the phase of the signal OSC is shifted by 90° with respect to the phase of the signal IF. The filtered output of the demodulator with an unmodulated input IF signal will then be zero. Tuning may be done with an Automatic Frequency Control (AFC) circuit.

Phase shift circuit 18 generates the output signal OSC SHIFTED that is phase shifted from the signal OSC by 90°. Multiplier 22 receives the signals OSC and OSC SHIFTED and generates the signal 2 IF (waveform 40 in FIG. 2) having a frequency twice that of the signal OSC. Multiplier circuit 24 receives the signals IF and OSC and generates an output signal PD (waveform 42 in FIG. 2 ). A summing circuit 30 receives the signals PD and 2 IF and provides a summed output signal OUT 2 (waveform 44 in FIG. 2) at terminal 32 .

Referring to FIG. 2, at time t 0 the signal PD transitions from a high value to a low value and the signal 2 IF transitions from a low value to a high value. The signal OUT remains at a low value when the signals 2 IF and PD transition at the same time. At time t 1 the signal PD transitions from a low value to a high value. At a latter time, i.e., time t 2 , the signal 2 IF transitions from a high value to a low value. When the signals 2 IF and PD transition at different times, the signal OUT from summing circuit 30 transitions from a low value to a high value and remains at that high value until the lagging signal transitions. At time t 3 the signal PD transitions from a high value to a low value and the signal 2 IF transitions from a low value to a high value. Again, since both of the signals 2 IF and PD transition at the same time, the signal OUT remains at a low value. On the other hand, the signal OUT transitions from a low value to a high value at time t 4 and remains at that high value until time t 5 because the signal PD makes a transition at time t 4 and the signal 2 IF makes a transition at time t 5 .

In operation, demodulator circuit 10 receives the signal IF and uses it to lock the signal OSC in oscillator 14 to the same frequency as the signal IF. Phase shift circuit 18 generates the signal OSC SHIFTED that is in quadrature with the signal OSC. Both of the signals OSC and OSC SHIFTED are multiplied in multiplier 22 and the output signal 2 IF has twice the frequency of the signal OSC. It should be noted that the signal 2 IF has a fifty percent duty cycle, i.e., a mark/space ratio of one. It should be noted that the signal 2 IF is a square wave having the same amplitude as the signal IF, but a frequency that is two times the frequency of the received signal IF. Multiplier circuit 24 also receives the signal IF and along with the signal OSC generates an output signal PD that indicates when the signal IF is in-phase with the signal OSC. The signal 2 IF is in antiphase with the signal PD. By summing the signals PD and 2 IF in summing circuit 30 , the signal OUT provided at terminal 32 has a non-zero value when the received signal IF deviates in phase quadrature from the signal OSC. The signal OUT has a zero value when the signals IF and OSC are in phase quadrature.

By now it should be appreciated that a demodulator tuning circuit has been shown for use in a receiver circuit that generates an output signal having the modulation information while cancelling the unwanted second harmonic information.