High impedance mirror scheme with enhanced compliance voltage

This invention relates generally to regulated current sources and more particularly to a high-impedance current source having an enhanced compliance voltage.

In today's analog low-voltage circuits it is desirable to provide enhanced current source functionalities such as the biasing of differential pairs with high impedance current sources. Current mirrors can be used to provide such enhanced functionalities. Current mirrors replicate at their outputs the currents present at their inputs and are widely used in the electronics industry. There are many variations of the basic current mirror that may provide such functionalities. Regular cascode, high-swing cascode, regulated cascode, low voltage current, and active-input regulated cascode mirrors are some of the known current source solutions utilized in the electronics industry to provide biasing of differential pairs. Mirroring functionality is quite useful in many circuit applications such as a regulated current source for transconductance amplifiers and high-speed digital receivers. A basic current mirror is illustrated in FIG. 1 .

The basic current mirror 10 comprises two p-channel MOS transistors M 11 and M 12 having their gates 11 and 12 connected together and their sources 13 and 14 connected to a supply voltage V DD . To optimize the operation of the current mirror 10 , transistors M 11 and M 12 are biased to operate in the saturated region on or near the boundary between the linear and saturated regions, that is, the output characteristic is: V DS =V GS −V T

where

V DS =drain to source voltage

V GS =gate to source voltage

V T =threshold voltage

In this configuration, a source-drain current of a MOS transistor has a positive dependence upon not only the gate voltage but also the source-drain voltage in the saturated region. If the source-drain voltage increases and the gate voltage is maintained at a constant level, the source-drain current correspondingly increases. This phenomenon is called “Early effect”. Early effect can be reduced by increasing the length of the PMOS transistors M 11 and M 12 . The dependence of source drain voltage is responsible for the very low output resistance of this configuration. The current mirror circuit of FIG. 1 has been employed in current sources in the prior art.

FIG. 2 shows a regular cascode current mirror 20 . With the regular cascode mirror 20 , a current I in from the current source 27 flows through transistor M 3 , and a corresponding gate-source voltage appears between gate 27 and source 35 of the transistor M 3 . This gate-source voltage is determined in accordance with the characteristics of transistor M 3 and by the current I in supplied from the constant current source 27 . The current through transistor M 2 mirrors the current through transistor M 1 . Likewise the current through transistor M 4 mirrors the current through transistor M 3 . By adjusting the relative dimensions of transistors M 1 and M 2 and of transistors M 3 and M 4 , a desired output current can be achieved.

This regular cascode current mirror 20 is a well-known scheme that enhances the output impedance of the circuit. However, it suffers from a lack of headroom, i.e., it begins to operate several 100 mv above the threshold voltage of a PMOS transistor, thus lowering the operating headroom left to other circuitry operations.

FIG. 3 illustrates a high-swing cascode current mirror 40 . For the same output impedance as the regular cascode current mirror 20 , the dynamics are improved. By a careful design of the cascode bias circuit, the need of at least one threshold voltage at the output is avoided. Nevertheless, both of the transistors in the output branch have to be in saturation mode.

Referring now to FIG. 4 there is shown a prior art regulated current mirror 50 . This scheme uses feedback circuitry that controls the drain source voltage of the MOS transistor M 2 . Its output resistance is therefore multiplied by the feedback gain factor and will be one order of magnitude higher than a usual cascode scheme.

A low-voltage current mirror 60 is illustrated in FIG. 5 . In this scheme if it is assumed that MOS transistors M 1 and M 2 have similar transconductance and output resistance, it can be shown that the output resistance is equal to the resistance of the current source driving transistor M 1 (R 1 In ). Using this technique, the output resistance can be high and the compliance voltage is very low. However, an active part or operational transconductance amplifier (OTA) is required.

FIG. 6 illustrates an active-input regulated cascode current mirror 70 . This mirror scheme requires two OTAs. Compliance voltage and output resistance are increased due to feedback. However, if performance, consumption and cost are considered, it does not appear as a good solution.

The above describe prior art solutions that have various disadvantages including lack of headroom, constrained operating characteristics, poor dynamics, and the need for controllable resistance devices (OTAs). What is needed then is a high-impedance current source which has a low compliance voltage, enhanced operating characteristics and dynamics, and which eliminates the need for OTAs.

These problems are generally solved, and technical advantages are generally achieved, by preferred embodiments of the present invention comprising a high impedance current source circuit having an enhanced compliance voltage. The current source circuit comprises an input circuit coupled to a first current mirror stage. A means for generating a biasing current produces a biasing current that is input into the input circuit. The first current mirror stage is in turn coupled to a second current mirror stage which acts as a feedback circuit. A stabilization circuit and output circuit which provides an output current are also included.

In one specific embodiment of the present invention, the first current mirror stage comprises a first transistor coupled to a second transistor; the second current mirror stage comprises a third transistor coupled to a fourth transistor; the stabilization circuit comprises a fifth transistor coupled to a sixth transistor, wherein the stabilization circuit is coupled between the first and second current mirror stages; and the output circuit comprises a seventh transistor connected to the stabilization circuit between the first and second current mirror stages.

The present invention also discloses a method for mirroring a current in the above embodiment of the present invention. The method comprises generating the biasing current; converting the biasing current into a gate voltage on the first, second, fifth, and sixth transistors; fixing the voltage across the fourth transistor whereby the percentage of current flowing through the sixth transistor and the fourth transistor is equal to the current flowing from the second transistor; and delivering a fixed current to the sixth and seventh transistors, whereby the voltage of said fifth transistor is substantially controlled to produce a stable output current.

An advantage of the preferred embodiment of the present invention is that the circuit has a low compliance voltage or point at which the circuit will operate. The low compliance voltage is due to the feedback operation included in the present invention. This low compliance voltage allows headroom for other circuitry operations.

Another advantage of the preferred embodiment of the present invention is that it is suitable for biasing wide common mode range differential pairs.

A further advantage of the preferred embodiment of the present invention is that the need for an active part or OTA is eliminated.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

The above features of the present invention will be more clearly understood from consideration of the following descriptions in connection with accompanying drawings in which:

FIG. 1 illustrates a basic current mirror;

FIG. 2 illustrates a prior art current mirror in the form of a regular cascode current mirror;

FIG. 3 illustrates a prior art regulated cascode mirror scheme;

FIG. 4 illustrates a prior art high swing cascode current mirror scheme;

FIG. 5 illustrates a prior art low voltage current mirror scheme;

FIG. 6 illustrates a prior art active-input regulated cascode current mirror scheme;

FIG. 7 is a block diagram of the present invention;

FIG. 8 illustrates one embodiment of the present invention;

FIG. 9 shows the equivalent small-signal circuit of the one embodiment of the present invention;

FIG. 10 illustrates another embodiment of the present invention;

FIG. 11 is a simple block diagram of a high-speed digital receiver utilizing an embodiment of the present invention; and

FIG. 12 shows the DC current versus the output voltage of the present invention.

Referring to the figures, FIG. 7 is a block diagram of the present invention, wherein a current source 80 comprises an input circuit 82 , a first current mirror stage 84 , a second current mirror stage 86 , a stabilization circuit 88 , and an output circuit 90 . The input circuit 82 provides a biasing current for the current mirror 80 . The biasing current for the current mirror 80 may be applied in several ways which include, but are not limited to, utilizing external circuitry which resides on a medium (e.g. fabricated chip) different from that of the current mirror 80 to supply the biasing current, utilizing a current generator resident on the same medium, or using a resistor with a supplied voltage.

The first current mirror stage 84 converts the biasing current to a gate voltage for the stabilization circuit 88 which delivers a fixed current to the output circuit 90 . The stabilization circuit 88 offsets variations in the output voltage that in turn cause variations in the regulated output current. The second current mirror stage 86 is interfaced with the first current mirror stage 84 and the stabilization circuit 88 to function as a feedback circuit. The output circuit 90 provides the regulated output current.

In FIG. 8 there is shown a preferred embodiment of the present invention wherein seven transistors are used to provide the high-impedance, low-compliance characteristics of the innovative current source 100 . MOS transistors, M 6 and M 1 form the first current mirror stage. Transistors M 6 and M 1 include gates, 104 and 106 respectively, which are tied together, and sources, 108 and 110 respectively, which are connected to a voltage source 102 . Gates 104 and 106 are tied to the drain of transistor M 6 and to bias current source 105 . Current source 105 provides the gate voltage for gate 106 of transistor M 1 . The stabilization circuit comprises MOS transistors M 3 and M 4 . When the gate voltage at M 1 is generated, the transistor M 1 generates a biasing current for the second current mirror stage, which comprises MOS transistors M 2 and M 5 . Transistors M 2 and M 5 include gates, 112 and 114 respectively, which are tied together and drains 116 and 118 , respectively, which are connected to a ground 120 . The output circuit comprises a MOS transistor M 7 .

In operation, the transistor M 3 will deliver a fixed current if its drain voltage is fixed to a stable value. In this circuit, this drain voltage is determined by transistor M 4 in sub-threshold mode. By a careful design, the saturation of transistor M 3 can still be guaranteed even if both transistors M 3 and M 4 are tied to the same gate. This can be achieved by a high W/L ratio of transistor M 4 and setting a very low drain current on transistor M 4 . If the drain voltage of transistor M 3 decreases (as a result of an increase in the output voltage V out ), the current through transistor M 4 will diminish. This results in less current through the second current mirror stage comprised of transistors M 2 and M 5 . The decreased current through transistor M 2 causes the voltage at node V 3 to increase and hence to increase at the gate of output transistor M 7 as well. This increase in gate voltage decreases the current flow through transistor M 7 , thus offsetting the effects of the increased output voltage. Therefore, any change on the drain of transistor M 3 due to the variation of the output voltage will be offset by operation of the second current mirror stage. Likewise, a decrease in the output voltage will be fed back through the second current mirror stage via transistor M 4 and will result in a decreased gate voltage on transistor M 7 . The decreased voltage on transistor M 7 allows for increased current flow through transistor M 7 .

Quantitatively, the current is mainly determined by the mirror ratio between MOS transistors M 1 , M 6 , and M 3 . As explained above, the very high stability in the output current I out is obtained by tightly controlling the drain voltage of transistor M 3 , i.e. V 2 . Deriving a small part of the drain current of transistor M 3 in a 1:1 NMOS second current mirror stage, comprised of transistors M 5 and M 2 , provides the tight control of V 2 .

When the circuit is in balance, the percentage of transistor M 3 drain current flowing though transistors M 4 and M 5 is equal to the drain current of transistor M 1 . To get transistor M 3 in saturation mode, this percentage and the size of M 4 has to be chosen in such a way transistor M 4 operates in the weak inversion region or in sub threshold mode. This means the current ratio between transistors M 3 and M 1 has to be very high to avoid excessively large dimensions for transistor M 4 .

This scheme will fix the voltage V 2 at the beginning of the saturation mode for transistor M 3 and it will ensure a current proportional to the aspect ratios in transistors M 6 , M 1 , and M 3 .

The drain current of M 1 can be written as: I 1 = n p  β 1 2  Vp12 = n p  β 1  C ax ( W 1 L 1 ) 2  V 1 2 ( 1 )

where V p1 ≅  V G1  -  V T p  n p

is the pinch-off voltage or the voltage for which transistor M 1 leaves its saturation region.

V T p is the threshold voltage for PMOS and n p is the slope factor of the gate voltage versus the pinch-off. Similarly the drain current of transistor M 3 in saturation is: I 3 = n p  β 3 2  Vp12 ( 2 )

This is valid as long as:

|V DS3 |=V DD −V 2 ≧V p1   (3)

If we assume transistor M 4 is in the weak inversion region, then its drain current will have an exponential characteristic: I 4 = 2  n p  β 4  U T 2  exp  ( V p1 - V DD + V 2 U T ) ( 4 )

where U T is the thermal voltage kT/q. It can be seen that if I 4 ((2n p β 4 U T 2 , the argument of the exponential will be negative and the condition ( 3 ) can be met. This also means that the shape factor (W/L) of transistor M 4 has to be very large and/or its drain current I 4 has to be very small. Due to the high gain from the source of transistor M 4 to the gate of transistor M 7 , this node is kept at a level such that: I out = I 3 - I 1 = n p  β Γ 2  ( V p3 - V DD + V 2 ) 2 ( 5 ) where     V p3 ≅  V G7  -  V T p  n p = V DD - V 3 -  V T p  n p ( 6 )

Should the node V 2 vary in one direction due to early effect in transistors M 7 or M 3 , then the small current of transistor M 4 should change in the same direction, leading to an opposite variation on the gate of transistor M 7 . This would stabilize the change. The high output impendence can be demonstrated with an equivalent small-signal circuit as shown in FIG. 9 .

Referring to FIG. 9, if the current sums are written for all the nodes, the following equations can be derived: ( g m2 0 g ds1 + g ds2 - g ds4 g ms4 + g ms7 + g ds3 + g ds4 + g ds7 - g m7 g m5 + g ds5 + g ds4 - g ms4 - g ds4 0 )  ( v 1 v 2 v 3 ) = ( 0 g ds7 0 )  v out ( 7 )

In addition, the output current can be expressed as: i out = ( 0 - ( g ms7 + g ds7 )  g m7 )  ( v 1 v 2 v 3 ) + g ds7  v out ( 8 )

where g ms4 =g m4 +g mb4

If some simplifications are done, i.e. if output conductance is neglected versus transconductance, an approximate formula can be derived for the tail current source output resistance: R out = v out i out ≅ ( 1 g ds7 )  ( g m2  g ms4  g m7 ( g ds1 + g ds2 )  ( g ms4 + g ds3 )  g m5 ) ( 9 )

The output resistance of transistor M 7 is in fact multiplied by two dominant gain terms: ( g m2 g ds1 + g ds2 ) ,

which can be one or several decades, and ( g m7 g m5 ) ,

which is also important due to the significant ratio between the current flowing in transistor M 7 and the one that is mirrored in transistors M 5 and M 2 . This leads to an output resistance that can be as high as several megaohms.

Another parameter has to be considered: the compliance voltage (or the minimum output voltage Vout for which the circuit still performs properly):

(V out ) min =|V DS sat3 |+|V DS sat7 |  (10)

The presence of any threshold voltage in the above equation does not penalize this scheme. This voltage can be as low as 400-600 mV in all voltage, temperature, and process conditions.

FIG. 10 illustrates another embodiment of the present invention. In this current mirror scheme, the W/L ratio of transistors M 6 , M 3 and M 1 better control the ratio between the biasing current and output current. The addition of transistors M 8 and M 9 allows transistors M 6 and M 1 to be set in the same voltage conditions as transistor M 3 . This is true, however, if the size ratio between transistors M 6 and M 9 , M 1 and M 8 and M 3 and M 4 are all identical.

FIG. 11 is a simple block diagram of a high-speed digital receiver 120 utilizing an embodiment of the present invention. A biasing current I BIAS is input to the current source circuit 122 of the present invention. The current source circuit 122 provides a regulated current I o to a differential pair stage 124 utilizing PMOS transistors. The differential pair stage 124 is provided a positive input and a negative input which results in an output to a folded cascode output stage 126 . The operation of the folded cascode output stage 126 results in an output current I out .

In FIG. 12 is shown the DC current versus the output voltage of the above described preferred embodiments. The results were obtained using 0.18 μm effective length CMOS technology with 3.3V transistors. The curve is very horizontal and the output impedance is around 10 Mohm for an output current of 230 μA. The second current mirror stage comprising transistors M 2 and M 5 has a ratio of 2:1. The transistors M 6 , M 1 , and M 3 have a 1:1:21 ratio. About half of the current flowing into transistor M 1 flows into transistor M 4 . For this technology, the product ILIM sq=2n p β p U T 2 for a square PMOS transistor is equal to 100 nA. This means that the saturation condition (3) will be met with a very large transistor. Assuming an input current of 12 μA is applied to transistor M 6 , a reasonable size for transistor M 4 is 400 um/0.9 um. The drain current of transistor M 4 (6 μA) will be around 13% of 100 nA×400/0.9 and the sub threshold mode can therefore be guaranteed. The spread versus temperature, process and supply voltage is rather small as shown by the proximity of the curves. Moreover, the flat part of the curves begins as low as 400 mV.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.