VCO gain self-calibration for low voltage phase lock-loop applications

The present invention relates to electronics, and specifically to phase-lock loop circuits.

A phase-lock loop (PLL) is a circuit that generates a periodic output signal having a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. A typical PLL incorporates a voltage-controlled oscillator (VCO). A VCO is a device that generates a periodic output signal having a frequency that is a function of the VCO input voltage. VCOs are typically designed to operate over a wide range of application frequencies, and over a wide range of process and temperature variation. Of particular interest are the VCO operating characteristics of frequency range and gain.

In order to span a wide range of operating frequencies, a common practice is to increase VCO gain, K O . However, the larger the K O , the larger the sensitivity of the VCO to its input modulation noise, which includes charge pump noise, loop filter noise, and ripple noise. The ripple noise is due to the possible mismatching between the charge pump up and down currents and the charge sharing effect. PLL jitter can be reduced by decreasing the gain of the VCO, K O , while increasing the charge pump current at the same time, if charge pump up and down currents are well matched.

One approach of reducing K O while at the same time spanning a wide frequency range is to break a wide range tuning curve into a number of narrower, overlapping range sections as described in U.S. Pat. No. 5,942,949, issued to Wilson et al. However, in deep submicron processes, the VCO gain can have a relatively high dependence on the process due to the variation in resistor, capacitor and transistor threshold voltages. Based on a simulation, it has been shown that K O can vary over processing by a factor of 8:1. The variation is also greatly influenced by the VCO structure and targeted frequency range. The conventional center frequency auto-calibration scheme, as described in U.S. Pat. No. 5,942,949, fails to limit the variation of K O caused by the process variation and by the frequency range over which it operates. This K O variation problem may degrade the loop stability margin and jitter performance.

The present invention includes a process for calibrating gain of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) circuit. The VCO has a plurality of input voltage versus output frequency operating curves. The method includes a selecting one of the VCO operating curves and determining VCO gain using the selected operating curve. If the value of VCO gain is not within a predetermined range, the VCO gain is adjusted and the process of selecting an operating curve and determining VCO gain is repeated.

Another aspect of the present invention includes a PLL circuit having a VCO. The VCO receives a loop-filter voltage signal and provides a PLL output signal. The VCO also has a VCO gain and a VCO center frequency which are automatically calibrated during a calibration phase.

The invention is best understood from the following detailed description when read in connection with the accompanying drawing. The various features of the drawings are not to scale. On the contrary, the dimensions of the various features may arbitrarily be expanded or reduced for clarity. Included in the drawing are the following figures:

FIG. 1 (Prior Art) is a functional block diagram of a conventional charge-pump phase-lock loop (PLL);

FIGS. 2A and 2B are graphs depicting exemplary sets of VCO operating curves;

FIG. 3 is a functional block diagram of a self-calibrating PLL circuit in accordance with the present invention;

FIG. 4 is a functional block diagram of an exemplary embodiment of a VCO gain calibration portion of a phase-locked loop in accordance with the present invention;

FIG. 5 is a circuit diagram of an exemplary embodiment of a voltage to current conversion portion of a VCO in accordance with the present invention; and

FIG. 6 is a flow diagram of an exemplary process for calibrating a PLL circuit in accordance with the present invention.

FIG. 1 is a functional block diagram of a conventional charge-pump phase-lock loop (PLL). Phase/frequency detector (PFD) 2 compares the phase of the input signal, F IN to the phase of the feedback signal F FB and generates an error signal. The error signal is either an up signal or a down signal. An up signal indicate that the phase of F IN leads the phase of F FB . A down signal indicates that the phase of F FB leads the phase of F IN . The width of the error signal pulse indicates the magnitude of the difference between the phase of F IN and the phase of F FB .

Charge pump 4 generates an amount of charge equivalent (in magnitude and polarity) to the error signal provided by PFD 2 . Depending upon the polarity of the error signal (up or down), the charge is either added to or subtracted from the capacitors in loop filter 6 . Loop filter 6 operates as an integrator that accumulates the net charge from charge pump 4 . Loop filter 6 is exemplary, other, more sophisticated loop filters are also possible. The resulting loop_filter voltage, V LF , is applied to voltage controlled oscillator (VCO) 8 . PLL output signal, F OUT , is used to generate the feedback signal, F FB , for the PLL circuit in FIG. 1 .

Optionally, feedback divider 10 and input divider 12 may be placed in the feedback and input paths, respectively, if the frequency of the output signal, F OUT , is to be either a fraction or a multiple of the frequency of the input signal, F IN . The divide by value is a real number, thus, if no division is desired, a divide by value of one is implemented.

It is emphasized that the present invention is not limited to charge pump PLL's. Rather, the present invention may be implemented for almost any PLL having a phase/frequency detector, an integrating loop filter, and a VCO.

FIGS. 2A and 2B are graphs depicting exemplary sets of VCO operating curves. VCO's are often designed for a wide range of applications (e.g., wide range of frequencies and gain). Accordingly, VCO's are often have a number of operating curves (i.e., input voltage versus output frequency). The frequency range of any one curve is only a portion of the total operating range of the VCO. For example, the operating frequency range for the VCO depicted in FIG. 2A ranges form f MIN to f MAX . Yet, the frequency range for the operating curve corresponding to L=000 ranges from f MIN to f 1 . A center frequency control signal, L, is used to select one of the operating curves. The process of selecting a VCO operating curve is often referred to as trimming.

For low noise PLL applications, it is advantageous to implement a VCO with a relatively low gain. VCO gain, K O , is defined as the ratio of output frequency over input voltage. Dividing values in hardware and software is well known in the art, accordingly determining VCO gain by dividing output frequency by input voltage may be accomplished by any such hardware or software technique. Relative gain may be determined by comparing the slopes of the operating curves. For example, the slopes of the set of operating curves in FIG. 2A is less than (i.e., less steep) the slopes of the set of operating curves in FIG. 2B, for all values of L. Thus, the gain of the VCO represented by FIG. 2B is greater than the gain of the VCO represented by FIG. 2 A. Also, note that the VCO gain, K O , may vary with the value of L for the same VCO. For example in FIG. 2B, K O for L=100 is less than K O for L=000. Further, it is not uncommon for a specific PLL application to be designed to operate within a specific frequency range. For example, an application may be designed to operate with a nominal output frequency of 100 MHz. This is accomplished by selecting a VCO operating curve having a center frequency close to the design nominal frequency.

A self trimming (i.e., self-calibrating) PLL circuit that automatically selects an appropriate VCO operating curve in order to meet operating frequency requirements, is described in U.S. Pat. No. 5,942,949 issued to Wilson et al. (hereinafter referred to as “Wilson et al.”). The Wilson et al. patent does not address automatic self-calibration of VCO gain, K O . As can be observed in FIGS. 2A and 2B, changing the value of L can also change the value of VCO gain, K O .

FIG. 3 is a functional block diagram of a self-calibrating PLL circuit in accordance with the present invention. The PLL circuit, generally designated 300 , comprises phase/frequency detector 20 , charge pump 22 , VCO 24 , input divider 36 , and feedback divider 38 , which are analogous to the corresponding components of the PLL in FIG. 1 . Additionally, circuit 300 comprises VCO center frequency calibration portion 26 , loop-filter portion 28 , VCO gain calibration portion 30 , and switches SW 1 and SW 2 . Circuit 300 automatically calibrates VCO 24 , during a calibration phase, by selecting an appropriate VCO operating curve and VCO gain, K O . Automatic calibration may occur when the PLL is powered on, or at in response to a calibration trigger signal. The selected VCO operating curve and VCO gain, K O , are used during normal operations.

During the calibration phase, switch SW 1 is open and SW 2 is closed. Accordingly, reference voltage, V REF , is provided to VCO 24 . During normal operations, SW 1 is closed and SW 2 is open, thus allowing loop-filter voltage, V LF , to be applied to VCO 24 . In one embodiment of the invention, the reference voltage, V REF , is the nominal center of the range of input voltages over which VCO 24 is designed to operate. In alternate embodiments of the invention, the functions of switches SW 1 and SW 2 are incorporated inside the VCO and controlled by any appropriate control signal.

In operation, during the calibration phase, state machine 32 generates a sequence of VCO center frequency control signals, L, which is provided to VCO 24 to sequentially select different VCO operating curves. The sequence of VCO center frequency control signals, L, is also provide to VCO gain calibration portion 30 . With reference voltage, V REF , applied to VCO 24 , for each VCO operating curve selected, VCO 24 generates an output signal, F OUT , having a constant frequency. Output signal, F OUT , is provided to frequency detector (FD) 34 . FD 34 also receives the input signal from divider 36 , R. FD 34 is analogous to PFD 20 , except that FD 34 detects a difference in frequency rather than phase. Thus, FD 34 generates up and down error signals, which are accumulated by state machine 32 . Because the frequency of F OUT provided to FD 34 is constant, FD 34 will eventually provide either a maximum up or down value to state machine 32 , depending upon whether the frequency of the feedback signal, V, is greater than or less than the frequency of the input signal at the output of divider 36 , R.

By purposefully selecting VCO center frequency control signals, L, state machine 32 may identify the two VCO operating curves that have center frequencies just above and just below the frequency of the input signal R. Either one of these two operating curves may be selected for use during normal PLL operations. In an exemplary embodiment of the invention, state machine 32 performs a linear search algorithm in which the values of the center frequency control value, L, are selected linearly starting at one end of the range of possible values (e.g., 0) and proceeding to the other end of the range until the error signal provided by FD 34 changes polarity. In an alternative embodiment of the invention, during step 58 , a binary search algorithm is performed such that each new value of L is selected midway between two previously selected values that yielded opposing error signal values, until two consecutive values of L are detected that yield opposing error signal values.

After the first iteration of VCO center frequency calibration is completed, VCO gain, K O is calibrated. VCO center frequency signal, L, is provided to the VCO gain calibration portion 30 . VCO gain calibration portion 30 uses this value of L to determine the value of VCO gain, K O , for the corresponding operating curve. VCO gain, K O , is determined by comparing L to a preset corresponding value of K O . Thus, VCO gain calibration portion 30 is programmed with corresponding values of L and K O for determining if K O is within a desired range. If the value of K O is not within preset limits, VCO gain calibration portion 30 provides VCO 24 with a VCO gain calibration signal, K for adjusting K O . When K O changes, the center frequency also changes, thus center frequency calibration is then restarted using the latest value of K. The process is repeated until satisfactory values of L and K O are obtained.

Once the calibration phase is complete, switches SW 1 is closed and SW 2 is opened to enable normal PLL operations using the VCO operating curve and value of VCO gain selected during the calibration phase.

In the embodiments of the invention described herein, signals L and K are digital signals, and VCO 24 comprises a digital to analog converter for converting L to an analog signal. In alternate embodiments of the invention, a digital to analog converter, separate from VCO 24 , converts L to an analog signal prior to being provided to VCO 24 .

FIG. 4 is a functional block diagram of an exemplary embodiment of a VCO gain calibration portion of a phase-locked loop in accordance with the present invention. Decoder 40 receives the VCO center frequency calibration signal, L. Upon receiving trigger signal 48 , decoder 40 decodes L to determine if K O is within range. Trigger signal 48 indicates that an iteration of automatic VCO center frequency calibration has completed. Decoder 40 is preset with predetermined values of L which are used to determine if L is in range. Thus, for example, if a value of L indicates that K O is too high (by comparing to the preset values) decoder 40 provides D flip-flops 42 with a decoder output signal. This decoder output signal is also provided to edge detector 46 . Responsive to the decoder output signal sent by decoder 40 , edge detector 46 sends a restart signal to restart the VCO center frequency calibration process. Each time the D flip-flops 42 receive a decoder output signal from decoder 40 , the value of K, which is sent to VCO 24 , is incremented. K<0> corresponds to bit zero of the digital word K, and K<1> corresponds to bit one of the digital word K.

Signal, K, adjusts the gain of the VCO 24 . FIG. 5 is a circuit diagram of an exemplary embodiment of a voltage to current conversion portion of a VCO in accordance with the present invention. In FIG. 5, transistor, M 1 , and resistor, R 1 , provide voltage-controlled transconductance. The gain of a VCO is proportional to transconductance. When K<0> in FIG. 5 is equal to a digital value of one, inverter 50 provides a digital value of zero to transistor M 3 . This decreases the value of transconductance by increasing the resistance between node C and ground. Further, transistor M 4 is turned on, which causes more current to flow through transistors M 2 and M 4 to ground. Therefore, less current is provided to the current-controlled oscillator (ICO) portion of VCO 24 . Accordingly, the gain of VCO 24 is decreased. The circuit shown in FIG. 5 may be replicated to accommodate each bit of the digital word K.

FIG. 6 is a flow diagram of an exemplary process for calibrating a PLL circuit in accordance with the present invention. The flow diagram in FIG. 6 is described with reference to FIGS. 3 and 4. At power up, or responsive to a calibration signal, as shown in step 54 , VCO center frequency calibration is performed. During step 56 , switches SW 1 is opened and SW 2 is closed. In this calibration switching configuration, V REF is provided to VCO 24 .

VCO Center frequency calibration is performed in step 58 . During this portion of the process, state machine 32 generates a sequence of VCO center frequency control signals, L, which is provided to VCO 24 to sequentially select different VCO operating curves. With reference voltage, V REF , applied to VCO 24 , for each VCO operating curve selected, VCO 24 generates an output signal, F OUT , having a constant frequency. Output signal, F OUT , is provided to frequency detector (FD) 34 . FD 34 also receives the input signal from divider 36 , R. FD 34 is analogous to PFD 20 , except that FD 34 detects a difference in frequency rather than phase. Thus, FD 34 generates up and down error signals, which are accumulated by state machine 32 . Because the frequency of F OUT provided to FD 34 is constant, FD 34 will eventually provide either a maximum up or down value to state machine 32 , depending upon whether the frequency of the feedback signal, V, is greater than or less than the frequency of the input signal at the output of divider 36 , R.

The desired frequency of the VCO output signal, F OUT , is the frequency of the input signal R. By purposefully selecting VCO center frequency control signals, L, state machine 32 may identify the two VCO operating curves that have center frequencies just above and just below the frequency of the input signal R. Either one of these two operating curves may be selected for use during normal PLL operations. In an exemplary embodiment of the invention, state machine 32 performs a linear search algorithm in which the values of the center frequency control value, L, are selected linearly starting at one end of the range of possible values (e.g., 0) and proceeding to the other end of the range until the error signal provided by FD 34 changes polarity. In an alternative embodiment of the invention, state machine 32 performs a binary search algorithm such that each new value of L is selected midway between two previously selected values that yielded opposing error signal values, until two consecutive values of L are detected that yield opposing error signal values.

After the first iteration of VCO center frequency calibration is completed, the present value of the digital control word, L, is provided to the VCO gain calibration portion 30 , in step 60 . Digital control word, L, is received by decoder 40 . This value of L is used to determine the value of VCO gain, K O , for the corresponding operating curve. VCO gain, K O , is determined by comparing L to a preset corresponding value of K O . Thus, VCO decoder 40 is programmed with corresponding values of L and K O for determining if K O is within a desired range.

VCO gain is determined and compared with preset limits in step 62 . As shown in steps 62 and 70 , if the value of K O is above a threshold value, VCO gain is reduced. In an alternate embodiment of the invention, VCO gain is checked to determine if it is below a threshold value (i.e., too low), and increased accordingly. During step 70 , VCO gain calibration portion 30 provides VCO 24 with a VCO gain calibration signal, K for adjusting K O . Another iteration of VCO center frequency calibration is then performed as indicated in step 58 . This process is repeated until satisfactory values of L and K O are obtained.

The values of L and VCO gain resulting from the calibration process are used during normal PLL operations, as indicated in step 64 . Switches SW 1 and SW 2 are configured for normal operations, as indicated in step 66 . That is, SW 1 is closed and SW 2 is opened. In step 68 , the calibrated PLL circuit is in normal operation. Thus, loop-back voltage, V LF , is provided to VCO 24 .

The present invention provides advantages over the PLLs of the prior art because the VCO is calibrated automatically to the appropriate operating curve and gain at power up. Reducing VCO gain, K O , variation through self-calibration helps maintain low variation in PLL bandwidth. This is important for stable loop dynamics. Reducing VCO gain also helps minimizes the output phase noise. In addition, because the VCO is not permanently calibrated, the PLL can be used for different applications operating at different nominal frequencies and gain values. Each time the PLL is powered up, the VCO will be calibrated to the current appropriate settings. In addition, the PLL automatic calibration operations may be repeated whenever an appropriate reset signal is applied to the PLL.

Although illustrated and described herein with reference to certain specific embodiments, the present invention is nevertheless not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the spirit of the invention.