Capacitance type digital/analog converter capable of reducing total capacitance

1. Field of the Invention

The present invention relates to a digital/analog (D/A) converter using capacitors.

2. Description of the Related Art

In order to decrease the occupied area while the resolution is high, capacitance type D/A converters have been developed.

A first prior art D/A converter is constructed by capacitors having binary weighted capacitance that are connected to an output terminal. Also, analog switches are provided that are controlled by input digital data connected to the capacitors. Each of the analog switches applies a low reference voltage or a high reference voltage to the corresponding capacitor in accordance with the corresponding input digital data. Thus, the first prior art D/A converter can generate an analog voltage in accordance with the input digital data (see JP-A-63-67920). This will be explained later in detail.

In the above-mentioned first prior art D/A converter, however, since the total capacitance of the capacitors is still large. Thus, the occupied area is still large.

In second and third prior art D/A converters, in order to more decrease the total capacitance, coupling capacitors are added to the first prior art D/A converters (see JP-A-57-124933 & JP-A-4-72819). This also will be explained later in detail.

In the above-mentioned second and third prior art D/A converters, however, the total capacitance is still large, which would increase the occupied area.

It is object of the present invention to provide a capacitance type D/A converter capable of further decreasing the total capacitance.

According to the present invention, in a D/A converter for converting 2n-bit input digital data into an analog output voltage where n is 2, 3, . . . , 2n capacitors, (n−1) coupling capacitors and 2n analog switches are provided. If k is 1, 2, . . . , n, a (2k−1)-th capacitor has a unit capacitance, and a 2k-th capacitor has a capacitance twice the unit capacitance. A first terminal of the (2k−1)-th capacitor is connected to a first terminal of the 2k-th capacitor. Also, if m is 1, 2, . . . , n−1, an m-th coupling capacitor is connected between the first terminal of the 2m-th capacitor and the first terminal of the (2m+1)-th capacitor, while an (n−1)-th coupling capacitor is connected to the output terminal. If m′ is 2, 3, . . . , n−1, the first coupling capacitor has the unit capacitance, and an m′-th one of coupling capacitors has a capacitance of the unit capacitance plus a quarter of the capacitance of an (m′−1)-th coupling capacitor. Each of the analog switches is responsive to one of the 2n input digital data and is connected between a second terminal of one of the capacitors and two power supply sources.

Note that, if the 2n-th capacitor and the 2n-th analog switch are omitted, the D/A converter serves as a (2n−1)-bit D/A converter.

The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram illustrating a first prior art 6-bit D/A converter;

FIG. 2 is a circuit diagram illustrating a second prior art 6-bit D/A converter;

FIG. 3 is a circuit diagram illustrating a third prior art 6-bit D/A converter;

FIG. 4 is a circuit diagram illustrating an embodiment of the D/A converter according to the present invention;

FIG. 5 is a diagram showing the relationship between the input digital data and the output voltage of FIG. 4;

FIG. 6 is a circuit diagram illustrating a modification of the D/A converter of FIG. 4;

FIG. 7 is a diagram showing the relationship between the input digital data and the output voltage of FIG. 6;

FIG. 8 is a circuit diagram illustrating a generalized D/A converter from the D/A converter of FIG. 4;

FIGS. 9 and 10 are circuit diagrams for explaining the operation of the D/A converter of FIG. 8; and

FIG. 11 is a circuit diagram illustrating a generalized D/A converter from the D/A converter of FIG. 6 .

Before the description of the preferred embodiment, prior art D/A converters will be explained with reference to FIGS. 1, 2 and 3 .

In FIG. 1, which illustrates a first prior art 6-bit D/A converter (see JP-A-63-67920), capacitors C 0 , C 1 , . . . , C 5 having binary weighted capacitance such as 1pF, 2pF, . . . , 32pF, respectively, are connected to an output terminal OUT where voltage is V OUT . Also, analog switches SW 0 , SW 2 , . . . , SW 5 controlled by 6-bit input digital data D 0 , D 1 , . . . , D 5 are connected to the capacitors C 0 , C 1 , . . . , C 5 , respectively. Each of the analog switches SW 0 , SW 1 , . . . , SW 5 applies a reference voltage V L or V H to the corresponding capacitor in accordance with the corresponding input digital data.

For example, if (D 0 , D 1 , D 2 , D 3 , D 4 , D 5 )=( 0 , 0 , 0 , 0 , 0 , 0 ), the analog switches SW 0 , SW 1 , . . . , SW 5 apply the reference voltage V L to the capacitors C 0 , C 1 , . . . , C 5 , respectively, so that the output voltage V OUT is

V OUT =0/(1+2+. . . +32)·( V H −V L )+ V L =V L

Also, if (D 0 , D 1 , D 2 , D 3 , D 4 , D 5 )=( 1 , 0 , 0 , 0 , 0 , 0 ), the analog switch SW 0 applies the reference voltage V L to the capacitor C 0 while the analog switches SW 1 , SW 2 , . . . , SW 5 apply the reference voltage V H to the capacitors C 1 , C 2 , . . . , C 5 , so that the output voltage V OUT is

V OUT =1/(1+2+. . . +32)·( V H −V L )+ V L =1/63·( V H −V L )+V L

Further, if (D 0 , D 1 , D 2 , D 3 , D 4 , D 5 )=( 1 , 1 , 1 , 1 , 1 , 1 ), the analog switches SW 0 , SW 1 , . . . , SW 5 apply the reference voltage V H to the capacitors C 0 , C 1 , . . . , C 5 , so that the output voltage V OUT is

V OUT =(1+2+. . . +32)/(1+2+. . . +32)·( V H −V L )+ V L

Thus, the D/A converter of FIG. 1 can generate an analog voltage V OUT in accordance with the 6-bit input digital data (D 0 , D 1 , . . . , D 5 ).

In the D/A converter of FIG. 1, since use is made of binary weighted capacitors, the occupied area can be decreased and the resolution can be higher as compared with conventional resistor string type D/A converters.

In the D/A converter of FIG. 1, however, the total capacitance C TOTAL of the capacitors C 0 , C 1 , . . . , C 5 is 63pF and is still large. Note that if the number of the capacitors is n, the total capacitance C TOTAL thereof is represented by

C TOTAL =2 n −1(pF)

where the capacitance of the capacitor C 0 is 1pF. Thus, the occupied area is still large.

In FIG. 2, which illustrates a second prior art 6-bit D/A converter (see JP-A-57-124933), a coupling capacitor CC having a capacitance of 1pF is added to the elements of FIG. 1, and the capacitances of the capacitors C 3 , C 4 and C 5 are 1pF, 2pF and 4pF, respectively. The operation of the D/A converter of FIG. 2 is the same as that of the D/A converter of FIG. 1 .

In the D/A converter of FIG. 2, the total capacitance C TOTAL of the capacitors C 0 , C 1 , . . . , C 5 as well as the coupling capacitor CC is 15pF and is smaller than that of the D/A converter of FIG. 1 .

In FIG. 3, which illustrates a third prior art 6-bit D/A converter (see JP-A-4-72819), coupling capacitors CC 1 , CC 2 , . . . , CC 5 having a capacitance of 1pF are added to the elements of FIG. 1, and the capacitances of the capacitors C 0 , C 1 , C 2 , C 3 , C 4 and C 5 are 1pF. The operation of the D/A converter of FIG. 3 is the same as that of the D/A converter FIG. 1 .

In the D/A converter of FIG. 3, the total capacitance C TOTAL of the capacitors C 0 , C 1 , . . . , C 5 as well as the coupling capacitors CC 1 , CC 2 , CC 3 , CC 4 and CC 5 is 16pF and is smaller than that of the D/A converter of FIG. 1 .

In the D/A converters of FIGS. 2 and 3, however, the total capacitance C TOTAL is still large, which would increase the occupied area.

In FIG. 4, which illustrates an embodiment of the D/A converter according to the present invention, coupling capacitors CC 1 and CC 2 having capacitances of 1pF and 1.25pF, respectively, are added to the elements of FIG. 1, and the capacitance's of the capacitors C 0 , C 1 , C 2 , C 3 , C 4 and C 5 are 1pF, 2pF, 1pF, 2pF, 1pF and 2pF, respectively. The operation of the D/A converter of FIG. 4 is the same as that of the D/A converter of FIG. 5 which shows a relationship between the input digital data (D 5 , D 4 , D 3 , D 2 , D 1 , D 0 ) and the output voltage V OUT where V L is 1V and V H is 1V.

In the D/A converter of FIG. 4, the total capacitance C TOTAL of the capacitors C 0 , C 1 , . . . , C 5 as well as the coupling capacitors CC 1 and CC 2 is 11.25pF and is smaller than those of the D/A converter of FIGS. 1, 2 and 3 , which would decrease the occupied area.

In FIG. 6, which illustrates a modification of the D/A converter of FIG. 4, the D/A converter of FIG. 4 is applied to a 5-bit D/A converter where the capacitor C 5 and the analog switch SW 5 of FIG. 4 are omitted. Note that the total capacitance C TOTAL of the D/A converter of FIG. 6 is smaller than that of the corresponding prior art D/A converter. In this case, FIG. 7 shows a relationship between the input digital data (D 4 , D 3 , D 2 , D 1 , D 0 ) and the output voltage V OUT where V L is 1V and V H is 1V.

In FIG. 8, which illustrates a generalized (2n+2)-bit D/A converter from the D/A converter of FIG. 4, capacitors C 0 , C 1 , C 3 , C 4 , . . . , C 2 n, C(2n+1) are provided where n is 1, 2, . . . In this case, the capacitance each of the capacitors C 0 , C 2 , . . . , C 2 n is 1pF which is a unit value or a minimum value, and the capacitance of each of the capacitors C 1 , C 3 , . . . , C(2n+1) is 2pF.

A first terminal of the capacitor C 2 k is connected to a first terminal of the capacitor C(2k+1) where k is 0, 1, . . . , n.

Also, one coupling capacitor CCk is connected between the first terminals of the capacitors C(2k−2) and C(2k−1) where k is 0, 1, . . . , n. In this case, the capacitance of the coupling capacitor CCk is represented by

CCk=C+CC ( k− 1)/4

where C is 1pF (unit value).

Further, the coupling capacitor CCn is connected to an output terminal OUT whose voltage is V OUT .

On the other hand, one analog switch SW(2k+1) is connected to a second terminal of the capacitor C(2k+1) where k is 0, 1, . . . , n. The analog switch SW(2k+1) is controlled by input digital data D(2k+1) to connect the second terminal of the capacitor C(2k+1) to either a power supply source PL or a power supply source PH. Note that the power supply sources PL and PH generate voltages V L and V H , respectively.

If the D/A converter of FIG. 8 operates a D/A converter where V L is 0V and V H is 1V, a voltage E(n+1) equal to the output voltage V OUT has to satisfy the following equation:

E ( n+ 1)=( D 0 + 2 ·D 1 +. . . 2 2n+1 ·D (2 n+ 1))/(2 2n+2 −1) ( V )   (1)

This equation (1) will be proved by using the following induction method.

First, assume that n is 0. In this case, an equivalent circuit diagram of the D/A converter of FIG. 8 is illustrated in FIG. 9 . That is, a voltage E 1 (D 0 ) derived by the digital data D 0 is

E 1 ( D 0 )=1 pF /(1 pF+ 2 pF )=⅓

Also, a voltage E 1 (D 1 ) derived by the digital data D 1 is

E 1 ( D 1 )=2 pF/( 1 pF+ 2 pF )

Therefore, from Thevenin's therem,

E 1 = E 1 ( D 0 )· D 0 + E 1 ( D 1 )· D 1 =( D 0 + 2 ·D 1 )/3

Thus, the equation (1) where n=1 is proved.

Next, assume that the equation (1) where n=k−1 is established, i.e.,

Ek =( D 0 + 2 · D 1 +. . . + 2 2k−1 ·D (2 k− 1))/(2 2k−2 −1)   (2)

Next, consider that n is k+1 as illustrated in FIG. 10 . In this case, a conductance C ok from a point whose voltage E(k+1) is given by

C ok =(1 −e −2k )· C=( 1 −e −2k ) ( pF )   (3)

Therefore, the voltage E(k+1) of FIG. 10 is calculated by

E ( k+ 1)=( C ok ·Ek+ 1 pF·D 2 k+ 2 pF·D (2 k+ 1))/( C ok +1 pF+ 2 pF )   (4)

Thus, from the equations (2), (3) and (4),

E ( k+ 1)=((1−2 −2k )·( D 0 + 2 · D 1 +. . . + 2 2k−1 ·D (2 k− 1)/(2 2k−2 −1)+( (D 2 k+D (2 k+ 1))/(4−2 −2k )

=( D 0 + 2 ·D 1 +. . . + 2 2k−1 ·D (2 k− 1)+2 2k ·D 2 k+D 2k+1 ·D (2 k+ 1))/(2 2k+2 −1)

Thus, the equation (1) has been proved.

In FIG. 11, which illustrates a generalized (2n+1)-bit D/A converter from the D/A converter of FIG. 6, capacitors C 0 , C 1 , C 3 , C 4 , . . . , C(2n−1), C 2 n are provided where n is 1, 2, . . . That is, the capacitor C(2n+1) and the analog switch SW(2n+1) of FIG. 8 are omitted. In this case, the equation (1) is replaced by

E ( n+ 1)=( D 0 + 2 ·D 1 +. . . + 2 2n+1 ·D 2 n )/(2 2n+2 −1)   (5)

As explained hereinabove, according to the present invention, since the total capacitance is small, the occupied area can be decreased.