Phase detector with minimized phase detection error

This is a continuation of application Ser. No. 08/582,045, filed on Jan. 2, 1996, which is a continuation of application Ser. No. 08/197,641, filed on Feb. 15, 1994 now abandoned.

The present invention pertains to the field of phase detection circuits. More particularly, this invention relates to a phase detector that relatively accurately detects the phase difference between two input signals having different voltage swing characteristics, wherein the phase detector substantially minimizes the phase detection error arising from parasitic capacitance.

Phase detection circuits are typically used in computer systems and other electronic systems for detecting the phase difference between two input signals. For example, in a phase locked loop (“PLL”) system, it is frequently desirable to generate a periodic signal waveform that is in a quadrature (i.e., 90 degree) phase relationship with a reference signal. This typically requires a phase detection circuit in the PLL system to detect any departure from the desired quadrature phase relationship between the two signals. The detected departure from the desired phase relationship between the two signals is typically referred to as quadrature phase error.

When the phase detection circuit detects the quadrature phase error, the amount of the quadrature phase error is then supplied to other circuits of the PLL system. These other circuits of the PLL system then compensate for the quadrature phase error of the two signals such that the desired quadrature phase relationship between the two signals is maintained. As is known, a PLL system is typically used to maintain stable frequency and phase characteristics of an input signal.

One type of prior art phase detection circuit for detecting the quadrature phase error of two signals is an exclusive-OR gate logic circuit. The exclusive-OR gate logic circuit detects the quadrature phase error by causing its average output voltage to be proportional to the quadrature phase error.

Disadvantages are, however, associated with the prior art exclusive-OR gate type quadrature phase detector. One disadvantage is that the prior art exclusive-OR gate type quadrature phase detector typically requires that its input signals have substantially similar voltage swing characteristics. If the input signals have different voltage swings, the average output voltage of the exclusive-OR gate typically cannot properly reflect the quadrature phase error detected.

Another disadvantage associated with such a prior art detector is that the prior art detector typically cannot accurately detect the quadrature phase error. This is often due to the fact that phase detection errors typically occur in the circuit during phase detection. One contributor to the phase detection errors is the parasitic capacitance in the circuit. Because of the unpredictable nature of the parasitic capacitance, it is often relatively difficult to compensate for the phase detection errors that arise from the parasitic capacitance.

One of the objects of the present invention is to provide a phase detector that accurately detects the phase difference between two input signals having different voltage swing characteristics.

Another object of the present invention is to provide a phase detector that substantially minimizes the phase detection error induced by the parasitic capacitance.

Another object of the present invention is to provide a phase detector that minimizes the phase detection error of the circuit by compensating for the parasitic capacitance that causes the phase detection error.

A further object of the present invention is to provide a phase detector for detecting the phase difference between a full voltage swing periodic signal and a low voltage swing quasi-differential or fully differential periodic signal, and for providing compensation for phase detection errors arising from parasitic capacitance such that substantially accurate measurement of the phase difference of the two signals can be obtained.

A phase detector is described that includes a load circuit that presents a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to (1) the first and second nodes and (2) ground for detecting a phase difference between a first input signal and a second input signal. A second circuit is coupled to (1) the first and second nodes and (2) ground for detecting the phase difference between the first and second input signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second input signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second input signals and a reference signal. The first and second circuits are cross-coupled such that an error current generated by the second circuit cancels that generated by the first circuit so that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.

A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit includes (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to (1) the first and second nodes and (2) ground for detecting a phase difference between a first input signal and a second input signal. The first circuit has a first transistor coupled to the first node and a third node, a second transistor coupled to the second and third nodes, and a third transistor coupled to the third node and ground via a first current source. The first transistor receives the first input signal. The second transistor receives a reference signal. The third transistor receives the second input signal. The first and second signals have different voltage swing characteristics.

Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.

The present invention is illustrated by way of example and not limited to the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIG. 1 illustrates a phase detector in accordance with one embodiment of the present invention;

FIG. 2 illustrates the waveform of the output signal of the phase detector of FIG. 1 in view of various input signals;

FIG. 3 is-a circuit diagram of a phase detector in accordance with another embodiment of the present invention;

FIG. 4 illustrates the waveform of the output signal of the phase detector of FIG. 3 in view of various input signals.

FIG. 5 shows a comparator that can be used in conjunction with the output signal produced by the circuits of FIGS. 1 and 3.

FIG. 1 illustrates the circuit of a quadrature phase detector 10 that implements one embodiment of the present invention. Phase detector 10 of FIG. 1 detects the quadrature phase error between first and second input signals that are in quadrature phase relationship and that have different voltage swing characteristics. FIG. 3 illustrates the circuit of another quadrature phase detector 40 that implements another embodiment of the present invention. Phase detector 40 minimizes the phase detection error induced by the parasitic capacitance. Phase detectors 10 and 40 will be described in more detail below.

Phase detector 10 shown in FIG. 1 includes transistors 11 through 14 and 19 through 21 . For one embodiment, transistors 11 - 14 and 19 - 21 are metal oxide semiconductor field effect transistors (“MOSFETs”) and are in a complementary metal oxide semiconductor (“CMOS”) configuration. For other embodiments, transistors 11 - 14 and 19 - 21 can be N-channel MOSFET transistors or P-channel MOSFET transistors. For alternative embodiments, other devices, such as bipolar transistors, may be used.

For one embodiment shown in FIG. 1, transistors 11 - 14 are P-channel transistors that are connected as current sourcing transistors between a power supply voltage V DD and nodes 15 and 16 . Alternatively, transistors 11 - 14 can be N-channel transistors or bipolar transistors.

Transistors 11 - 14 together constitute the load of phase detector 10 . Transistors 11 - 14 present a high differential impedance between nodes 15 - 16 and a low common mode resistance from the power supply V DD to nodes 15 - 16 . Diode connected transistors 11 - 12 serve as a low common mode resistance between the power supply V DD and nodes 15 - 16 . Transistors 11 - 12 also constitute a positive differential load resistance between nodes i 5 and 16 . Transistors 13 - 14 constitute a negative differential load resistance between nodes 15 and 16 . The negative differential load resistance cancels the positive differential load resistance. As a result, transistors 11 - 14 together present the high differential load resistance between nodes 15 and 16 . The connection of transistors 11 - 14 is described below.

Alternatively, other types of load circuits can be used in phase detector 10 between the power supply V DD and nodes 15 - 16 . In addition, the load formed by transistors 11 - 14 can be any other kind of high differential impedance load circuit.

The drain of transistors 1 1 - 14 are connected to node 15 and the drain of transistors 12 and 13 are connected to node 16 . Each of transistors 11 - 12 has its gate coupled to its drain. In addition, the gate of transistor 13 is connected to the gate of transistor 11 , and the gate of transistor 14 is connected to the gate of transistor 12 . Because the gates of transistors 11 and 13 are connected together and the gates of transistors 12 and 14 are connected together, transistor 13 mirrors the current through transistor 11 and transistor 14 mirrors the current through transistor 12 . In other words, transistors 11 and 13 constitute a current mirror and transistors 12 and 14 constitute another current mirror. By mirroring the current flowing through transistor 11 to node 16 and by mirroring the current flowing through transistor 12 to node 15 , each of nodes 15 - 16 receives substantially the same amount of current and no differential current is generated. This therefore causes transistors 11 - 14 to present a high differential load resistance because the negative differential load resistance generated by transistors 13 - 14 cancels the positive differential load resistance generated by transistors 11 - 12 .

For one embodiment, transistors 11 - 14 are substantially identical in size such that the negative differential load resistance generated by transistors 13 - 14 cancels the positive differential load resistance generated by transistors 11 - 12 .

Nodes 15 - 16 form the output of phase detector 10 . A first capacitor or capacitance 17 is connected between ground and node 15 and a second capacitor or capacitance 18 is connected to node 16 and ground. For one embodiment, capacitors 17 and 18 have substantially equivalent capacitance. For one embodiment, capacitors 17 and 18 include parasitic capacitances of transistors 11 - 14 at nodes 15 - 16 , respectively. Alternatively, capacitors 17 and 18 may or may not comprise parasitic capacitances, such as those of transistors 11 - 14 at nodes 15 - 16 , respectively.

The circuit of FIG. 1 has a pair of transistors 19 and 20 that receive a quasi-differential input signal comprising signals V IN2 and V REF , and that produce output signal V OUT at output nodes 15 and 16 . In addition, the circuit has a transistor 21 that receives an input signal V IN1 . More specifically, node 15 is connected to the drain of transistor 19 and node 16 is connected to the drain of transistor 20 . The sources of transistors 19 - 20 are connected to a node 23 . Node 23 is then connected to the drain of transistor 21 . Transistor 21 has its source connected to ground via a current source 24 . The gate of transistor 19 receives an input signal V IN2 . The gate of transistor 20 receives an input signal V REF . The gate of transistor 21 receives an input signal V IN1 . Transistors 19 - 21 are N-channel transistors. Alternatively, transistors 19 - 21 can be P-channel transistors or bipolar transistors. For one embodiment, transistor 19 has a size that is substantially equal to that of transistor 20 .

As seen from FIG. 2, the V IN1 signal exhibits a full CMOS voltage swing. The V IN2 signal, however, is a small voltage swing signal that oscillates substantially symmetrically around the V REF reference voltage. As can be seen from FIG. 2, the V REF signal is a constant DC reference voltage. The V IN2 signal is therefore referred to as quasi-differential signal. In other words, the V IN2 and V REF signals are not complementary to each other. The V IN1 and V IN2 signals are shown in the quadrature phase relationship in FIG. 2 .

Alternatively, the V IN2 signal is a small swing, fully differential signal that swings between a V high voltage and a V low voltage. In this case, the V REF signal is complementary to the V IN2 signal. In other words, when the gate of transistor 19 receives the V high voltage, the gate of transistor 20 receives the V low voltage.

Transistors 19 - 21 detect the quadrature phase error of the V IN1 and V IN2 input signals. It is desirable to have the V IN1 and V IN2 signals in a quadrature phase relationship. When quadrature phase error occurs (i.e., the desired quadrature phase relationship has not been achieved), phase detector 10 detects that condition by producing a net differential voltage across nodes 15 - 16 (i.e., the output V OUT ) at the end of each measurement cycle. The amplitude of the net differential voltage across nodes 15 - 16 is a function of the amount of quadrature phase error between the V IN1 and V IN2 input signals. If phase detector 10 does not detect any quadrature phase error, phase detector 10 does not produce any net differential voltage across nodes 15 - 16 at the end of the detection cycle.

Phase detector 10 also includes a transistor 22 coupled between nodes 15 - 16 . Transistor 22 is an N-channel MOSFET transistor. Alternatively, transistor 22 can be a P-channel MOSFET transistor or a bipolar transistor. Transistor 22 is used in phase detector 10 as an equalizing transistor. Transistor 22 causes the voltage difference across nodes 15 - 16 to be zero when transistor 22 conducts before a measurement cycle is initiated. As can be seen from FIG. 1, transistor 22 is switched on or off by the V EQ signal. When transistor 22 is turned on by the V EQ signal, nodes 15 and 16 are connected together via transistor 22 and the voltages at nodes 15 - 16 are equalized.

FIG. 2 also illustrates the signal waveform of the V EQ signal. As can be seen from FIG. 2, the V EQ signal can be a periodic pulse signal that occurs before every pulse of the V IN1 signal. The V EQ signal helps to equalize the voltages across nodes 15 - 16 for starting a detection cycle. Alternatively, the pulse cycle of the V EQ signal can occur before every Nth pulse of the V IN1 signal.

Referring to FIGS. 1-2, the operation of phase detector 10 is now described. As shown in FIG. 1, transistor 21 connects a current I from node 23 to current source 24 when the V IN1 signal is at the high V DD voltage, thereby enabling transistors 19 and 20 to charge or discharge capacitances 17 and 18 as 11 will be described in more detail below. Because transistor 21 is connected to current source 24 , transistor 21 , when conducting, only allows the amount of current I to flow through. The V IN1 signal controls the start of each detection cycle. Whenever the voltage level of the V IN1 signal rises to the V DD voltage, a detection cycle is initiated.

When the voltage level of the V IN2 signal is higher than that of the V REF voltage and when the V IN1 signal is at the V DD voltage (e.g., from time t 1 to time t 2 ), transistor 19 conducts more than transistor 20 does. Transistor 19 thus contributes substantially all the I current to node 23 . Because each of nodes 15 and 16 receives substantially the same amount of current from the load element formed by transistors 11 - 14 , capacitor 17 is charged differently than capacitor 18 if transistors 19 and 20 are not drawing the same amount of current to node 23 . In this case, capacitor 18 may be charging while capacitor 17 is discharging. This in turn generates a differential voltage across nodes 15 - 16 , and therefore at the output V OUT Of phase detector 10 . The differential voltage at the output V OUT ramps linearly upwards for the time that the voltage of the V IN2 signal is higher than the V REF reference voltage (e.g., from time t 1 to time t 2 in FIG. 2 ). The signal waveform of the V OUT signal is also shown in FIG. 2 .

When the voltage level of the V IN2 signal is lower than that of the V REF voltage and when the V IN1 signal is at the V DD voltage (e.g., from time t 2 to time t 3 ), transistor 20 then contributes substantially all the I current to node 23 . This in turn causes the charging of capacitors 17 - 18 to be uneven. In this case, capacitor 17 may be charging while capacitor 18 is discharging. This then results in the differential voltage at the output V OUT of phase detector 10 to drop linearly downwards (see the waveform of the V OUT signal in FIG. 2 ).

When the voltage level of the V IN1 signal goes to ground, at the conclusion of the detection cycle, transistor 21 disconnects current I from node 23 and transistors 19 and 20 are thereby effectively disabled from charging or discharging capacitances 17 and 18 . Because of this, the differential voltage at the output V OUT stops changing. If the V IN1 and V IN2 signals are in perfect quadrature, the differential voltage across nodes 15 - 16 ramps linearly towards zero and no net differential voltage will be developed at the V OUT output of phase detector 10 at the time when the V IN1 signal goes to ground (e.g., at time t 3 , after the detection cycle). If, however, a quadrature phase error exists between the V IN1 and V IN2 signals, a net differential voltage will be developed across nodes 15 - 16 at the end of the phase detection cycle (e.g., from time t 1 to time t 3 ). The net differential voltage across nodes 15 - 16 is substantially proportional to the amount of the quadrature phase error.

The output V OUT of phase detector 10 can be connected to a comparator to generate a binary quadrature phase error output. Other circuits may also be used to generate the binary quadrature phase error output. FIG. 5 shows an example of a comparator 100 connected to receive signals V+ OUT and V− OUT of FIG. 1, and to produce a binary quadrature phase error output 102 .

The above description of phase detector 10 in detecting the quadrature phase error assumes the desirable situation in which the influence of any parasitic capacitance of transistors 19 through 21 at node 23 is neglected. As can be seen from FIG. 1, phase detector 10 , however, includes a parasitic capacitor 25 coupled between node 23 and ground. Parasitic capacitor 25 includes the parasitic capacitance associated with one or more of transistors 19 - 21 at node 23 , as well as other parasitic capacitances. Because transistor 21 is used as a switch, parasitic capacitor 25 includes the parasitic capacitance between the source of transistor 21 and ground.

Due to the existence of parasitic capacitor 25 in the circuit of phase detector 10 , phase detector 10 generates a net differential voltage at the output V OUT of the circuit at the end of a detection cycle even when the V IN1 and V IN2 signals are in the perfect quadrature phase relationship, as can be seen from FIG. 2 (e.g., at time t 3 ). The generation of the net differential voltage at the V OUT output of phase detector 10 by parasitic capacitor 25 is described below.

As can be seen from FIG. 1, due to parasitic capacitor 25 , the voltage level at node 23 does not change immediately after transistor 21 is turned on by the V IN1 signal, causing the current flowing through transistor 21 to exceed the current I, which generates an additional error current. Because the voltage level of the V IN2 signal is higher than the V REF voltage, this additional error current flows through transistor 19 . This in turn causes capacitor 17 to be additionally discharged by the additional error current, which results in the differential voltage at the output V OUT to be ramped higher.

When, however, the voltage level of the V IN2 signal drops below the V REF voltage, transistor 19 is much less conducting than transistor 20 , and transistor 20 contributes substantially all the I current to node 23 . The voltage level at node 23 falls. This causes parasitic capacitor 25 to be discharged, reducing the current flowing through transistor 20 , which generates an additional error current flowing through transistor 20 to capacitor 18 . This additional error current causes capacitor 18 to be additionally charged.

In addition, due to parasitic capacitor 25 , the voltage level at node 23 does not change immediately after transistor 21 is turned off by the V IN1 signal, causing an additional error current to flow through transistor 20 to parasitic capacitor 25 . This additional error current causes capacitor 18 to be additionally discharged.

As a result, all the above-described error currents in charging capacitors 17 - 18 cause a net differential voltage at the output V OUT of phase detector 10 at the end of a detection cycle even when the V IN1 and V IN2 signals are in the perfect quadrature phase relationship, as can be seen from FIG. 2 . When this occurs, a phase detection error occurs. Because of the unpredictable nature of the parasitic capacitance, the voltage level of the net differential voltage due to the parasitic capacitance also cannot be predicted.

Phase detector 40 of FIG. 3 eliminates the net differential voltage occurring at the output of the circuit due to the parasitic capacitance. To accomplish this, the circuit of FIG. 3 includes error correction transistors 52 and 53 that are cross-coupled to the output nodes 45 and 46 to reduce any output signal error induced by parasitic capacitance 57 . The configuration and operation of these transistors will be explained in more detail below.

Node 45 is connected to capacitor 47 and capacitor 48 is connected to node 46 . The capacitance of capacitor 48 is substantially equal to that of capacitor 47 . Nodes 45 - 46 are then connected to a first circuit formed by transistors 49 through 51 and a second circuit formed by transistors 52 through 54 . Transistors 51 and 54 are then connected to a circuit 60 , which essentially includes a first current source for providing a first current I 1 through transistors 51 and a second current source for providing a second current I 2 through transistor 54 , as can be seen from FIG. 3 . Both the I 1 and I 2 currents are generated and controlled by a I BIAS current.

Circuit 60 generates the I 1 and I 2 currents. The value of the I 2 current is smaller than that of the I 1 current. For one embodiment, the value of the I 2 current is in a range of 20% to 30% of the I 1 current. For alternative embodiments, the value of the I 2 current can be larger or smaller than 20% to 30% of the I 1 current.

For one embodiment, transistors 49 - 51 and 52 - 54 are N-channel MOSFET transistors. For alternative embodiments, transistors 49 - 51 and 52 - 54 can be P-channel MOSFET transistors or bipolar transistors. For one embodiment, the size of each of transistors 52 - 53 is substantially equal to that of each of transistors 49 - 50 and the size of transistor 54 is substantially equal to that of transistor 51 .

Transistor 49 is connected to node 45 and node 55 . Transistor 50 is connected to nodes 46 and 55 . Transistor 51 connects node 55 to ground via the current source I 1 formed by circuit 60 . Similarly, transistor 52 is connected to node 46 and a node 56 . Transistor 53 is connected to nodes 45 and 56 . Transistor 54 connects node 56 to ground via the current source I 2 formed by circuit 60 . The gate of each of transistors 51 and 54 receives the V IN1 signal. The gate of each of transistors 49 and 52 receives the V IN2 signal and the gate of each of transistors 50 and 53 receives the V REF voltage. The V IN1 and V IN2 signals and the V REF voltage are identical to those described above and shown in FIGS. 1-2. FIG. 4 also illustrates the signal waveforms of these signals.

FIG. 3 also illustrates a parasitic capacitor 57 connected to node 55 and ground and a parasitic capacitor 58 connected to node 56 and ground. Parasitic capacitor 57 includes the parasitic capacitance of transistors 49 - 51 at node 55 and parasitic capacitor 58 includes the parasitic capacitance of transistors 52 - 54 at node 56 . Parasitic capacitor 57 also includes other parasitic capacitances. Because transistor 51 is used as a switch, parasitic capacitor 57 includes the parasitic capacitance between the source of transistor 51 and ground. Likewise, parasitic capacitor 58 also includes other parasitic capacitances. Because transistor 54 is used as a switch, parasitic capacitor 58 includes the parasitic capacitance between the source of transistor 54 and ground.

Transistors 49 - 51 detect the phase error of the V IN1 and V IN2 signals. Transistors 52 - 54 cancel the net differential voltage at the output V OUT Of phase detector 40 due to parasitic capacitor 57 in the circuit. As described above, each of transistors 52 - 53 has a size that is substantially equal to that of each of transistors 49 - 50 . Therefore, the capacitance of parasitic capacitor 58 is substantially equal to that of parasitic capacitor 57 . Due to the negative cancellation effect of transistors 52 - 54 , the additional error currents generated in the circuit due to parasitic capacitors 57 - 58 cancel each other and phase detector 40 of FIG. 3 does not experience any net differential voltage generated at the output V OUT of the circuit due to the parasitic capacitance. Because the capacitance of parasitic capacitors 57 - 58 is substantially equal, the additional error currents associated with parasitic capacitors 57 - 58 are also substantially equal. Transistors 49 - 50 and 52 - 53 are, however, cross-connected such that their respective contributions subtract from each other. This causes the additional error currents to cancel each other. This thus allows phase detector 40 to detect the quadrature phase error of the V IN1 and V IN2 signals with minimized phase detection error.

The operation of transistors 52 - 54 is described below, in conjunction with FIGS. 3 and 4. As can be seen from FIG. 3, when transistor 51 is turned on by the logical high V IN1 signal, the voltage level at node 55 does not change immediately, causing the current flowing through transistor 51 to exceed the current 11 , which generates an additional error current. Because the voltage level of the V IN2 signal is higher than the V REF voltage at this time, this additional error current flows through transistor 49 , causing capacitor 47 to be additionally discharged. Meanwhile, because transistor 54 is also turned on by the logical high V IN1 signal, the voltage level at node 56 does not change immediately, which also generates an additional error current flowing through transistor 54 . As the voltage level of the V IN2 signal is higher than the V REF voltage at this time, an additional error current flows through transistor 52 , causing capacitor 48 to be additionally discharged. Because the capacitance of parasitic capacitor 57 is equal to that of parasitic capacitor 58 , the additional error current that flows through transistor 52 is substantially equal to the additional error current through transistor 49 . Given that transistor 52 is connected to node 46 while transistor 49 is connected to node 45 , the additional error current generated by transistor 52 cancels that generated by transistor 49 .

When the voltage level of the V IN2 signal is lower than that of the V REF voltage, transistor 49 is much less conducting than transistor 50 and transistor 52 is much less conducting than transistor 53 . The voltage level at each of nodes 55 and 56 falls. This causes parasitic capacitors 57 and 58 to be discharged, reducing the current flowing through transistors 50 and 53 , respectively. This then causes an additional error current to flow through transistor 50 to capacitor 48 and an additional current to flow through transistor 53 to capacitor 47 , additionally charging capacitors 47 and 48 , respectively. Given that transistor 50 is connected to node 46 and transistor 53 is connected to node 45 and given that the additional error currents through transistors 50 and 53 are substantially equal to each other, the additional charging to each of capacitors 47 and 48 cancels each other.

In addition, due to parasitic capacitors 57 and 58 , the voltage level at each of nodes 55 and 56 does not change immediately after transistors 51 and 54 are turned off by the V IN1 signal, causing an additional error current to flow through transistor 50 to parasitic capacitor 57 and an additional error current to flow through transistor 53 to parasitic capacitor 58 . The additional error currents cause capacitors 47 and 48 to be additional discharged, respectively. Because the capacitance of parasitic capacitor 57 is substantially equal to that of parasitic capacitor 58 , the additional error current flowing through transistor 50 is substantially equal to the additional error current flowing through transistor 53 . Given that transistor 50 is connected to node 46 and transistor 53 is connected to node 45 , the additional error currents cancel each other. By doing so, no net differential voltage due to parasitic capacitor 58 will be developed at the output V OUT and phase detector 40 detects the quadrature phase error of the V IN1 and V IN2 signals with minimized detection error. The signal waveform of the V OUT signal of phase detector 40 is shown in FIG. 4 .

The V OUT output of phase detector 40 can also be connected to a comparator to generate a binary quadrature phase error output. Alternatively, other circuits can be used to generate the binary quadrature phase error output. FIG. 5 shows an example of a comparator 100 connected to receive signals V+ OUT and V− OUT of FIG. 3, and to produce a binary quadrature phase error output 102 .

Phase detector 40 also includes an equalizing transistor 59 connected between nodes 45 - 46 . Transistor 59 ensures that phase detector 40 initiates a phase detection cycle with a zero differential voltage at the output V OUT , and is controlled by the V EQ signal.

The generation of the V EQ signal can be controlled by a clock signal. Therefore, various clocking protocols can be used to generate the V EQ signal pulses. For example, to increase sensitivity in some applications, the measurement can take place over a number of clock cycles. In those cases, the V EQ pulse is generated such that transistor 59 is activated only once every N clock cycles, wherein N is the number of clock cycles during which the phase error measurement is allowed to integrate.

For one embodiment, N is equal to two, as shown in FIG. 4 . For alternative embodiments, N can be larger than two.

Thus, the phase detector described above includes first and second circuits that are constructed in substantially the same way and receive the same input signals. The first and second circuits are, however, cross-coupled together such that the error current generated by the second circuit cancels that generated by the first circuit in order to allow the circuit to perform the designated function with minimized error.

In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.