Circuit for compensating for the difference between the Vgs voltages of two MOS transistors

The present invention relates to the field of integrated circuits, and, more particularly, to a circuit that compensates for the difference between the gate-source voltages (Vgs) of two MOS transistors of an integrated circuit. The present invention also applies to field-effect transistors of different types.

MOS transistors are field-effect transistors produced by metal-oxide semiconductor (MOS) technology processes, and are commonly used as basic components for devices in analog and digital integrated circuits.

Characteristics of the components of integrated circuits vary relative to the design characteristics because of the variability of the production processes. MOS transistors of different types or dimensions formed in the same circuit may respond differently to process variations. In many applications, particularly in analog circuits, this different behavior of MOS transistors causes imbalances in the operation of the circuits, or undesired deviations from the operation provided for at the design stage.

An example of such an application is the input stage of an amplifier. As shown in FIG. 1, the input stage includes an n-channel transistor Mn and a p-channel transistor Mp having their source electrodes connected to the respective terminals of a voltage reference (ground and VDD), and their gate electrodes connected to respective biasing circuits. The biasing circuits include, in this example, two identical current generators Go respectively connected to an input node N of the input stage via a resistor Ro. The drain electrodes of the two transistors form two outputs of the input stage, and are connected to other components of the amplifier.

If the input stage is required to have a symmetrical response to an input signal applied to the input node N, the generators Go must generate identical currents, the resistors Ro must have the same resistance, and the voltages Vgsn and Vgsp between the gate electrodes and the source electrodes of the two transistors Mn and Mp must be identical. The first two conditions can be satisfied by sufficient precision, but the third cannot generally be satisfied because the two transistors are structurally different from one another. Therefore, they have different characteristic curves. Moreover, the two transistors respond differently to temperature variations during operation.

In this example, two complementary MOS transistors are considered, but similar problems also arise with the use of MOS transistor pairs that include both n-channel transistors or both p-channel transistors. These transistors have different dimensions or are biased such that different currents pass through them.

An object of the present invention is to provide a circuit which compensates for the difference between the gate-source voltages of two MOS transistors of different types due to variations in the production processes and/or to variations of other parameters, such as temperature.

This object is achieved using a compensation circuit for compensating a difference between gate-source voltages of first and second MOS transistors of an integrated circuit. The compensation circuit preferably comprises third and fourth MOS transistors in the integrated circuit and which are respectively a same type as the first and second MOS transistors. A bias circuit is preferably connected to the third and fourth MOS transistors for biasing thereof, and a measurement circuit measures a difference between gate-source voltages of the third and fourth transistors.

The compensation circuit preferably further includes a current compensation circuit connected to the measurement circuit for generating a compensation current based upon the measured difference between the gate-source voltages of the third and fourth transistors. A bias compensation circuit is preferably connected to the measurement circuit for modifying biasing of the first and second MOS transistors using the generated compensation current.

The integrated circuit also includes a voltage compensation circuit for generating a compensation voltage to add to or substrate from the gate-source voltages of the first and second MOS transistors so that respective drain currents are equal. The difference between gate-source voltages of the first and second MOS transistors are thus compensated to overcome variations in the production processes and/or to variations of other parameters, such as temperature. The first and third MOS transistors may be p-channel MOS transistors and the second and fourth MOS transistors may be n-channel MOS transistors.

The invention will be better understood from the following detailed description of an embodiment thereof which is given by way of a non-limiting example with reference to the appended drawings, in which:

FIG. 1 is a simplified circuit diagram of an input stage of an amplifier according to the prior art;

FIG. 2 is a diagram similar to that of FIG. 1 modified by the addition of a compensation circuit according to the present invention;

FIG. 3 is a diagram of a compensation circuit according to the present invention;

FIGS. 4 a and 4 b show two applications of the compensation circuit according to the present invention; and

FIG. 5 shows a variation of the compensation circuit illustrated in FIG. 3 .

FIG. 2 shows schematically the amplifier input stage of FIG. 1, and includes a circuit for compensating for the difference between the voltages Vgsn and Vgsp. The compensation circuit is represented by block 10 , and generates a compensation current Io which is injected into node N.

As can be seen in FIG. 3, the compensation circuit 10 comprises two MOS transistors, a p-channel transistor Mp 1 and an n-channel transistor Mn 1 which are of the same type as the transistors Mp and Mn of FIG. 2 . That is, the transistors are manufactured in the same device and by the same process stages. In this embodiment, the transistors Mp 1 and Mn 1 respectively have the same dimensions as the transistors Mp and Mn. However, they could have different dimensions.

Each of the two transistors Mp 1 and Mn 1 has its gate and drain electrodes connected to one another. The transistors Mp 1 and Mn 1 are each connected between the voltage reference or supply terminals by a constant current generator. In this embodiment, the constant current generators are formed by two p-channel transistors Mp 2 and Mp 3 which have their source electrodes connected together to the terminal VDD. The gate electrodes are connected together to a terminal VB 2 of a constant voltage supply. One of the transistors has its drain electrode connected to the source electrode of the transistor Mp 1 at node A 1 , and the other transistor has its drain electrode connected to the drain electrode of the transistor Mn 1 at node A 2 . The transistor Mp 1 has its body region connected to its source electrode.

Each of the nodes A 1 and A 2 is connected to the input of a decoupling stage. The outputs of the decoupling stage are connected to one another by resistor R 1 . In this embodiment, the decoupling stages are formed by two p-channel MOS transistors Mp 4 and Mp 5 having their gate electrodes connected to nodes A 1 and A 2 , respectively. Their source electrodes are connected to the terminal VDD via respective constant current generators, and their drain electrodes are connected to ground via the input branches of respective current mirrors Sp 1 and Sp 3 .

The constant-current generators are formed, respectively, by two p-channel transistors Mp 6 and Mp 7 having their source electrodes connected together to terminal VDD, their gate electrodes connected together to terminal VB 1 of a constant-voltage supply, and their drain electrodes connected to the source electrodes of the transistors Mp 4 and Mp 5 , respectively. The output branches of the current mirrors Sp 1 and Sp 3 are in series with the input and output branches, respectively, of a further current mirror Sp 2 , as shown in FIG. 3 .

The circuit combination comprising transistors Mp 2 and Mp 3 has the function of biasing the transistors Mp 1 and Mn 1 . The circuit combination comprising the decoupling stages Mp 4 and Mp 5 and the respective current generators Mp 6 and Mp 7 has the function of measuring the difference between the gatesource voltages Vgsp and Vgsn of the two transistors Mp 1 and Mn 1 .

The voltages of nodes A 1 and A 2 relative to ground, that is, voltages Vgsp and Vgsn, are reproduced substantially unchanged by the decoupling stages at the terminals of the resistor R 1 so that a current Id proportional to the difference between the voltages Vgsn and Vgsp flows through this resistor.

Upon the assumption that all of the mirrors have a gain equal to 1, a current Io=2Id is supplied to a load RL. The load RL is shown in FIG. 3 using a dashed line connected between the output branches of the mirrors Sp 2 , Sp 3 and ground. This can easily be confirmed based upon the following.

The current passing through the resistor R 1 is Id=(Vgsn-Vgsp)/R 1 , where R 1 is the resistance of the resistor R 1 . The currents Ip 4 and Ip 5 passing through the transistors Mp 4 and Mp 5 , respectively, differ from one another by 2Id. The currents in the input and output branches of the mirror Sp 2 are equal to Ip 4 . The current in the output branch of the mirror Sp 3 is equal to Ip 5 .

The injection of the current thus obtained into node N of the circuit of FIG. 2 with the use of two resistors Ro as compensation-voltage generators having the same resistance as the resistor R 1 adds to or subtracts from the voltages Vgs of the two transistors Mn and Mp a voltage rendering the drain currents of the two transistors equal to one another. In other words, this compensates for any differences between the Vgs voltages of the two transistors.

If the transistors Mp 1 and Mn 1 are not identical to the transistors Mp and Mn to be compensated but, for example, have different dimensions, it is necessary to select resistors Ro to achieve the desired compensation. The resistances Ro have resistances proportional to that of the resistor R 1 with a proportionality factor dependent on the ratios between the dimensions of the transistors to be compensated and those of the transistors Mn 1 and Mp 1 of the compensation circuit 10 . This also takes into account the currents and the current ratios of the current mirrors.

With the same circuit 10 or with a circuit similar thereto, it is also possible to compensate the gate-source voltages of n-channel and p-channel transistors in circuit configurations other than that shown in FIG. 2 . For example, as shown in FIGS. 4 a and 4 b , the transistors Mn′ and Mp′ may have their gate electrodes connected to their drain electrodes and may be biased by respective generators Gn and Gp connected between their drain electrodes and respective voltage references Vdd and ground.

The compensation current Io is injected into the drain electrode of the respective transistor Mn′, Mp′ via a resistor Ro′. If the transistors Mn′ and Mp′ are identical to the transistors Mn 1 and Mp 1 , respectively, compensation is achieved with the use of resistors Ro′ having the same resistance as the resistor R 1 . Otherwise, the resistance value is selected to be proportional to that of the resistor R 1 with a proportionality factor which depends on the ratio between the dimensions of the transistors Mn′ and Mp′ to be compensated and those of the transistors Mn 1 and Mp 1 of the circuit 10 . The compensated voltages Vn and Vp are given by the sum of the gate-source voltages Vgsn and Vgsp of the transistors Mn′ and Mp′, respectively, and by the voltage drop in the resistors Ro′.

If the transistors to be compensated belong to separate circuits, as shown in FIGS. 4 a and 4 b , the mirrors Sp 2 and Sp 3 should have two separate output branches, as shown in FIG. 5 . Moreover, if there are more than two transistors to be compensated it may be necessary to modify the current mirrors Sp 2 and Sp 3 such that they have as many output branches as there are transistors to be compensated independently of one another.

Although only one embodiment of the invention has been described and illustrated, clearly many variations are possible within the scope of the same inventive concept. For example, instead of a resistor, another component such as a MOS transistor biased to the linear zone may be used as the compensation current generator.