Memory modules and packages using different orientations and terminal assignments

1. Field of the Invention

The present invention relates to memory modules and packaging of integrated memory circuits.

2. Description of the Related Art

Fast computer systems have needed memory modules and dynamic random access memories (DRAMs) having high bandwidths and short access times. To meet these needs, synchronous DRAM (SDRAM), double data rate SDRAM, and Rambus DRAM (RDD) have been developed. When using RDDs in a main memory, each RDD is generally mounted on a Rambus inline memory module (RiMM).

FIG. 1 shows the configuration of a typical RDD memory system, which includes multiple RiMMs connected to a controller. Each RiMM includes a printed circuit board SUB, on or through which multiple RDDs serially connect to each other. RDDs of each RiMM operate according to signals synchronized with a clock signal. In particular, each RDD of the main memory operates according to a packet of signals, which are sequentially received during a specific period, and each RDD receives and outputs data independently of the other RDDs.

FIG. 2 illustrates a RiMM such as used in the memory system of FIG. 1 . The RiMM includes eight RDDs ID 0 to ID 7 , each of which has sixteen data input/output (I/O) pins (DQ pins) DQA 1 to DQA 8 and DQB 1 and DQB 8 . The bandwidth of the RiMM depends on the output speed and the number of DQ pins or terminals on each RDD. Each RDD ID 0 to ID 7 in FIG. 2 can be a 8M×16 RDD package. FIG. 3 is an expanded view of area (A) of FIG. 2 and illustrates how buses on the RiMM connect to the data and control pins of the separate RDD packages.

A pair of RDD packages, for example, RDD ID 0 and RDD ID 1 form a memory having a 16M×16 organization. However, a specific memory organization such as 16M×16 can be achieved in different manners, for example, using two (8M×16) RDD packages or two (16M×8) RDD packages. However, packages for memory chips having different data widths often have different sizes. For example, a packaged for ×8 RDD is typically smaller than a package for a ×16 RDD because the ×8 package has fewer data pins. Accordingly, methods, modules, and packages that use memory chips having narrower data widths to achieve a high data bandwidth facilitate reducing the size of memory components.

The present invention provides memory modules and methods of packaging memory devices. In accordance with an embodiment of the invention, a method includes: preparing semiconductor packages of the memory devices, each of which has external pins that include external data I/O pins and command signal pins; mounting the packages on a printed circuit board, on which a first bus, a second bus, and a third bus are formed; connecting the data I/O pins of odd-numbered packages to the first bus; connecting the data I/O pins of even-numbered packages to the second bus; and connecting the command signal pins of the packages to the third bus. The semiconductor packages can have orientations that alternate so that even-numbered packages have one orientation and odd-numbered packages have another orientation.

In accordance with another embodiment of the invention, a memory module includes: a printed circuit board on which a first bus, a second bus, and a third bus are formed; and semiconductor packages, each of which includes a memory device, data pins, and command signal pins. In odd-numbered packages, the data pins connect to the first bus, and in even-numbered packages, the data pins connect to the second bus. The command signal pins of the packages connect to the third bus. The even-numbered packages can have orientations or assignment of pins that differ from those of the odd-numbered packages.

The features and advantages of the present invention will become more apparent by describing in detail specific embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a schematic diagram of a conventional Rambus memory system;

FIG. 2 illustrates a conventional Rambus inline memory module (RiMM);

FIG. 3 is a magnified view of the portion (A) of FIG. 2;

FIG. 4 is a partial view of a RiMM according to an embodiment of the present invention;

FIG. 5 is a partial view of a RiMM according to another embodiment of the present invention;

FIG. 6 is a partial view of a RiMM according to still another embodiment of the present invention;

FIG. 7 shows pin configurations of RDDs used in the RiMM of FIG. 6;

FIG. 8 is a partial view of a RiMM according to still another embodiment of the present invention; and

FIG. 9 shows pin configurations of RDDs in the RiMM of FIG. 8 .

Use of the same reference symbols indicates identical or similar items.

Memory systems using Rambus DRAMs (RDDS) require a channel with an impedance that is lower than the impedance of channels for some other DRAMs and SDRAMs. For example, the channel impedance of an SDRAM memory system is typically between 50Ω and 80Ω, while the channel impedance of an RDD memory system must be approximately 28Ω. In addition, the channel impedance deviation of different channels on a RiMM must be within +/− 10% of 28Ω for accurate transmission of data. In the design of a typical RiMM, portions of the printed circuit board away from the RDDS, such as the tab (connecting area to external system) portion, are designed to have channel impedance of 28Ω +/− 10%. The portion of RiMM printed circuit board, on which RDDs will be mounted, is designed to have an impedance such that a combination with the impedance of the RDDs results in the impedance of 28Ω +/− 10%. Generally, the line impedance of a line (on the RiMM printed circuit board) on which no RDDs are mounted is (L L /C L ) ½ , and the line impedance of a line on which RDDs are mounted is approximately (L L /(C L +C i )) ½ . Here, L L is the self inductance of the line, C L is the self capacitance of the line, and C i is the input capacitance of an RDD connected to the line. Accordingly, the impedance of a line on which RDDs are mounted depends on the input capacitance of the RDDs.

FIG. 4 illustrates a RiMM according to an embodiment of the present invention, in which pairs of (16M×8) RDDs are combined to function as (16M×16) RDDs. In FIGS. 4 to 9 , RDDs are packaged in an area array package form, such as μ-BGA (Ball Grid Array), and white and dark circles are external pins of the RDD packages. Dark circles denote data pins for receiving and outputting a first or second group of data DQA or DQB, and white circles denote command pins for receiving commands and power pins for receiving a power supply voltage VDD or a ground voltage VSS. FIGS. 4 to 9 shows only one data pin or one command pin of each RDD as being connected to each bus. In an actual RiMM, each data pin and each required control pin of each RDD package connects to the appropriate data or command line of the RiMM.

Referring to FIG. 4, multiple RDD packages are arranged along the direction of buses BUS 1 , BUS 2 , and BUS 3 on one side of a RiMM printed circuit board SUB. Odd-numbered RDD packages, such as RDD 1 and RDD 3 , are mounted on printed circuit board SUB with one orientation, and even-numbered RDD packages, such as RDD 2 and RDD 4 , are mounted on printed circuit board SUB with an orientation rotated by 180° with respect to the odd-numbered RDD packages. With these orientations, data pins of the odd-numbered RDDs are nearer the top of the RiMM, and data pins of the even-numbered RDDs are nearer the bottom of the RiMM. Two adjacent RDD packages, e.g., RDD 1 and RDD 2 , are a memory pair, which forms a 16M×16 memory section.

Bus BUS 1 transmits a first group of data signals DQAi (i is an integer, e.g., between 1 and 8) and connects to data pins of the odd-numbered RDD packages, such as RDD 1 and RDD 3 . Bus BUS 2 transmits a second group of data signals DQBi (i is an integer, e.g., between 1 and 8) and connects to the data pins of the even-numbered RDD packages, such as RDD 2 and RDD 4 . The difference in orientations of RDDs allows buses BUS 1 and BUS 2 to connect to the RDDs without interfering with each other.

Bus BUS 3 transmits a group of signals RQj (j being an integer, e.g., between 1 and 6), and commonly connects to all RDD packages. More generally, signals RQj include all signals except data signals, e.g., command signals and power supply voltage VDD.

In FIG. 4, each RDD package has (16M×8) organization, and a pair of a non-rotated package and a rotated package (RDD 1 , RDD 2 ) or (RDD 3 , RDD 4 ) operates as a 16M×16 RDD. As described above, bus BUS 3 connects to all of the RDD packages, but buses BUS 1 and BUS 2 connect to alternate RDD packages. Thus, buses BUS 1 , BUS 2 , and BUS 3 must be designed to have different impedances so that the impedance of the bus BUS 3 with connected control terminals matches the impedance of bus BUS 1 or BUS 2 with the connected data terminals. The different orientations of RDD packages causes particular control pins to be in different relative location for even-numbered and odd-numbered packages, which can complicate the layout of bus BUS 3 . However, in accordance with a further aspect of the invention, the odd-numbered RDDs can have a pin assignment that differs from the pin assignment of even-numbered RDDs so that matching control terminals lie along the same line on the RiMM.

FIG. 5 illustrates a RiMM according to another embodiment of the present invention in which each of buses BUS 1 and BUS 2 connects to every RDD package. Odd-numbered RDD packages, such as RDD 1 and RDD 3 , are mounted on printed circuit board SUB with one orientation, and even-numbered RDD packages, such as RDD 2 and RDD 4 , are mounted on printed circuit board SUB with an orientation rotated by 180° with respect to the odd-numbered RDD packages. Bus BUS 1 connects data pins of the odd-numbered packages RDD 1 and RDD 3 and to dummy pins of the even-numbered RDD packages RDD 2 and RDD 4 . Similarly, bus BUS 2 connects to the data pins of the even-numbered packages RDD 2 and RDD 4 and to dummy pins of the odd-numbered RDD packages RDD 1 and RDD 3 . The dummy pins are not connected to active circuits inside the RDD packages, but each dummy pin provides an impedance approximately matching the impedance of a data pin or control pin. Thus, buses BUS 1 , BUS 2 , and BUS 3 can be designed to have the same impedance and retain impedance matching when connected to the RDD packages.

A drawback of the RiMM of FIG. 5 is the complexity of routing of bus BUS 3 to connect to the appropriate control pins. However, in an alternative embodiment of the inventions even and odd-numbered RDD have different pin assignments to simplify connection to bus BUS 3 .

FIGS. 6 and 7 illustrate a RiMM according to a still another embodiment of the present invention, in which two (16M×8) RDDs function as a (16M×16) RDD. In FIG. 6, odd-numbered RDD packages, such as RDD 1 and RDD 3 , are mounted on the front side of printed circuit board SUB, and even-numbered RDD packages, such as RDD 2 and RDD 4 , are mounted on the back side of printed circuit board SUB. For mounting on opposite sides of printed circuit board SUB, the even-numbered packages are flipped about an axis perpendicular to the direction of buses BUS 1 , BUS 2 , and BUS 3 relative to the odd-numbered packages. A view of a transparent RiMM from above, as in FIG. 6, shows the pin configurations of the odd-numbered RDD packages and the even-numbered RDD packages. In the view of FIG. 6, each odd-numbered RDD package partially overlaps an even-numbered RDD package, and printed circuit board SUB is between them. FIG. 7 shows two of the RDDs (RDD 1 and RDD 2 ) in a view that is the same as FIG. 6 except that the RDD 2 is shifted so that RDD 1 and RDD 2 no longer overlap. In this embodiment, DQ pins of the RDD packages are arranged along one side of the RDD packages, so that the DQ pins of the odd-numbered RDD packages do not overlap with the DQ pins of the even-numbered RDD packages.

Bus BUS 1 that transmits signals DQA is formed on the front of printed circuit board SUB and connected to DQ pins of the odd-numbered RDD packages. Bus BUS 2 that transmits signals DQB is formed on the back of printed circuit board SUB and connected to DQ pins of the package of the even-numbered RDD packages. Bus BUS 3 that transmits a signals RQ is commonly connected to all RDD packages.

In FIG. 6, the pair of RDD packages RDD 1 and RDD 2 function as a (16M×16) RDD. The pair of RDD packages RDD 3 and RDD 4 also function as a (16M×16) RDD. In addition, since not all of buses BUS 1 , BUS 2 , and BUS 3 connect to all RDD packages, buses BUS 1 , BUS 2 , and BUS 3 are designed to have different impedances.

FIGS. 8 and 9 illustrate a RiMM according to a still another embodiment of the present invention, in which two (16M×8) RDDs can function as a (16M×16) RDD. In FIG. 8, odd-numbered RDD packages, such as RDD 1 and RDD 3 , are mounted on the front of printed circuit board SUB, and even-numbered RDD packages, such as RDD 2 and RDD 4 , are mounted on the back of printed circuit board SUB. In this case, for mounting on opposite sides of printed circuit board SUB, the even-numbered packages are flipped about an axis along the direction of buses BUS 1 , BUS 2 , and BUS 3 relative to the odd-numbered packages. A view of a transparent RiMM from above, as in FIG. 8, shows the pin configurations of the odd-numbered RDD packages and the even-numbered RDD packages. In FIG. 8, each odd-numbered RDD package completely overlaps an even-numbered RDD packages. In particular, the DQ pins of the odd-numbered RDD packages are directly opposite the dummy or disconnected pins of the even-numbered RDD packages. FIG. 9 shows two of the RDDs (RDD 1 and RDD 2 ) in a view that is the same as FIG. 8 except that the RDD 2 is shifted so that RDD 1 and RDD 2 no longer overlap.

Each line of buses BUS 1 and BUS 2 connects to a DQ or dummy pin of each RDD package. In particular, bus BUS 1 connects to DQ pins of the odd-numbered packages RDD 1 and RDD 3 and to dummy pins of the even-numbered RDD packages RDD 2 and RDD 4 . Similarly, bus BUS 2 connects to dummy pins of the odd-numbered packages RDD 1 and RDD 3 and to DQ pins of the even-numbered RDD packages RDD 2 and RDD 4 . The dummy pins are not connected to the active circuitry in the respective packages. The pin assignments of dummy and DQ pins in the odd-numbered RDD packages are the same as the pin assignments of dummy and DQ pins in the odd-numbered RDD packages. The dummy and DQ pin assignments appear to differ in FIG. 9 because FIG. 9 shows RDD package RDD 2 is flipped relative to RDD package RDD 1 .

Each line bus BUS 3 connects to a control pin on each of the RDD packages. However, to achieve a configuration where each control pin on an odd-numbered RDD package directly opposes a corresponding control pin on an even-numbered RDD package, the even-numbered RDD packages have a control pin assignment that differs from the pin assignment of the odd numbered packages. In particular, control pins CA 1 and CB 1 connect to the same line of bus BUS 3 and to matching circuitry in respective RDD packages RDD 1 and RDD 2 . However, control pin CA 1 is near dummy pins of odd-numbered package RDD 1 , and control pin CB 1 is near DQ pins of even-numbered package RDD 2 . More generally, the pin assignments of control pins in odd-numbered RDD packages are the mirror image of the pin assignments of control pins in even-numbered RDD packages.

The pair of RDD packages RDD 1 and RDD 2 function as a (16M×16) RDD. The pair of RDD packages RDD 3 and RDD 4 also function as a (16M×16) RDD. In addition, since buses BUS 1 , BUS 2 , and BUS 3 connect to all RDD packages, buses BUS 1 , BUS 2 , and BUS 3 are designed to have the same impedance.

Although the invention has been described with reference to particular embodiments, the description is only an example of the inventor's application and should not be taken as limiting. Various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as defined by the following claims.