Highly sensitive capacitance comparison circuit

1. Field of the Invention

The present invention relates generally to circuits for measuring electrical capacitance and in particular to a circuit for comparing the relative value capacitances, the circuit finding use in precision electronic sensors and the like.

2. Background of the Invention

A wide range of sensor applications use capacitors as sensing elements. The signal to be measured modifies the capacitor and a sense circuit detects changes in the capacitance of the capacitor to produce a corresponding electrical output.

Position, for example, can be measured by attaching opposite plates of a capacitor to separate structures which will be moving with respect to each other. The capacitor formed by the plates will have a capacitance that is a function of the plate's separation. Thus measurement of the capacitance can provide an electrical output indicating relative position of the structures.

Capacitance position sensors are an attractive option for Micro Electro-Mechanical Systems (MEMS). Microscopic movable plate capacitors are easily integrated into MEMS and fabricated using the same integrated circuit techniques used to construct the MEMS. Unfortunately, at the MEMS scale, the changes in capacitance that can be effected by typical movements of the MEMS components are very small, for example 10 −17 Farads. What is needed is a precise and stable circuit capable of resolving such small capacitance changes.

The present invention provides a simple and accurate measurement of the relative size of two capacitors by connecting them in series, then monitoring the voltage at their junction as the series connected capacitors are alternately connected in a first polarity and a second polarity across an arbitrary power and ground connection. If the capacitors are exactly equal, the voltage at their junction will not change. If they differ, the voltage at the junction will be greater when the smaller capacitor is connected to ground and the larger capacitor is connected to the power connection. The changes in voltage, as a function of the switched polarity, may be detected with a comparator storing an earlier junction voltage in a reference capacitor for comparison at the next polarity switch with a later junction voltage. The offset voltage of the comparator may be nulled by modifying the voltage stored in the reference capacitor by the offset voltage provided by the comparator itself during a calibration mode.

Importantly, switching noise from the switching of the polarity of the series connected capacitors is managed by disconnecting the sensing comparator during the switching period.

Specifically, then, the present invention provides a capacitance comparison circuit for comparing the capacitance of a first and second capacitor. The circuit includes a switching network connecting the first and second capacitors to connect them in one of two modes. In the first mode, the first and second capacitor are in series between the power and ground connections with one terminal of the first capacitor connected to power and one terminal of the second capacitor connected to ground. In the second mode, the first and second capacitor are in series between the power and ground connections with one terminal of the second capacitor connected to power and one terminal of the first capacitor connected to ground. A voltage monitor compares the voltage at a junction of the first and second capacitor in the first mode to the voltage at the junction between the first and second capacitor in the second mode to provide an output signal indicating which of the first and second capacitors has greater capacitance and the switching network disconnects the voltage monitor in between the first and second modes.

Thus it is one object of the invention to provide a simple means of precisely comparing two capacitances without the need for precision voltage, time or capacitive references. The power connection may have an arbitrary voltage, so long as it is stable between the first and second mode, and the timing of the first and second modes is flexible. Disconnecting the voltage monitor from the switching capacitors during the switching process allows improved resolution of capacitor values to be obtained. In this way, a slight asynchrony between the operations of the switches of he switching networks such as might otherwise produce errors in the measurement, is tolerated.

The voltage monitor may include a third capacitor storing the voltage at the junction of the first and second capacitor in the first mode for later comparison to the voltage at the junction of the first and second capacitor in the second mode.

Thus it is another object of the invention to provide a simple means of comparing a voltage at two different times.

The voltage monitor may impose a reference voltage on the junction between the first and second capacitances during the first mode and the reference voltage may be substantially half a voltage of the power connection.

Thus it is another object of the invention to provide a well characterized voltage on the capacitors that will be within the operating range of circuitry used to analyze the change in voltage, such circuitry which will share the ground and power connections.

The voltage stored on the third capacitor may be a difference between the voltage at the junction of the first and second capacitor in the first mode and an offset voltage of a differential amplifier used to later compare the voltage on the third capacitor to the voltage at the junction of the first and second capacitors in the second mode.

Thus it is another object of the invention to null the effects amplifier offset voltages on the evaluation of the first and second capacitor such as allows differences in capacitance between these two capacitors to be more finely resolved.

The foregoing objects and advantages may not apply to all embodiments of the inventions and are not intended to define the scope of the invention, for which purpose claims are provided. In the following description, reference is made to the accompanying drawings, which form a part hereof, and in which there is shown by way of illustration, a preferred embodiment of the invention. Such embodiment also does not define the scope of the invention and reference must be made therefore to the claims for this purpose.

FIG. 1 is a simplified view of a sensor providing a mechanical transducer arm whose position is monitored by capacitors C 1 and C 2 whose changing capacitance with movement of the transducer arm may be detected by the capacitance comparison circuit of the present invention;

FIG 2 is a schematic diagram of the capacitance comparison circuit of FIG. 1 showing a switching network for changing a polarity of connection of the series connected capacitors C 1 and C 2 and an operational amplifier for detecting voltage changes at the junction C 1 and C 2 induced thereby;

FIG. 3 is a timing diagram for the switching network of the capacitance comparison circuit;

FIG.4 is a plot of the voltage response at the output of the operational amplifier;

FIG. 5 is a schematic diagram of capacitors C 1 and C 2 implemented with an inter-digitated MEMS structure;

In certain applications, a sensor 10 as shown in FIG. 1 includes an input stage 12 that receives an excitation signal and mechanically couples it to a detector 14 . The detector includes a pair of capacitors C 1 and C 2 connected to a transducer arm 16 . Mechanical movement of the transducer arm 16 changes C 1 and C 2 's relative capacitance values in opposition such that C 1 increases and C 2 decreases or C 1 decreases and C 2 increases depending upon the direction of movement.

The capacitors C 1 and C 2 may be designed as to have nominally the same value at a reference position of the transducer arm 16 . A capacitance comparison circuit 18 is connected to capacitors C 1 and C 2 and, by detecting the relative values of C 1 and C 2 , can determine the position of the transducer arm 16 relative to the null position.

As shown in FIG. 2, the capacitance comparison circuit 18 comprises a high impedance, high gain transconductance operational amplifier 102 having dual outputs followed by a comparator 104 and used in conjunction with a switched capacitor network 106 to determine the relative values of two series-connected capacitors C 1 and C 2 . The switched capacitor network 106 preferably switches four switch pairs S 1 , S 2 , S 3 and S 4 . The switch pairs may be implemented by solid-state devices, for example, CMOS devices well known in the art.

Switch pairs S 1 and S 2 operate to connect the series connected capacitors C 1 and C 2 between power and ground connections first in one direction and then in the opposite directions. More particularly, switch S 1 a (S 2 b ) couples the top of capacitor C 1 (bottom of C 2 ) to ground (GND), and switch S 1 b (S 2 a ) couples the bottom of capacitor C 2 (top of C 1 ) to power (Vdd) typically 5V.

Switch pair S 3 a , S 3 b connects the transconductance amplifier's non-inverting output 108 to its inverting input 110 and its inverting output 112 to its non-inverting input 114 , respectively.

Switch pair S 4 a , S 4 b connects the operational amplifier's differential inputs 110 and 114 to a junction 20 between C 1 and C 2 and to the top of a reference capacitor C 0 , respectively. Capacitor C 0 may have a capacitance equal to the parallel combination of C 1 and C 2 to charge balance the operational amplifier when switch pair S 3 is closed.

The transconductance amplifier's non-inverting and inverting outputs 108 , 112 are applied to the comparator's non-inverting and inverting inputs 116 and 118 , respectively. A pair of diodes 120 and 122 is connected in an anti-parallel configuration across the outputs of the amplifier to prevent the amplifier from saturating by clamping its output to a maximum voltage. This allows the transconductance amplifier to recover quickly during the calibration cycle to be ready for the next measurement cycle.

As illustrated in FIG. 3, the switch network preferably actuates switch pairs S 1 , S 2 , S 3 and S 4 at a high sampling rate, e.g. 1 MHz, to repeatedly execute calibration, transition and measurement phases 130 , 132 and 134 , respectively, to determine the relative sizes of capacitors C 1 and C 2 . During the calibration phase (first mode), the circuit establishes a reference voltage at the junction 20 between capacitors C 1 and C 2 and across reference capacitor C 0 . With switches S 1 and S 4 closed and S 2 open, switches S 3 are closed thereby shorting each of the transconductance amplifier's double-sided outputs to its inverse inputs. This establishes the reference voltage at the center of the supply range while simultaneously reflecting the transconductance amplifier's offset voltage to its inputs to eliminate DC offset. For example, with the Vdd equal to 5 volts and a 15 mV transconductance amplifier offset, the reference voltages at the junction 20 and C 0 would be 2.515V and 2.5V, respectively. The reference voltage does not have to be set at one-half the supply, doing so provides the maximum and most balanced swing.

The capacitance comparison circuit 18 enters the transition phase 132 by opening switch pair S 4 to isolate the transconductance amplifier 102 . Switch pairs S 1 and S 2 are opened and closed, respectively, to reverse the supplies thereby providing a switched voltage across the two capacitors C 1 and C 2 . If C 1 and C 2 are equal, then the resultant charge flow between the capacitors C 1 and C 2 will cause the voltage at the junction 20 to return to the reference plus offset voltage, producing a true input differential of 0V. If C 1 and C 2 are not equal, charge on the capacitors will redistribute causing the voltage at the junction 20 to move to a different value. For example, if C 1 >C 2 by just a small amount, then the voltage at the junction 20 moves higher to, for example, 2.517V, producing a true input differential of 0.002V.

Once the voltage at the junction 20 settles, the measurement phase (second mode) is initiated by first opening switch pair S 3 and then closing switch pair S 4 to apply the junction voltage and the reference voltage at the top of C 0 to the transconductance amplifier. This differential input is amplified and applied to the comparator which outputs a digital signal. The digital signal is sampled during the measurement phase by a latch 119 to provide an output indicating the relative size of C 1 and C 2 . Sensitivity to small differences in C 1 and C 2 is enhanced by eliminating the transconductance amplifier's offset voltage, sampling the junction voltage at a high rate to eliminate the effect of any drift in the power supplies, and amplifying the differential input.

As illustrated with ideal waveforms in FIG. 4, the sense circuit samples at, for example, a 1 microsecond sample period (1 MHz sampling rate) and produces a differential voltage 140 that is applied to the comparator. At the beginning of the calibration phase 130 , the establishment of the reference voltages as described above applies a true input differential of zero volts at the input of the transconductance amplifier. More particularly transconductance amplifier outputs 108 and 112 merge to the same voltage when switches S 3 close during calibration. This produces a zero differential voltage throughout the calibration and transition phases 130 and 132 to prepare the comparator for the measurement phase.

At the onset of the measurement phase 134 , assuming C 1 does not equal C 2 , a non-zero true input differential voltage is applied to the transconductance amplifier input and held throughout the measurement phase. The resulting differential output voltage 140 is applied to the comparator over the measurement period until the latch 119 is clocked near the end of the measurement phase. For example, with an amplifier gain of 100, a 0.002V differential input signal would be amplified to 0.2V. Since the circuit is operating at a high sampling rate the amplifier's slew rate must be taken into account. With an example slew rate of 50, the expected 0.2V output, due to amplifier gain alone, will yield an actual output of 0.1V. This 0.1V overcomes the comparator offset 142 such that the comparator makes a valid comparison and outputs a digital signal. Resolutions on the order of 16 bits have been demonstrated.

Resolutions can be further improved by increasing the sample period. The tradeoff is increased delay, possible capacitor droop due to leakage current through the switches and amplifier drift.

Although the sense circuit is generally applicable to compare any two capacitors C 1 and C 2 , its high sensitivity make it particularly well suited for MEMS applications such as current sensors, accelerometers, pressure sensors, and voltage detectors. In the case of voltage and current sensors, the input stage 12 of FIG. 1 must provide an actuation of the transducer arm 16 dependent upon voltage or current respective.

A suitable configuration for MEMS capacitors C 1 and C 2 in typical MEMS applications is shown in FIG. 5 . In this case, capacitors C 1 and C 2 change in opposition to each other in response to the movement of a common bridge element 150 , which is suspended above substrate 156 and coupled to the input stage (not shown). Note, capacitors C 1 and C 2 may be configured to change in opposition without sharing a common bridge element. Capacitor C 1 includes a pair of inter-digitated fingers 152 a and 152 b that are connected to a contact 154 on substrate 156 and bridge element 150 , respectively, and suspended above underlying substrate 156 . Capacitor C 2 includes a pair of inter-digitated fingers 158 a and 158 b that are connected to a contact 160 on substrate 156 and bridge element 150 , respectively, and suspended above underlying substrate 156 . Bridge element 150 is mechanically coupled to a conducting bridge 164 that is suspended between contacts 166 a and 166 b , one of which provides junction 20 .

In this particular configuration, a force applied to bridge element 150 that causes it to move to the right reduces the overlap between inter-digitated fingers 152 a and 152 b and increases the overlap between inter-digitated fingers 158 a and 158 b thereby reducing capacitor C 1 and increasing capacitor C 2 . A force that causes the bridge to move in the opposite direction increases C 1 and reduces C 2 . The structure is configured so that in its relaxed state C 1 is nominally equal to C 2 . Any number of input stages can be configured to exert a force on bridge element 150 to cause C 1 >C 2 or vice-versa in response to an excitation signal. The sense circuit detects the relative values of the capacitors and outputs a digital signal.

It is specifically intended that the present invention not be limited to the embodiments and illustrations contained herein, but that modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments also be included as come within the scope of the following claims. For example, while the circuitry shown provides a preferred embodiment of the capacitance comparison circuit 18 , the functions of setting a reference voltage, compensating for amplifier offset may not be required in certain embodiments covered by the claims.