Adaptive amplifier circuit with enhanced dynamic range

The present application is related to U.S. patent application Ser. No. 09/675,278, entitled “SELF-ADJUSTING ADAPTIVE MINIMAL NOISE INPUT AMPLIFIER CIRCUIT”, filed Sep. 29, 2000; and is also related to U.S. patent application Ser. No. 09/675,487, entitled “HIGH GAIN DETECTOR AMPLIFIER WITH ENHANCED DYNAMIC RANGE FOR SINGLE PHOTON READ-OUT OF PHOTODETECTORS”, filed Sep. 29, 2000; the disclosures of which are herein incorporated by reference.

1. Field of the Invention

The present invention relates to interface circuits for focal plane arrays (FPAs) and, specifically, to an adaptive amplifier circuit that uniquely provides high charge-handling capacity for coupling long wavelength IR detectors to multiplexing readouts with both maximum sensitivity and enhanced dynamic range.

2. Description of the Related Art

Infrared sensors transform incident radiant signals in the near infrared (NIR; λ=0.8-2 μm), short wavelength IR (SWIR;λ=2.0-2.5 μm), medium wavelength IR (MWIR;λ=2.5-5 μm), and long wavelength IR (LWIR;λ=5-30 μm) bands into electrical signals that are used for data collection, processing, storage and display, such as real-time video. For high-quality imaging of various scenes without concern for ambient light, the MWIR and LWIR bands are often used interchangeably. However, MWIR infrared detector systems typically require sophisticated signal processing algorithms to accommodate the large dynamic changes in background information that result from the relatively high contrast and large solar influence of the scene radiation. Detectors operating in the preferred long wavelength infrared (LWIR) spectral band, on the other hand, can attain the same or greater thermal sensitivity with reduced signal processing complexity. This is especially true in the 8 to 12 μm wavelength atmospheric window, which is optimum for imaging many terrestrial scenes. As a result, infrared detection and tracking can be accomplished using smaller, more cost-effective sensors having LWIR focal plane arrays.

Unfortunately, LWIR focal plane arrays and multiplexing readout circuits have practical design constraints that severely limit system performance. The result is degradation in signal-to-noise ratio by >10× below the theoretical limit. In the readout portion of a focal plane array, each pixel has an preamplifier to couple the signal from each detector into the respective unit cell. The corresponding readout site must perform several functions that are difficult to simultaneously incorporate in the small amount of “real estate” typically available on such a signal-processing chip. Ideally, each detector/amplifier cell of an FPA should include the following: 1) a detector interface stage that provides low impedance at a uniform operating bias; 2) an integration capacitor with large charge-handling capability; 3) a stage for uniform suppression of the background if integration capacity is inadequate; 4) facility for low-power multiplexing and reset; 5) an output buffer capable of driving the bus line capacitance for subsequent multiplexing of the electrical signal at video rates; and 6) a sufficiently large transimpedance to enable sensor-limited rather than camera-noise-limited performance; i.e., the output-referred noise level of the shot noise at the lowest background must be easily measurable by conventional camera electronics.

Staring LWIR FPAs in formats up to 1024 by 1024 have now been demonstrated in the prior art. However, these LWIR devices are typically coupled to conventional MWIR readout circuits, which have several deficiencies that compromise system performance. The limited charge-handling capacity, for example, supports camera sensitivity no better than that achieved by a typical MWIR FPA. This obviates a key benefit of operation in the LWIR spectral band. Moreover, prior art devices limit capability for reducing pixel pitch and increasing pixel density. If the pixel pitch and detector/amplifier cell real estate are reduced in prior art devices, the performance limitations are further exacerbated.

Given the current photolithographic state-of-the-art and the limited chip area, there is insufficient detector/amplifier cell real estate to integrate even the most important features including the ability to directly handle all the charge that can be generated during the full frame time. Nevertheless, because small cells are necessary for FPAs with high pixel counts that can be used with compact optics, the readout circuit must be integrated in as little chip real estate as possible. Thus, there is a need for a compact amplifier having characteristics that are better optimized for use in staring LWIR FPAs.

U.S. Pat. No. 5,128,534 teaches the technique of biasing a capacitor with a variable voltage source to increase the amount of charge that can be effectively integrated on an integrating capacitor (of the typical size that can readily fit into a standard unit cell). This improves the signal-to-noise ratio of the focal plane array by clipping excess signal. The enhancement in capacity is a trade-off for a nonlinear dynamic range; this non-linearity is not optimum for LWIR imaging since the signal of interest is a small fraction of the background radiation.

U.S. Pat. No. 5,055,667 and U.S. Pat. No. RE34,802 also disclose nonlinear techniques for visible CCD imagers. These methods control the dynamic range of a CCD in a manner somewhat analogous to U.S. Pat. No. 5,128,534 by providing a sink region to dispose of excess charge from the photogate region by clipping any signal above the potential set by a control gate where the potential can be similarly modulated during the exposure period. Such predetermined fluctuation can facilitate various transfer functions including logarithmic behavior. Such characteristics are not optimum for LWIR imaging.

U.S. Pat. No. 5,382,977 proposes an alternative that effectively enhances the linear charge-handling capacity via electronic scanning. Since the total charges accumulated during a typical frame time ({fraction (1/60)} th second) can exceed 10 10 carriers while the typical integration capacitor can only handle on the order of mid-10 7 carriers, this method accepts the ˜100× disparity between the two to extend the linear capacity to approximately 10 9 carriers. Unfortunately, all the available charges for each frame time are not used so maximum sensitivity is impossible. The inefficiency translates to a proportional reduction in the effective quantum efficiency of the imaging sensor.

U.S. Pat. No. 5,146,302 again teaches skimming in a CCD to enhance the linear charge-handling capacity. To improve efficacy, a sampling circuit comprising a tandem input is used to generate a prescribed skimming voltage. However, the non-uniformity in threshold voltages between the input gates of the main input and the sampling input sets a limit on the amount of charge that can be skimmed. This limit is typically no more than 3 times the instantaneous charge-handling capacity. The linear capacity is thus effectively increased to the order of 10 8 carriers. A further improvement of two orders of magnitude is still needed.

Finally, U.S. Pat. No. 6.064,431 discloses a circuit for skimming to linearly enhance the effective charge-handling capacity. This circuit, shown in FIG. 1, provides automatic control of the skimming charges to be transferred. Here the capability for predetermined sinking of excess signal, as taught by U.S. patents '534, '667 and '802 noted above, is combined with conventional skimming, as taught by the '302 patent, to further enhance the effective charge-handling capacity. In principle, the 2× to 3× enhancement of '302 patent can be enhanced to yield several orders of magnitude enhancement in charge-handling capacity. Unfortunately, the improvement is again non-linear and thus not optimum for infrared applications.

In general, the present invention provides an adaptive amplifier circuit, having minimal excess noise and a linear charge-handling capacity exceeding 10 10 electrons, to enable high-quality imaging at long wavelength infrared backgrounds and video frame rates. The present invention supports various types of photovoltaic and photoconductive detectors, and largely reduces the fixed pattern noise relative to the prior art. Since the circuit does not discriminate between dark current and photocurrent, it can also be used to operate MWIR detectors at elevated operating temperatures including room temperature. The adaptive detector amplifier circuit comprises either impedance-buffered or direct injection detector interface with self-nulling skimming of the background signal and self-adapting offset suppression. An adaptive skimming circuit skims off excess charge during the integration of charge on an integration capacitor. These features are integrated in conjunction with a compact low-pass filter at the pixel output to recover the instantaneous dynamic range. Such recovery is necessary since the skimming serves to boost the noise level at the expense of dynamic range. The net outcome is LWIR FPA sensitivity commensurate with a charge-handling capacity of 10 10 carriers and a dynamic range in excess of 14 bits. In the context of LWIR imaging, for example, the noise equivalent temperature difference that is achieved is on the order of 0.001 K, which is well over an order of magnitude better than the LWIR staring FPA state-of-the-art. The front-end provides very uniform skimming without significantly increasing the read noise.

This solution fits into the typical pixel pitches normally used for single-photon detection (≧20 μm) to amplify the photo-generated signal for subsequent processing or display. The resulting video has large margin over the background noise of the camera electronics.

The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:

FIG. 1 is a schematic diagram of a prior art technique for enhancing dynamic range as shown in U.S. Pat. No. 6,064,431;

FIG. 2 is a schematic diagram for a preferred embodiment of an enhanced adaptive amplifier circuit with minimal noise input;

FIG. 3 is a schematic diagram for an adaptive amplifier circuit with minimal noise input and impedance-buffered interface to the photodetector; and

FIG. 4 is a cross-section plan for an alternative embodiment of the invention to facilitate highest performance by vertically integrating the amplifier circuit.

The following description is provided to enable any person skilled in the art to make and use the invention and sets forth the best modes contemplated by the inventor for carrying out the invention. Various modifications, however, will remain readily apparent to those skilled in the art, since the basic principles of the present invention have been defined herein specifically to provide to a self-adjusting adaptive amplifier circuit that uniquely provides high charge-handling capacity for optimally coupling IR detectors to multiplexing readouts with both maximum sensitivity and enhanced dynamic range in high-density staring FPAs. Any and all such modifications, equivalents and alternatives are intended to fall within the spirit and scope of the present invention.

The present invention provides a high-performance detector amplifier to support each pixel of an infrared focal plane array. According to the various embodiments of the present invention, one benefit of the various features of the present invention is the simultaneous achievement of very high sensitivity with extended dynamic range of at least 14 bits. A second benefit is an output signal that is rich with signal content rather than parasitic nonuniformities. The usable dynamic range of most high-performance thermal images is limited by the fixed pattern noise arising from offset variations in the detector and amplifier.

A first embodiment of the present invention is shown in FIG. 2 . The amplifier circuit 2 comprises a detector PD 1 that is directly coupled to the source of an input transistor Q 20 . The gate of Q 20 is adjusted to set the detector bias and the source of Q 20 is modulated by the photo-generated signal from PD 1 . Minority carriers are injected into an integration capacitor C int in the adaptive skimming circuit, where they are accumulated for subsequent readout. The integration capacitor C int is preferably formed using a MOSFET having its source and drain connected. The adaptive skimming circuit 200 skims off excess charge during the integration of charge on an integration capacitor. A suitable adaptive skimming circuit is disclosed in, for example, U.S. patent application Ser. No. 09/675,278, entitled “SELF-ADJUSTING ADAPTIVE MINIMAL NOISE INPUT AMPLIFIER CIRCUIT”, filed Sep. 29, 2000, the disclosure of which is herein incorporated by reference.

An integration capacitor C int in the adaptive skimming circuit 200 is connected to a switched-capacitor low-pass filter comprising transistors Q 30 and Q 31 , and capacitors C filter and C out . The signal φ filter , which is a clock that essentially parses the frame time into N integration periods, is applied to the gate of Q 30 to successively sample the signal charges integrated in C int onto C filter . The charge on C filter is then shared over to the output capacitor C out . Since C filter is relatively small, a smaller fraction of the charge is stored onto C out . This cycle is repeated N times during the frame time so that the cumulative voltage on C out exponentially reaches equilibrium. While the signal builds exponentially as described, the associated noise also adds exponentially, but in quadrature. The enhancement in linear charge-handling capacity for this stage relative to integration on C int over a single epoch without skimming is consequently: N boost 2 = 1 - η N 1 + η N · 1 + η 1 - η

where N is the number of cycles. η is an efficiency factor described by the equation: η = C filter C filter + C int + C out C out + C filter - C filter C filter + C int · C out C out + C filter

The total enhancement in charge-handling capacity effected by the entire circuit is multiplicative and becomes: N boost , total =    N boost 1 · N boost 2 ≥    10 · 1 - η N 1 + η N · 1 + η 1 - η

Since C int and C out are on the order of 1 pF and C filter is optimally chosen to be about an order of magnitude smaller, η>0.9 is achieved in practice. Assuming N=25, a minimum charge-handling capacity enhancement factor well in excess of 100× is provided by the present invention.

A source follower transistor Q 24 buffers the signal and an access transistor Q 25 supplies the signal to the bus. A common current source CS 1 may be connected to the bus and shared by all the pixels on the bus.

The key aspects of the present self-adjusting adaptive input with minimal noise circuit are applicable to other types of circuits used for interfacing infrared detectors. For example, FIG. 3 is a schematic circuit of an alternative embodiment for use with lower impedance detectors PD 2 , such as those fabricated in the HgCdTe ternary system for operation at cutoff wavelengths beyond 12 μm at operating temperatures above 60 K. The negative feedback provided by amplifier 500 enhances the injection efficiency of detector current into the integration capacitor C int by decreasing the input impedance of source-modulated transistor Q 520 . The inverting amplifier can be of many types known to those of ordinary skill in the art, such as a basic CMOS inverter, a basic differential amplifier, or a folded cascode differential amplifier, among others. Regardless, the amplifier will also luminesce and must be optically shielded for proper operation of the skimming input circuit.

To incorporate the desired capacitances of the present invention, pixel real estate can still be at a premium as pixel pitches reduce to 20 μm and lower. In this case, it is best to use vertical integration. FIG. 4 is a cross-section plan where the vertical integration is achieved by combining the circuit integration provided by bulk CMOS with SOI CMOS. A part of the circuit is incorporated in the bulk CMOS constituent. The other part of the circuit is incorporated in the SOI CMOS wafer. The SOI CMOS wafer is subsequently filcher processed to remove the handle wafer. The thinned SOI material is subsequently transferred by thin-film transfer such as taught in U.S. Pat. No. 5,627,112, herein incorporated by reference.

Those skilled in the art will appreciate that various adaptations and modifications of the just-described preferred embodiments can be configured without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.