Method and system for dynamic compensation

This application claims priority under 35 USC §119(e)(1) of provisional application No. 60/152,664 filed Sep. 7, 1999.

This invention relates generally to the field of integrated circuits and more particularly to a method and system for dynamic compensation.

Integrated circuits often employ a variety of amplifiers, such as voltage regulators, to increase or decrease voltage levels within the integrated circuit. Amplifiers often have at least two poles in their frequency response that are associated with gain and phase behavior. Gain and phase behavior depends upon the circuit design of the amplifier, and can depend upon load circuitry associated with the amplifier.

Conventional amplifier circuits, including voltage regulators, may include an output stage that resembles a class A amplifier stage. Such designs are limited by the output storage capacitance of the circuit. Other designs may employ a class B output configuration with a generally low impedance output and internal compensation to maintain the amplifier within an operable range. Many of these circuit designs are used in applications or with loads having a range of transistor current requirements and load characteristics. However, these designs are often not able to maintain the amplifier within an operable range for these applications or for loads having varying requirements.

Amplifiers using field effect technology generally have high output impedance and the pole contributed by the output load is generally located at a relatively low frequency. Without a zero between the first two poles in the amplifier's frequency response, instability can result. Existing compensation schemes depend on the characteristics of the load. The location of the zero and one or more poles can be affected by the load, if the pole moves due to output load characteristics such that the zero designed into the frequency response for stability is no longer between the first two poles of the amplifier's frequency response. Thus, designing stable amplifiers is difficult without knowing beforehand the load characteristics. Often, however, load characteristics may not be known. Therefore, a system and method is needed to provide effective dynamic compensation for amplifier applications in integrated circuits.

One aspect of the invention is an integrated circuit comprising an amplifier having at least two poles in its frequency response and an output impedance compensation circuit coupled to an output node of the amplifier. The output impedance compensation circuit is operable to create a feedback signal proportional to the impedance of an output load coupled to the output node, and create a zero in the frequency response of the amplifier in response to the feedback signal between the at least two poles.

The invention provides several important advantages. Various embodiments of the invention may have none, some, or all of these advantages. The invention allows amplifiers in integrated circuits to operate stably under a wide variety of output load conditions. Generic amplifier designs, including voltage regulator designs, may thus be done without detailed knowledge of output load characteristics. Such amplifiers may have reduced circuit area in comparison to amplifiers with other compensation schemes, and may have improved power consumption.

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in connection with the accompanying drawings in which:

FIG. 1 illustrates a schematic diagram of an integrated circuit constructed in accordance with the teachings of the present invention; and

FIG. 2 illustrates a schematic diagram of another integrated circuit constructed in accordance with the teachings of the present invention.

The present invention and its advantages are best understood by referring to FIGS. 1 and 2, like numerals being used for like and corresponding parts of the drawings.

FIG. 1 illustrates a schematic diagram of an integrated circuit 10 constructed in accordance with the teachings of the present invention. It comprises amplifier 11 and load circuitry 50 . Amplifier 11 comprises two amplifiers, A 1 and AC 1 , a plurality of field effect transistors M 1 , M 2 , M 3 , M 1 A, and MA, and a capacitor C comp . These components couple input node 20 of amplifier 11 to output node 30 of amplifier 11 . Any suitable load circuitry 50 may be coupled to node 30 , whether analog or digital. Although direct connections are illustrated for various elements, many elements may be coupled through other elements without departing from the scope of the invention. As further detailed below, compensation circuitry such as transistors M 1 A, M 2 , M 3 and amplifier AC 1 may be coupled to any amplifier having at least two poles in its frequency response to dynamically compensate for variations in output loading, or load impedance, Z O at output node 30 . Such compensation circuitry may be used to introduce a zero between the two poles.

In this embodiment, amplifier 11 comprises a voltage regulator. For example, input 22 of amplifier A 1 is coupled to a reference voltage Vref at input node 20 , and input 21 is coupled to output node 30 to serve as voltage regulating feedback. Amplifier Al may represent an input differential pair of transistors, an operational amplifier, or any similar circuit. Field effect transistor MA may comprise part of a transconductance amplifier stage, where the gate of transistor MA is typically low-impedance. Although the invention may be used for regulators, it may also be used for other amplifiers without departing from the scope of the invention.

In this example, amplifier 11 utilizes a typical class AB configuration (e.g., a class A amplification stage with source-follower class B output). The output of amplifier A 1 is coupled to the gate of transistor MA, whose drain is coupled to a reference voltage V CP via a load. Reference voltage V CP may comprise any suitable power supply, such as a charge pump providing bias current. The drain of transistor MA is also coupled to capacitor C comp , and drives the gate of output transistor M 1 . Output node 30 couples to load circuitry 50 , which has a load impedance Z O . Load circuitry 50 may be digital or analog circuitry.

In this embodiment, the amplifier has at least two poles in the frequency response of the amplifier—a dominant pole and an output pole. A dominant pole of the two-stage amplifier may be determined by the high impedance node at the drain of transistor MA and the gates of output and sense transistors M 1 and M 1 A. This dominant pole may be determined by a C comp that is sized conservatively large enough to insure stable operation. The location in the frequency response of the output pole of the amplifier depends upon Z O and output transistor M 1 , and may vary as the impedance Z O changes.

Compensation circuitry may be coupled to the two-stage amplifier to form amplifier 11 and introduce a zero between the first or dominant pole of the amplifier and its next order pole. Such compensation circuitry may provide additional phase margin and maintain a separation between the two poles as impedance Z o varies over a wide range of values. Thus, the invention may reduce or eliminate the risk of instability of the amplifier due to variations in impedance Z O . For example, compensation circuitry as illustrated in FIG. 1 may be coupled between the drain of transistor MA and ground. In this embodiment, compensation circuitry comprises transistors M 1 A, M 2 , M 3 and amplifier AC 1 .

The drain of transistor MA drives the gate of sense transistor M 1 A. Transistors M 1 and M 1 A may be coupled together to a suitable reference voltage V PWR . The source of transistor M 1 is coupled to output node 30 and to input 28 of amplifier AC 1 . The source of transistor M 1 A is coupled to the drain of transistor M 2 , and to input 29 of amplifier AC 1 . The output of amplifier AC 1 drives the gates of transistor M 2 and compensation transistor M 3 . Finally, the drain of compensation transistor M 3 may be coupled to capacitor C Comp .

Field effect transistors M 1 , M 1 A, M 2 , and M 3 , when operating in their respective active regions, may act as adjustable resistors to dynamically compensate for changes in impedance Zo. Other types of transistors may also be used without departing from the scope of the invention. For example, bi-polar transistors and P-channel field effect transistors may also be used.

In operation, amplifier 11 dynamically compensates for variations in load impedance Z O at output node 30 . Current flows from V PWR to output node 30 through transistor M 1 . Because inputs 28 and 29 tend toward the same potential, the gate source voltage V gs of transistor M 2 will be generally proportional to current delivered to the load at output node 30 . Furthermore, the sources of transistors M 1 and M 1 A should tend toward the same potential. Thus, sense transistor M 1 A operates to sense the current drawn by load circuitry 50 through transistor M 1 in proportion to its size. Sizes for transistors M 1 A and M 1 may be configured as a W/L ratio to suit amplifier 11 design requirements such as cost and circuit area. Thus for example, where transistor M 1 is designed with W=1000 and L=1, and transistor M 1 A with W=10, typical sense current through the drain of transistor M 1 A is roughly {fraction (1/100)}th of the drain current drawn through transistor M 1 . In this embodiment, the source of transistor M 2 is grounded and thus V gs for compensation transistor M 3 will also be generally proportional to the current delivered to the load.

As the current delivered to output node 30 decreases, impedance Z O at output node 30 typically increases. In this embodiment, the dominant pole of the amplifier typically does not vary with impedance Z O . Compensation capacitor C comp sees an impedance that is dominated by a high impedance associated with the bias source. The output pole, however, does typically vary with the load impedance Z O . A zero to cancel the output pole varies with the ratio of the transconductance of compensation transistor M 3 and compensation capacitor C comp . Thus, as impedance Z O increases, sense current through the drain of transistor M 1 A decreases, and the transconductance of compensation transistor M 3 decreases by the reduction in V gs across transistor M 2 . As a result, the zero moves down in frequency in correspondence with the output pole, thereby forming a first-order dynamic load compensation. The compensation circuitry maintains the zero between the two poles even as one of the poles varies.

In decreased impedance conditions at output node 30 , the output pole typically moves out in frequency. In this case, both sense current through transistor M 1 A and the transconductance of compensation transistor M 3 increase by an increase in V gs across transistor M 2 . As a result, the zero moves out in frequency in correspondence with the pole, thus maintaining amplifier 11 stability.

FIG. 2 illustrates a schematic diagram of another integrated circuit 110 constructed in accordance with the teachings of the present invention. It comprises amplifier 111 and load circuitry 50 . In this embodiment, amplifier 111 comprises a voltage regulator constructed using the elements described in conjunction with FIG. 1, although the components are arranged slightly differently. In addition, transistor M 4 comprises a part of the compensation circuitry, coupling input node 20 of amplifier 111 to output node 30 of amplifier 111 . Thus, compensation circuitry comprises transistors M 1 A, M 2 , M 3 , M 4 and amplifier AC 1 . In addition, transistor M 3 and compensation capacitor Cc are coupled between the drain and gate of transistor MA, rather than the drain of transistor MA and ground as illustrated in FIG. 1 .

Any suitable load circuitry 50 may be coupled to node 30 , whether analog or digital. Although direct connections are illustrated for various elements, many elements may be coupled through other elements without departing from the scope of the invention. As further detailed below, compensation circuitry such as transistors M 1 A, M 2 , M 3 , M 4 and amplifier AC 1 may be coupled to any amplifier having at least two poles in its frequency response to dynamically compensate for variations in output loading, or load impedance, Z O at output node 30 . This compensation circuitry may also be used to introduce a zero between the two poles of an amplifier, as is described in conjunction with FIG. 1 .

In this example, the source of sense transistor M 1 A is coupled to the drains of field effect transistors M 2 and M 4 . The source of transistor M 2 is coupled to the gate of transistor M 4 , and a current bias to ground. In operation, amplifier AC 1 drives the gates of transistors M 2 and M 4 to match the source voltages for transistors M 1 and M 1 A. Thus, the drain currents of M 1 and M 1 A are typically close in ratio to their sizes, as is discussed in conjunction with FIG. 1 .

Amplifier 111 may dynamically compensate for variations in transconductance of load 50 at output node 30 . In this embodiment, the impedance of transistor M 3 sets a zero to cancel the output pole associated with the impedance Z O of load 50 . Amplifier AC 1 drives the gates of transistors M 2 and M 3 , where V gs of transistor M 3 varies with the sum of V gs of transistor M 2 and the ratio of the current density to the transconductance of transistor M 4 . Transistors MA and M 2 may be similarly sized and biased to have the same current densities. The gate source voltage V gs for transistor M 3 is approximately equal to that for transistor M 4 . The transconductance of transistor M 4 varies with the transconductance, and thus current demand, of load 50 . Thus, as was discussed in conjunction with FIG. 1, this zero set by transistor M 3 varies with the transconductance of transistor M 1 , and thus load 50 , allowing stable operation of amplifier 111 for a variety of loads 50 .

As discussed in conjunction with FIG. 1, such compensation circuitry as illustrated in FIG. 2 may also be desirably used to maintain amplifier 111 in operable range as Z O varies. Similarly, it is also within the scope of the invention to utilize other compensation elements to achieve such dynamic compensation, such as p-channel MOSFETS or bipolar transistors. Further, the embodiment illustrated in FIG. 2 may desirably reduce circuit area needed for dynamic compensation. That is, C comp may be more area-efficient as a result of a Miller effect achieved by the gain of the MA transistor stage.

While the invention has been particularly shown and described by the foregoing detailed description, it will be understood by those skilled in the art that various other changes in form and detail may be made without departing from the spirit and scope of the invention.