Semiconductor memory device and method for the manufacture thereof

The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having a compact cell size and a method for the manufacture thereof.

As is well known, a dynamic random access memory (DRAM) having a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.

To meet the demand, therefore, there have been proposed several methods, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged a capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.

In attempt to meet the demand, there have been proposed a ferroelectric memory (FeRAM) where a capacitor thin film with ferroelectric properties such as strontium bithmuth tantalate (BST) is used for capacitors in place of conventional silicon oxide film or silicon nitride film.

In FIG. 1, there is shown a cross sectional view setting forth a conventional semiconductor memory device 100 for use as FeRAM. The semiconductor memory device 100 includes an active matrix 10 incorporating a metal oxide semiconductor (MOS) transistor therein, a capacitor structure 24 having a bottom electrode, a capacitor thin film and a top electrode, a bit line 34 and a metal interconnection 36 .

In FIGS. 2A to 2 E, there are illustrated manufacturing steps involved in manufacturing a conventional semiconductor memory device 100 shown in FIG. 1 .

The process for manufacturing the conventional semiconductor memory device 100 begins with the preparation of an active matrix 10 having a silicon substrate 2 , a MOS transistor formed thereon as a selective transistor, an isolation region 4 and a first insulating layer 16 formed on the MOS transistor and the isolation region 4 . The MOS transistor includes diffusion regions 6 as a source and a drain, a gate oxide 8 , a spacer 14 and a gate electrode 12 .

In a subsequent step, there is formed on top of the active matrix 10 a first metal layer 18 , a dielectric layer 20 and a second metal layer 22 , sequentially, as shown in FIG. 2 A. Both of the metal layers 18 , 22 are formed of titanium (Ti) and platinum (Pt) in which Ti is used for an adhesive layer. The dielectric layer 20 is made of a ferroelectric material. The first and the second metal layers 18 , 22 are deposited with a sputter and the dielectric layer 20 is spin-on coated.

Thereafter, the second metal layer 22 and the dielectric layer 20 are patterned into a predetermined configuration. And then, the first metal layer 18 is patterned into a second predetermined configuration by using a photolithography method, thereby obtaining a capacitor structure 24 having a bottom electrode 18 A, a capacitor thin film 20 A and a top electrode 22 A, as shown in FIG. 2 B.

In a next step, a second insulating layer 26 , e.g., made of silicon dioxide (SiO 2 ), is formed on top of the active matrix 10 and the capacitor structure 24 by using a plasma chemical vapor deposition (CVD), as shown in FIG. 2 C.

In an ensuing step, openings 28 , 30 , 32 are formed in the second insulating layer 26 and the first insulating layer 16 of the active matrix 10 at positions over the diffusion regions 6 of the MOS transistor and the capacitor structure 24 by reactive ion etching (RIE), as shown in FIG. 2 D.

Finally, a metal interconnection layer is formed over the entire surface including the interiors of the openings 28 , 30 , 32 , and is patterned to form a bit line 34 and a metal interconnection 36 , as shown in FIG. 2 E.

One of the major shortcomings of the above-described semiconductor memory device 100 and the method for the manufacture thereof is that it is difficult to decrease the cell area thereof since the location of the capacitor structure 24 is not aligned with that of the MOS transistor in vertical direction.

It is, therefore, an object of the present invention to provide a semiconductor memory device having a reduced cell area by forming a capacitor structure at a position over a transistor.

It is another object of the present invention to provide a method for manufacturing a semiconductor memory device having a reduced sized by forming a capacitor structure at a position over a transistor.

In accordance with one aspect of the present invention, there is provided a semiconductor memory device, including: an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate and a field oxide for isolating the transistor; a first metal line formed on top of the active matrix and extending outside the transistor; a capacitor structure formed over the transistor; and a second metal line formed on top of the capacitor structure to electrically connect the capacitor structure to the transistor through the first and the second metal line.

In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, the method comprising the steps of: a) preparing an active matrix provided with a semiconductor substrate and a transistor formed on top of the semiconductor substrate; b) forming a first metal layer and pattering the first metal layer into a first predetermined configuration to obtain a first metal line for electrically connecting the transistor thereto; c) forming an insulating layer on top of the first metal line; d) forming a capacitor structure at a position over the transistor; and e) forming a second metal layer and patterning into a second predetermined configuration to electrically connect the second metal line to the first metal line.

The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:

FIG. 1 shows a cross sectional view representing a prior art semiconductor memory device having a capacitor structure;

FIGS. 2A to 2 E are schematic cross sectional views illustrating a prior art method for the manufacture of a semiconductor memory device;

FIG. 3 is a cross sectional view setting forth a semiconductor memory device provided with a capacitor structure in accordance with the present invention; and

FIGS. 4A to 4 H are schematic cross sectional views setting forth a method for the manufacture of the semiconductor memory device provided with the capacitor structure in accordance with the present invention.

There are provided in FIGS. 3 and 4A to 4 H a cross sectional view of a semiconductor memory device 200 and cross sectional views setting forth a method for the manufacture thereof in accordance with preferred embodiments of the present invention. It should be noted that like parts appearing in FIGS. 3 and 4A to 4 H are represented by like reference numerals.

In FIG. 3, there is provided a cross sectional view of the inventive semiconductor memory device 200 comprising an active matrix 210 , a bit line 218 , a leading pad 220 , a capacitor structure 230 and a local interconnection line 238 .

The active matrix 210 includes a semiconductor substrate 202 , an isolation region 204 , diffusion regions 206 , a gate oxide 208 , a gate line 212 formed on top of the gate oxide 208 , a spacer 214 formed around the gate line 212 and a first insulating layer 216 . One of the diffusion regions 206 serves as a source and the other diffusion region 206 serves as a drain. In the semiconductor memory device 200 , the bit line 218 is electrically connected to one of the diffusion regions 206 and the top electrode 228 A of the capacitor structure 230 is electrically connected to the other diffusion region 206 through the leading pad 220 and the local interconnection line 238 , wherein the bit line 218 and the leading pad 220 are electrically disconnected each other. The bottom electrode 224 A may be connected to a plate line (not shown) to apply a common constant potential thereto. Although the electrical contact between the leading pad 220 and the local interconnection line 238 occurs at a position over the isolation region 204 , the electrical contact can occur at other positions provided that it gives rise to reduce the cell area of the semiconductor memory device 200 . It should be understood that the present invention is not limited to the use of any specific shape of the leading pad 220 and the local interconnection line 238 provided that they give the intended electrical operation to the semiconductor memory device 200 .

FIGS. 4A to 4 H are schematic cross sectional views setting forth the method for manufacture of a semiconductor memory device 200 in accordance with the present invention.

The process for manufacturing the semiconductor memory device 200 begins with the preparation of an active matrix 210 including a semiconductor substrate 202 , an isolation region 204 , diffusion regions 206 , a gate oxide 208 , a gate line 212 , spacers 214 and a first insulating layer 216 . One of the diffusion regions 206 serves as a source and the other diffusion region 206 serves as a drain.

Thereafter, the first insulating layer 216 , made of a material, e.g., boron-phosphor-silicate glass (BPSG), is patterned into a predetermined configuration by using a method such as a photolithography method to open top portions of the diffusion regions 206 . And then, a first interconnection metal layer is formed on top of the active matrix 210 and patterned into a first predetermined configuration, thereby obtaining a bit line 218 and a leading pad 220 , as shown in FIG. 4 B. It should be noted that the bit line 218 and the leading pad 220 be formed during the same process. The first predetermined configuration is divided into a first shape corresponding to the bit line 218 and a second shape corresponding to the leading pad 220 . The first interconnection metal layer can be made of a conducting material including, but not limited to: polysilicon doped with phosphorus (P), titanium silicide (TiSi 2 ), tungsten silicide (WSi 2 ), and the combination thereof or the like.

In an ensuing step, a second insulating layer 222 , made of a material, e.g., BPSG, is formed on top of the bit line 218 , the leading pad 220 and the active matrix 210 by using a method such as a chemical vapor deposition (CVD) and made flat by means of chemical mechanical polishing (CMP), as shown in FIG. 4 C.

In the subsequent step, a first metal layer 224 , a dielectric layer 226 and a second metal layer 228 are formed on top of the flat second insulating layer 222 , subsequently, as shown in FIG. 4 D. In the preferred embodiment, both of the first and the second metal layers 224 , 228 can be formed of a material such as platinum (Pt), iridium (Ir), ruthenium (Ru) or the like. And also, it is possible that both of the first and the second metal layers 224 , 228 can be made of a material such as IrO 2 , RuO 2 , LaSrCoOx or the like. The dielectric layer 226 can be made of a ferroelectric material such as SBT(SrBiTaOx), PZT(PbZrTiOx) or the like.

Thereafter, the second metal layer 228 and the dielectric layer 226 are patterned into a second predetermined configuration to obtain a top electrode 228 A and a capacitor thin film 226 A. And then, the first metal layer 224 is patterned into a third predetermined configuration to obtain a bottom electrode 224 A, thereby obtaining a capacitor structure 230 having the bottom electrode 224 A, a capacitor thin film 226 A and a top electrode 228 A, as shown in FIG. 4 E. It is preferable that the size of the third predetermined configuration is larger than that of the second predetermined configuration for forming a plate line (not shown) during the following processes.

In a next step, a third insulating layer 232 , e.g., made of BPSG, is formed on top of the second insulating layer 222 and the capacitor structure 230 by using a method such as a plasma CVD and made flat by using a method such as CMP, as shown in FIG. 4 F. Although the semiconductor memory device 200 of FIGS. 3 and 4A to 4 H are illustrated in one transistor and one capacitor structure 230 , this is not intended as a limitation of the present invention. In other word, the memory device 200 may comprise, for example, two transistors and two capacitors, in which one capacitor stores data and the other capacitor structure stores the complementary value of the data.

In an ensuing step, openings 234 , 236 are formed in the third insulating layer 232 and the second insulating layer 222 of the active matrix 210 at positions over the capacitor structure 230 and the leading pad 220 by using a method such as a photolithography or a plasma etching, e.g., reactive ion etching (RIE), as shown in FIG. 4 G.

Finally, a second interconnection metal layer is formed over the entire surface including the interiors of the openings 234 , 236 , and is patterned into a preset configuration to form a local interconnection metal line 238 , as shown in FIG. 4 H. For example, the second interconnection metal layer can comprise a conductive material such as titanium nitride (TiN), polysilicon doped with phosphorus, TiSi 2 , WSi 2 , Pt or the like. In the figures, each of the layers is shown as that having a single layer structure for simplification.

In comparison with the prior art, the present invention can reduce the cell area of the semiconductor memory device 200 by forming the capacitor structure 230 at a position over the gate line 212 . This is achieved by utilizing the leading pad 220 and the local interconnection line 238 .

Further, the present invention has an advantage that it needs not an additional process for forming the leading pad 220 since it is formed during the process for forming the bit line 218 .

Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claim.