Low distortion video analog-to-digital converter

1. Field of Invention

The present invention relates to an analog-to-digital (A/D) converter for image sensors. More particularly, the present invention relates to a low distortion video A/D converter for image sensor interfaces.

2. Description of Related Art

For general imaging applications, such as scanners, images from charge couple device (CCD) have to be processed to compensate for non-uniform illumination of a subject. In order to obtain a correct two-dimensional picture from the CCD signal, several corrections or adjustments must be performed. For example, gain and offset corrections account for the difference in sensitivity between red, green and blue signals. A video A/D converter is used not only for converting the analog image signal to a digital signal, but also performing these corrections and adjustments.

FIG. 1 shows a conventional block diagram of a video A/D converter. The video A/D converter comprises a correlated double sampling (CDS) module, an A/D converter (ADC) 110 , a DC restoring circuit 120 , and a plurality of adjustment circuits 130 , 140 , 150 and a timing control circuit 160 .

A typical CDS module 100 is illustrated in FIG. 2 for discussion of its operations. Referring to FIG. 2, the CDS module 100 comprises three CDS circuits and a 3-to-1 multiplexer 108 . All of the three CDS circuits have the same structure. Taking the first CDS circuit for sampling the analog red signal V R as an example, the first CDS comprises a first sample/hold circuit 104 a , a second sample/hold circuit 104 b and a differential amplifier 106 a . The first sample/hold circuit 104 a is driven by a control signal Vs and the second sample/hold 104 b is driven by a control signal Rs. The analog red signal V R from a CCD is inputted to the first and the second sample/hold circuits 104 a / 104 b through a capacitor C R .

The conventional CDS module uses three CDS circuits to sample the red, green and blue signals V R , V G and V B simultaneously. Accordingly, a signal Sc is simultaneously applied to the analog switches 102 a , 102 b and 102 c to clamp simultaneously the capacitors C R , C G and C B to a reset level (voltage V x ). The control signals Vs and Rs activate the sample/hold circuits 104 a / 104 b for sampling the red signal V R , the sample/hold circuits 104 c / 104 d for sampling the green signal V G , and the sample/hold circuits 104 e / 104 f for sampling the blue signal V B . The control signal Vs is applied to all of the first sample/hold circuits 104 a / 104 c / 104 e , and the control signal Rs is applied to all of the second sample/hold circuits 104 b / 104 d / 104 f.

After the analog switches 102 a / 102 b / 102 c are disabled, the sample/hold circuits 104 a / 104 b , 104 c / 104 d , and 104 e / 104 f begin to sample the red, green, and blue signal V R , V G , and V B respectively in response to the control signals Rs, Vs. As shown in FIG. 3, the sample/hold circuit 104 b begins to sample the red signal V R , obtaining a reset level voltage V 1 , when the control signal Rs is transient to high, while the sample/hold circuit 104 a begins to sample the red signal V R , obtaining a video signal voltage V 2 when the control signal Vs is transient to high. Thereafter, the differential amplifier 106 a receives the two input signals V 1 and V 2 , and then outputs the result to the multiplexer 108 . The operations for sampling the green and blue signals V G and V B are the same. The multiplexer 108 then selects one of the outputs of the differential amplifier 106 a , 106 b and 106 c and outputs an amplified signal V A to the ADC 110 at each clock period.

For the reasons discussed above, the conventional CDS module uses three CDS circuits for sampling the red, green and blue signals V R , V G and V B simultaneously, and consequently the noise level is high and an electric magnetic interference (EMI) problem always occur.

In addition, a practical problem with the CDS circuit is that the output node of the differential amplifier slews back and forth between a video signal level and an initialized reset level at each clock period. This increases a settling time of the differential amplifier. Furthermore, this slew back and forth phenomenon also causes signal distortions.

Referring to FIG. 1 again, the outputted signal V A from the CDS module 100 is then received by the ADC 100 for converting the analog signal V A to a digital signal first according to a constant reference voltage V REF . For example, when the ADC 110 outputs a digital red signal, the multiplexer 122 selects a DC bias from the red register 124 a to the DC restoring circuit 120 , the DC restoring circuit 120 then adds the DC bias to the digital red signal. Thereafter, the gain adjustment circuit 130 adjusts the gain of the digital red signal by multiplying a gain value selected by the multiplexer 132 from the red register 134 a . The offset adjustment circuit 140 and shading adjustment circuit 150 then adjust the offset and shading of the digital red signal by multiplying an offset and a shading value respectively selected by the multiplexers 142 , 152 from the red registers 144 a , 154 a.

Therefore, from the discussion above, the video signal is converted to digital in advance, and a number of adjustment operations, such as DC restoration, gain adjustment, offset adjustment and shading adjustment, are then performed in the digital domain. The majority of these adjustments are multiplication operations. However, due to the current technological limitations in speed and resolution, the data length (x-bit) of the digital output is limited to such as 12-bit, 14-bit or 16-bit, etc. Therefore, after each adjustment operation is performed, the generated data length is increased due to the multiplications, and must be truncated to meet data length requirement. The outputted signal is then distorted.

Accordingly, for the reasons discussed above, the conventional video A/D converter has several shortcomings. For example, a larger noise level and an EMI problem occur because all of the prime signals are sampled simultaneously. The slew back and forth phenomenon of the CDS circuit also causes signal distortions. In addition, all of the adjustment operations are performed by multiplication in digital domain, the outputted signal is then distorted because truncation of the data is necessary in view of the data length requirement.

The invention provides a video analog-to-digital converter, comprising a differential correlated double sampling (DCDS) module, a DC bias circuit, an adjustment module and an analog-to-digital (A/D) converter. The DCDS module is used for sampling a red, a green, and a blue analog signal respectively with a delay time, and then selecting one of the sampled red, green and blue analog signals for outputting. The DC bias circuit is connected to the DCDS module for performing an analog addition to the output signal of the DCDS module for the DC bias restoration. The adjustment module is used for converting a set of digital adjustment data to an analog adjustable reference voltage The A/D converter is connected to the output of the DC bias circuit and the output of the adjustment module. By referring the adjustable reference voltage, the A/D converter converts the analog input signal to a digital output signal.

The DCDS module further comprises three DCDS circuits for sampling the red, the green and the blue analog signals respectively, time delay circuits connected between the DCDS circuits, and a multiplexer is used for selecting one of the sampled red, green and blue analog signals as an output signal.

Advantageously, the DCDS circuit can overcome the slew back and forth phenomenon of the conventional CDS circuit. In addition, the restoration of the DC bias and all of the adjustments are performed in the analog domain to avoid the truncation that causes signal distortion. Furthermore, the time delay circuits are used in the DCDS module to avoid simultaneous sampling from the CCD sensor, thereby reducing the noise level and the EMI problem.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

FIG. 1 shows a conventional block diagram of a video A/D converter;

FIG. 2 illustrates a detailed circuit diagram of a correlated double sampling (CDS) circuit shown in FIG. 1;

FIG. 3 shows a timing chart for illustrating that the inputted video signal is sampled;

FIG. 4 schematically shows block diagram of a video A/D converter according to one preferred embodiment of the present invention; and

FIG. 5 schematically shows an exemplary circuit diagram of a differential correlated double sampling (DCDS) module shown in FIG. 4 .

In order to overcome the shortcomings of the conventional video A/D converter, the present invention provides a differential correlated double sampling (DCDS) circuit to overcome the slew back and forth phenomenon of the CDS circuit. In addition, the restoration of the DC bias and all of the adjustments are performed in the analog domain to avoid the truncation that cause signal distortion. Furthermore, time delay circuits are used in the DCDS module to avoid simultaneous sampling from the CCD sensor, thereby reducing the noise level and the EMI problem.

FIG. 4 schematically shows block diagrams of a video A/D converter 200 according to one preferred embodiment of the present invention. The video A/D converter 200 comprises a DCDS module 210 , a DC bias circuit 220 , an ADC 230 , a timing controller 250 , a rail-to-rail buffer 232 and an adjustment module 240 .

The DC bias circuit 220 comprises a summing circuit 221 , a digital-to-analog converter (DAC) 222 , a multiplexer 224 , and a number of registers 226 a-c.

The adjustment module 240 comprises a DAC 234 , a number of multiplexers 236 , 238 a-c , and a number of registers 241 / 242 / 243 .

The DCDS module 210 comprises three DCDS circuits and a multiplexer. The number of the DCDS circuits is determined by which primary color sequence is used. For example, if an R-G-B primary color sequence is used, three DCDS circuits are then used to sample analog color signals respectively. The CCD sensor generates three analog signals V R , V G and V B . The DCDS module 210 then receives the three analog signals V R , V G and V B and samples the three analog signals V R , V G and V B respectively by a delay time ΔT. Namely, when the red signal V R is sampled, the green signal V G is then sampled after a delay time ΔT; and when the green signal V G is sampled, the blue signal V B is then sampled after a delay time ΔT.

Therefore, the present invention overcomes the larger noise level and the EMI problem that occurs in the conventional video A/D converter due to simultaneous sampling of all the prime signals. The detailed operation and circuit of the delay time are described together with the DCDS module as following.

The multiplexer of the DCDS module 210 then selects one of the three sampled analog signals at each one-clock period. For convenience, the sampled red signal is used for description; the green and blue ones are the same and are omitted to avoid redundancy.

The adjustment operations arc then performed on the selected Output signal of the DCDS module 210 in the analog domain during the conversion from analog to digital. For example if the DCDS module 210 outputs a red signal, a DC bias has to be restored to the red signal first. Accordingly, the multiplexer 224 selects a red DC bias R dc from the register 226 a . The DAC 222 converts the red DC bias R dc from digital to analog. The summing circuit 221 sums the analog signal of the red DC bias R dc to the sampled red signal, and outputs signal V A .

After the DC bias is restored, the adjustments are further performed for adjusting the gain, offset, or shading in the analog domain. According to the present invention an adjustable reference voltage V AREF is used to perform the adjustment operations. For example, if the inputted analog signal V A is 2 V, the adjustable reference voltage V AREF can be adjusted to 2V to obtain a full-scale output, or adjusted to 4V to obtain a half scale output.

The registers 241 consisting of resisters R 1 , . . . , R n are used to store the data for the adjustment. The registers 242 and 243 have the same function. The multiplexer 238 a , such as an n-to- 1 multiplexer, is used for selecting one of the registers R 1 , . . . , R n . For example, the multiplexer 238 a selects data from the register R 1 to perform the adjustment on the analog signal V A . The multiplexer 236 then selects the output of the multiplexer 238 a , and the DAC 234 converts the output of the multiplexer 236 to an analog value. By choosing an adjustable reference voltage V AREF to scale the input signal V A, the ADC 230 then converts the input signal V A into a digital output. Similarly, all of the adjustment operations are performed in the same manner in the analog domain.

The adjustments are performed by scaling the input signal during the analog to digital conversion, rather than by multiplying values in digital domain. Contrary to the conventional video A/D converter, no extra bits occur and no truncation is needed. Accordingly, the original signals are not distorted.

Taking the output data length is 12-bit (b 0 , b 1 , . . . , b 11 ) as an example, the analog signal V A and the digital output b 0 , b 1 , . . . , b 11 are converted referring to the adjustable reference voltage V AREF by the following equation: V A = b 11 · 2048 4095 · V AREF + b 10 · 1024 4095 · V AREF + … + b 2 · 4 4095 · V AREF + b 1 · 2 4095 · V AREF + b 0 · 1 4095 · V AREF

As the adjustable reference voltage V AREF decreases, a larger digital output is obtained, which means that the signal V A is equivalently amplified. And, as the adjustable reference voltage V AREF increases, a smaller digital output is obtained; i.e., the signal V A decays equivalently. Therefore, the analog signal V A is equivalently adjusted by scaling the adjustable reference voltage V AREF .

According to the foregoing discussion, scaling the input signal during the analog to digital conversion performs all of the adjustments, and no truncation is necessary. Therefore, the outputted digital signals are not distorted.

FIG. 5 schematically shows an exemplary circuit diagram of the differential correlated double sampling (DCDS) module 210 shown in FIG. 4 . The DCDS module 210 comprises three DCDS circuits and a multiplexer 218 . All of the three DCDS circuits have the same structure. The multiplexer 218 can select one of the output signals from the three DCDS circuits for outputting.

Taking the first DCDS circuit for sampling the red signal V R as an example, the first DCDS circuit comprises a first sample/hold circuit 214 a , a second sample/hold circuit 214 b, a third sample/hold circuit 214 c and a differential amplifier 216 a . The first sample/hold circuit 214 a is driven by a control signal Vs and the second sample/hold circuit 214 b is driven by a control signal Rs. The additional third sample/hold circuit 214 c is used to enable the output of the second sample/hold circuit 214 b to the differential amplifier 216 a until the first sample/hold circuit 214 a samples the red signal V R .

Due to the third sample/hold circuit 214 c , the sampled signal by the second sample/hold circuit 214 b is synchronized with the control signal Vs. Then the inputs of the differential amplifier 216 a can receive the sampled values by the first and second sample/hold circuit 214 a / 214 b , thereby avoiding the slew back and forth phenomenon of the conventional CDS circuit.

Furthermore, time delay circuits are connected between the three DCDS circuits. For example, time delay circuit 219 a , 219 d and 219 c are respectively connected between the analog switches 212 a and 212 b , between the sample/hold circuit 214 b and 214 e , and between the sample/hold circuit 214 a and 214 d . Due to the time delay circuits 219 a - 219 f , the input red signal V R , green signal V G and blue signal V B are not sampled simultaneously. Therefore, the noise level and the EMI problem are reduced.

For the reasons discussed above, the conventional CDS circuit uses three CDS circuits for sampling the red, green and blue signals, V R , V G and V B , simultaneously; consequently, a larger noise level and an electric magnetic interference (EMI) problem always occur.

Advantageously, the present invention provides the DCDS circuit to overcome the slew back and forth phenomenon of the conventional CDS circuit. In addition, the restoration of the DC bias and all of the adjustments are performed in the analog domain to avoid the truncation that causes signal distortion. Furthermore, time delay circuits are used in the DCDS module to avoid simultaneously sampling from the CCD sensors, thereby reducing the noise level and the EMI problem.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.