Analog-to-digital converter

This application relies for priority upon Korean Patent Application No. 1999-22497, filed on Jun. 16, 1999, the contents of which are herein incorporated by reference in their entirety.

1. Field of the Invention

The present invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter operable in a high speed operation.

2. Background of the Invention

An analog-to-digital converter (ADC), converting an analog signal to a digital signal, has many applications in electronic signal processing systems. In particular, the ADC is becoming a more useful component in accordance with an increase of mixed-mode systems. It may be proper for the advanced mixed-mode systems, DVDP (digital video disk player) or DBSR (direct broadcasting for satellite receiver), which would be the foremost applications in the market of household electrical appliances, to be manufactured with low cost and in a one-chip by a CMOS process. For the purpose of that, it is important to provide an ADC capable of conducting a radio frequency (RF) signal of high bandwidth to the system. Such an ADC may be on desire of being operable in high frequency over 100 MHz and having the characteristic of a medium resolution.

Now, among the ADCs of various types proposed by now, “flash” ADC has been disclosed in IEEE Journal of Solid State Circuit on December 1979 (Vol. SC-14, pp. 926˜932) by Andrew G. F. Dingwall. In the Dingwall's flash ADC, an input signal is compared with reference voltages that are of different levels each other and converted into a digital signal at once, by means of amplifiers the number of which corresponds to a predetermined resolution. The flash ADC is advantageous for a fast conversion adaptable to an operating frequency of the one-chip mixed system even though it has a number of circuit elements. As shown in FIG. 1, the flash ADC is composed of reference voltage generator 10 , amplifying circuit 20 , and latch circuit 30 . The reference voltage generator 10 establishes 64 reference voltage levels Vref 1 ˜Vref 64 from two external reference voltages Vreft and Vrefb between which 65 resistors R 1 ˜R 65 are connected in serial. Pre-amplifiers PA 1 ˜PA 64 of the amplifying circuit 20 are differential amplifiers receiving the reference voltages Vref 1 ˜Vref 64 and input voltage Vin. Sixty-four latches L 1 ˜L 64 of the latch circuit 30 receives and stores amplified voltages VA 1 ˜VA 64 from the pre-amplifiers PA 1 ˜PA 64 . Each of output data bits DO 1 ˜DO 64 generated from the latch circuit 30 is set into six bits by a coding process.

Although the flash ADC of FIG. 1 can accomplish a function of fast and precise data conversion, there are static offsets (most physical) at the pre-amplifiers due to a variation of manufacturing process, external noises, or element parameters. The static offsets would cause the amplifying precise to be worse and a reliable conversion to degrade thereby. In order to eliminate the static offsets, there has proposed of “auto-zero function” in which sampling operations for the difference between the reference voltages Vreft and Vrefb and for the offsets at the pre-amplifiers are employed. However, such auto-zero function does not overcome a limitation of an increase of RC delay time due to sampling capacitors and an operation speed of the amplifier itself, being impossible to accomplish a flash ADC operable in a very high frequency over 100 MHz.

Other techniques to promote the processing speed of the ADC have been proposed in various types. In “A 200 Msample/S 6 b flash ADC in CMOS” (ISSCC Dig. Tech. Papers, Febuary 1996, pp. 320˜321), there is provided a specific period assigning to the auto-zero operation and inhibiting a normal operation of the ADC. Nevertheless, that is not available for a general application, just for very specific application.

In “A CMOS 6-b 200 Msample/s 3V supply converter for a PRML read channel LSI” (IEEE J. Solid State Circuit, Vol. 31, No. 11, pp. 1248˜1257, September 1996), dummy amplifiers are additionally provided thereto and the static offsets of the amplifiers are removed by activating the dummy and existed amplifiers in alternative operating modes. It needs a complex circuit arrangement in constructing switches for alternatively selecting the amplifiers and circuits for performing timing operations against the switches.

The fast accessing with a high frequency analog signal is determined by bandwidths and slew rates of analog blocks, while the processing speed with a digital signal accords mostly to a latching time, meta-stability, and a propagation delay time. Although the highest frequency of an analog input signal available to be converted into a digital signal is a half of a clock frequency (according to a theoretical analysis), it is substantial to obtain the operating frequency of 10˜20 MHz because of a weak current drivability with the analog circuit block even when the ADC operates in hundreds mega-Hertz. Such insufficient drivability occurs at the top and bottom amplifiers, e.g., PA 1 and PA 64 in FIG. 1, very seriously. Referring to FIGS. 2 A˜ 2 C, the top reference voltage Vref 1 as the lowest one is located too low, relative to the input voltage Vin. The small votage difference would cause instability of the amplifying operation due to short periods for high and low levels, PH and PL. Although the current drivability of the amplifiers PA 64 and PA 1 becomes larger therefrom to increase their amplifying ratios, it is hard to overcome the disharmony between the reference voltages. Since the increase amplifying ratios against the input voltage Vin also makes the swing-depth be larger, the amplifiers PA 64 and PA 1 can not generate their normal output voltages VA 64 and VA 1 of high and low levels when the input voltage Vin is higher than their corresponding reference voltages Vref 64 and Vref 1 , as shown in FIGS. 2A and 2B, respectively. The amplifiers PA 64 and PA 1 can do nothing but generating normal-low and high level output signals, VA 64 and VA 1 respectively. Furthermore, the larger swing depth due to the increased drivability causes timing discords between the input voltage Vin and the mostly one-sided output signals VA 64 and VA 1 , each of the output signals being incapable of following the oscillation of Vin. The two figures about VA 64 and VA 1 are extreme cases for the malfunction and timing discord. The nearer the top or bottom reference voltages is easier to cause the malfunctions with the output signals from the amplifiers. All those problems may act as a limitation of carrying out the fast conversion, restricting an allowable frequency that is desirable to be high in the ADC.

Accordingly, it is an object of the invention to provide an ADC capable of performing a faster conversion and a higher resolution.

In order to attain the above object, according to an aspect of the present invention, there is provided an analog-to-digital converter including: a reference generator circuit for generating a plurality of reference voltages; a plurality of amplifying comparators for recieving the reference voltages and analog input signals, each amplifing comparator including: two amplifying paths, each of which has a first amplifier and a second amplifier for alternatively receiving signals from the two paths; a latching comparator having a plurality of latches and receiving output signals from the amplifying comparator; and a digital decoder receiving output signals from the latching comparator and generating a predetermined number of data bits.

Amplifying periods through the two paths are overlapped for predetermined time each other. The amplifying comparator further includes a capacitor for sampling an offset voltage of the first amplifier; a first switch for shorting input and output terminals of the first amplifier; a second switch for resetting the output signals from the first amplifier into a predetermined voltage level in response to a clock signal; and a plurality of switches for controlling a transfer with the reference voltages, the analog input signals, and the output signals from the amplifiers.

The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.

The present invention will be described by way of exemplary embodiments, without limitations, illustrated in the accompanying drawings in which like reference symbols denote similar elements, and in which:

FIG. 1 shows a known construction of a flash ADC;

FIGS. 2A through 2C shows waveforms of the input voltage, reference voltages, and amplified voltage signals, assessing in amplifiers of FIG. 1;

FIG. 3 is a block diagram showing a construction of an ADC according to a preferred embodiment of the invention;

FIG. 4 is a circuit diagram showing an interconnection between the reference voltage generating circuit, the amplifying comparator, and the latching comparator employed in the ADC of FIG. 3, according to the preferred embodiment;

FIG. 5 is a circuit diagram of amplifiers arranged in the amplifying comparator shown in FIG. 4, according to the preferred embodiment;

FIG. 6 is a timing diagram of signals and voltages, being involved in the operation of the circuit of FIG. 5; and

FIGS. 7A and 7B show waveforms generated from the bottom and top amplifiers of FIG. 4, respectively.

It should be understood that the description of this preferred embodiment is merely illustrative and that it should not be taken in a limiting sense. In the following detailed description, several specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details.

The ADC according to the invention is embodied to be in use for 6-bit digital signals. Referring first to FIG. 3, the ADC includes reference voltage generator 40 including first and second reference voltage circuits 50 and 55 , switching controller 80 , amplifying comparator circuit 60 , latching comparator circuit 90 , and digital encoder 100 . The first reference voltage circuit 50 of the reference voltage generator 40 receives external reference voltages Vreft and Vrefb, and then generates the first group of reference voltages Vref* (32ea; hereinbelow, “*” denotes there are plural numbers each of which is a pair of bits). The second reference circuit 55 of the generator 40 receives external reference voltages VreftB and VrefbB (hereinbelow, the suffix “B” denotes the signal is a complementary signal), and then generates the second group of reference voltages Vrefb* (32ea). The switching controller 80 generates clock signal QL, switch control signals Q 1 , Q 1 N, Q 1 P, Q 2 , Q 2 N, and Q 2 P. The amplifying comparator circuit 60 includes a plurality of amplifying comparators, thereby comparing the reference voltages, Vref* and Vrefb*, with analog input signals INP and INN, and then generates signals VP* that are amplified signals with the difference between the reference signals and analog input signals. The latching comparator circuit 90 includes a plurality of latching comparators for holding the amplified signals VP* as digital signals DT* that are to be converted into 6-bit data by the digital encoder 100 . The feature of the detail interconnection from the reference voltage circuits 50 to the latching comparator circuit 90 , through the amplifying comparator circuit 60 , is disclosed FIG. 4 .

Referring to FIG. 4, the first reference voltage circuit 50 is formed of resistors R 1 ˜R 64 connected between Vreft and Vrefb in serial, and dividing nodes DN 1 ˜DN 32 which A are spaced by two resistors. Reference voltages Vref 1 ˜Vref 32 are established at the dividing nodes DN 1 ˜DN 32 , respectively. It should be understood that the second reference voltage circuit 55 in the reference generator 100 has the same construction as the first reference circuit 50 . Amplifying comparators A 1 ˜A 32 in the circuit 60 receive the analog input signals INP and INN. The dividing nodes DN 32 and DN 1 are coupled to the input terminal of the amplifying comparator A 32 , DN 31 and DN 2 are coupled to the input terminal of the amplifying comparator A 31 , . . . , and DN 32 and DN 1 are coupled to the input terminal of the amplifying comparator A 1 . Each of the amplifying comparators A 1 ˜A 32 has two pair of inputs and two outputs. The internal construction of each of the amplifying comparators A 1 ˜A 32 will be explained with FIG. 5 .

At the next stage, latching comparators L 1 ˜L 63 in the circuit 90 are arranged. Amplified signals VP 32 and VP 32 B, as outputs from A 32 , are coupled to L 61 , VP 31 and VP 31 B outputs from A 31 are coupled to L 63 , . . . , and VP 1 and VP 1 B outputs from A 1 are coupled to L 1 . The latching comparators L 2 , L 4 , . . . , and L 62 , being interposed between L 1 , L 2 , . . . , and L 63 , receive the amplified signals from their adjacent amplifying comparators. That is, the input of L 62 is coupled to VP 32 and VP 31 B, the input of L 60 is coupled to VP 31 and VP 30 B, . . . , and the input of L 2 is coupled to TP 2 and VP 1 B. The outputs of the latching comparators L 1 ˜L 63 are digital output signals DT 1 /DT 1 B˜DT 63 /DT 63 B, respectively.

FIG. 5 shows a circuit construction the amplifying comparator A 1 including two differential amplifiers, FAn and FAp, a plurality of switches S 1 ˜S 17 , capacitors C 1 ˜C 4 , and sense amplifier SA. Referring to FIG. 5, switch S 1 couples Vref 1 to one electrode of the capacitor C 1 in which the other electrode is connected to one input terminal of amplifier FAn. The switch S 1 is controlled by the signal Q 2 N generated from the switch controller 80 . The switch S 2 couples the analog input signal INP to the capacitor C 1 and is controlled by signal Q 2 . The switch S 3 couples the analog input signal INN to one electrode of the capacitor C 2 , the other electrode of which is connected to the other input terminal of the amplifier FAn, being controlled by the signal Q 2 . The switch S 4 couples the reference voltage Vref 32 to the capacitor C 2 , responding to the signal Q 2 N. The switch 5 S couples the reference voltage Vref 1 to one electrode of the capacitor C 3 , the other electrode of which is connected to one input terminal of the amplifier FAp, being controlled by the signal Q 1 N supplied from the switch controller 80 . The switch S 6 couples the analog input signal INP to the capacitor C 3 , responding to the signal Q 1 generated from the switch controller 80 . The switch S 7 couples the analog input signal INN to one electrode of the capacitor C 4 , the other electrode of which is connected to the other input terminal of the amplifier FAp, responding to the signal Q 1 . The switch S 8 couples the reference voltage Vref 32 to the capacitor C 4 , responding to the signal Q 1 N. The capacitors C 1 ˜C 4 are provided to conduct sampling functions against their corresponding amplifiers, detecting the offset voltages at the input terminals of FAn and FAp.

The amplifiers FAn and FAp are two-input/two-output differential types. Switch S 9 is interposed between the one input terminal and one output terminal of the amplifier FAn, and controlled by the signal Q 2 N. The switch S 10 is interposed between the other input terminal and the other output terminal of the amplifier FAn, and controlled by the signal Q 2 N. The switch S 11 is interposed between the one input terminal and one output terminal of the amplifier FAp, and controlled by the signal Q 1 N. The switch S 12 is interposed between the other input terminal and the other output terminal of the amplifier FAp, and controlled by the signal Q 1 N. The outputs of the amplifier FAn are applied to sense amplifier SA through the switches S 13 and S 14 , respectively. The switches S 13 and S 14 are controlled by the signal Q 2 P supplied from the switch controller 80 . The outputs of the amplifier FAp are applied to the sense amplifier SA through the switches S 15 and S 16 which are controlled by the signal Q 1 P. Between two input terminals of the sense amplifier SA, the switch S 17 is connected in response to the clock signal QL. The amplifiers FAn and FAp, i.e., a two-way alternative amplifier, act as a first amplifying stage with operating in an alternative mode each other, and the sense amplifier SA does a second-stage amplifying operation with receiving the outputs from FAn and FAp continuously and alternatively.

Now, referring to FIG. 6, the operation for converting the analog input signals, INP and INN, into the digital signals DTs will be described hereinafter. Basically, the amplifying comparators A 1 ˜A 32 conduct the auto-zero functions for eliminating the static off-set at the amplifying and latching stages, as well as comparing the analog input signals with the reference voltages and amplifying the compared results.

The switches connect their signal paths when the control signals for themselves are enabled with high levels. The clock signals QL is toggling with a high frequency. The operating periods throughout the timing sequence on FIG. 6 are composed of amplifying period Tamp and auto-zero period Taz, in view of oscillating with Q 1 or Q 2 . Q 1 P and Q 2 P determine data transfer periods Ttrn, and Q 1 n and Q 2 N define periods for eliminating the static offsets, Tos. The signals Q 1 , Q 1 N, and Q 1 P are assigned to control the signal path employing FAp, while the signals Q 2 , Q 2 N, and Q 2 P are assigned to control the signal path including employing FAn.

It should be noted that a pulse width of Tos is shorter than that of Taz. In addition, the amplifying periods by Q 1 and Q 2 , Tamp, are overlapped between each other. The transferring periods by Q 1 P and Q 2 P, Ttrn, are overlapped between each other by ΔOLP, so that the latches in latching comparator 90 can receive the amplified signals from the amplifying comparator 60 throughout an entire operating period. Those arrangements with the pulse widths of the signals are provided to secure a stable conduction of data processing and to overcome a synchronous timing control in a high bandwidth operation.

In the Path through FAp

Before amplifying, during Taz, the reference voltages Vref 1 and Vref 32 are coupled to the nodes N 3 and N 4 (one electrodes of the capacitors C 3 and C 4 ), respectively, through the switches S 5 and SS in response to Q 1 N of high level for Tos. The analog input signals INP and INN can not be applied to the capacitors C 3 and C 4 because Q 1 is low level. Since Q 1 N also makes the path from the input terminals to output terminals of FAp short through S 11 and S 12 , the voltages at the nodes N 7 and N 8 (the other electrodes of C 3 and C 4 ) become Vref 1 -Vosp 1 and Vref 32 -Vosp 2 , respectively. Vosp 1 and Vosp 2 are static DC offset voltages at the inverted and non-inverted input terminal of FAp. It would be understood that the capacitors C 3 and C 4 hold charges to compensate the offset voltages of FAp.

Next, Q 1 N goes to low level and thereby S 5 , S 8 , S 11 , and S 12 are shut off. During Q 1 is on high level for Tamp and Q 1 N (almost a complementary signal of Q 1 ) is on low level, the analog input signals INP and INN are applied to the nodes N 3 and N 4 through the switches S 6 and S 7 . Then, at the input terminals of FAp, INP-Vref 32 -Vosp 1 and INN-Vref 1 -Vosp 2 are charged, and FAp generates amplified output signals having the values of α (INP-Vref 32 -Vosp 1 ) and α (INN-Vref 1 -Vosp 2 ). The parameter a means a gain of the amplifier FAp. Since Q 1 P is high level for Ttrn, the amplified signals from FAp are transferred to nodes N 9 and N 10 through the switches S 15 and S 16 . Then, the sense amplifier SA generates the secondary amplified signals, i.e., the VP 1 and VP 1 B, the final outputs of the amplified comparator A 1 , that are to be applied to the corresponding latch (e.g., L 1 ). The secondary amplified signals from the sense amplifier SA are evaluated with including a gain β of the sense amplifier SA.

In the Path through FAn

Alternatively with the amplifying and auto-zero operations with the path through FAp, the path through FAn carries out the auto-zero and amplifying operations, as shown in FIG. 6, under the control with Q 2 , Q 2 N, and Q 2 P.

Namely, before amplifying, during Taz, the reference voltages Vref 1 and Vref 32 are coupled to the nodes N 1 and N 2 (electrodes of the capacitors C 1 and C 2 ), respectively, through the switches S 1 and S 4 in response to Q 2 N of high level for Tos. The analog input signals INP and INN can not be applied to the capacitors because Q 2 is low level for Toz. Since Q 2 N also makes the path from the input terminals to output terminals of FAn short through S 9 and S 10 , the voltages at the nodes N 5 and N 6 (the other electrodes of C 1 and C 2 ) become Vref 1 -Vosn 1 and Vref 32 -Vosn 2 , respectively. Vosn 1 and Vosn 2 are static DC offset voltages at the inverted and non-inverted input terminal of FAn. It would be understood that the capacitors C 1 and C 2 hold charges to compensate the offset voltages of FAn, as C 3 and C 4 do.

Next, Q 2 N goes to low level and thereby S 1 , S 4 , S 9 , and S 10 are turned off. During Q 2 is on high level for Tamp and Q 2 N (almost a complementary signal of Q 1 ) is on low level, the analog input signals INP and INN are applied to the nodes N 1 and N 2 through the switches S 2 and S 3 . Then, at the input terminals of FAn, INP-Vref 32 -Vosn 1 and INN-Vref 1 -Vosn 2 are charged, and FAn generates amplified output signals having the values of α (INP-Vref 32 -Vosn 1 ) and α (INN-Vref 1 -Vonp 2 ). The parameter α means a gain of the amplifier FAn. Since Q 2 P is high level for Ttm, the amplified signals from FAn are transferred to nodes N 9 and N 1 through the switches S 13 and S 14 . Then, the sense amplifier SA generates the secondary amplified signals, i.e., the VP 1 and VP 1 B, the final outputs of the amplified comparator A 1 , that are to be applied to the corresponding latch (e.g., L 1 ). The secondary amplified signals from the sense amplifier SA are evaluated with including a gain β of the sense amplifier.

Since the amplifiers FAn and FAp generates their output signals alternatively and then the switches S 13 /S 14 and S 15 /S 16 transfer them to the nodes N 9 and N 10 , the input terminals of the sense amplifier SA receive continuous amplified signals. However, as the switch S 17 is turned on and off by means of QL that is oscillating with a high frequency, e.g., 300 MHz, N 9 and N 10 (the input terminals of SA) are charged up to the voltage levels of the current output signals from FAn or FAp only when QL is low level N 9 and N 10 are reset to the level of reference voltage difference, ΔVR (=Vref 1 -Vref 32 ), as shown in FIG. 7A illustrating output levels of the latch (e.g., L 1 ) and the output signals of the amplifier (e.g., FAn or FAp).

In FIG. 7A, it can be seen that, although there is a comparing point where ΔVI (voltage difference between the analogue input signals; INP−INN) is slightly positioned under ΔVR, conditioning a very small difference therebetween, ΔVO 1 (voltage difference between the output terminals of the amplifier, e.g., FAn) can be read as a lower level than ΔVR. That is because the staring level of the amplification is from the reset level of ΔVR forced by QL. Also, in FIG. 7B illustrating the case of the top amplifying comparator (e.g., A 32 ), although there is a comparing point where ΔVI is slightly higher than ΔVR, conditioning a very small difference therebetween, ΔVO 32 (voltage difference between the output terminals of the amplifier like FAn in FIG. 5) can be read as high level.

Such wave forms of the output signals from the amplifier will be more clarified in the latching comparator 90 , after passing through the sense amplifier SA. The output signals from the latching comparator 90 become continuous digital data, and then generated into 6-bit digital data by the digital encoder 100 .

As represented in FIG. 6, the operational sequence with the amplifying, transferring, and performing auto-zero function are proceeded in an asynchronous feature, which is very slower operation in the order of several MHz rather than the high bandwidth clock signal of about 300 MHz. Regarding that the sense amplifier SA generates its amplified signals in sequence from the continuously supplied output signals of the amplifiers (FAn and FAp, alternatively), and the latch comparator 90 generates clarified digital signals in response to QL, the frequency disharmony between the amplifiers and the clock signal may not be a disturbance in accomplishing the technical goal.

As described above, the ADC of the invention can accomplish a faster conversion and a higher resolution by means of two-way alternative amplifying in the amplifying comparator and resetting the amplified signals on the reference voltage level in response to the high bandwidth clock signal.

While the invention has been described in terms of an exemplary embodiment, it is contemplated that it may be practiced as outlined above with modifications within the spirit and scope of the appended claims.