Low power LCD driving scheme employing two or more power supplies

This invention relates in general to liquid crystal displays (LCDs) and, in particular, to a low power driving scheme for LCDs.

FIG. 1 is a schematic view of a LCD panel and its n row electrodes labeled COM 1 , . . . COM n in FIG. 1 , and k column electrodes shown as vertical rectangles labeled SEG 1 ˜SEGk in FIG. 1 . Not shown in FIG. 1 (to simplify the figure) is a layer of liquid crystal material between the row and column electrodes. Each row electrode will overlap a column electrode when viewed in a viewing direction, where the overlapping portion of the two overlapping electrodes will define a pixel of the LCD panel. When an appropriate voltage is applied across a particular row and a particular column electrode, a portion of the liquid crystal layer at the pixel between the overlapping row and column electrodes controls the light transmission or reflective properties of such portion.

FIG. 2 a is a graphical illustration of the Improved Alto-Pleshko (IAPT) waveform for the row (or COM) electrodes and column (or SEG) electrodes. FIG. 2 b is a graphical plot of the conventional Alto-Pleshko driving waveform for row (COM) and column (SEG) electrodes. In FIGS. 2 a and 2 b , voltages labeled V COM or variations thereof indicate voltage waveforms that are applied to the row electrodes and voltages labeled V SEG or variations thereof indicate voltage waveforms applied to column electrodes. The driving waveforms in FIGS. 2 a and 2 b are conventional. Referring to FIG. 1 and FIG. 2 a , a typical configuration of passive LCD and a conventional driving waveform is illustrated. As demonstrated in FIG. 1 , the ith row electrode is connected to a node at voltage V COMi , on one side, and the jth column electrode is connected to a node at voltage V SEGj on the other side. In FIG. 2 a , where vertical axis is voltage, and the horizontal axis time, the data signals V SEGj are also drawn as overlapped shaded region over V COMi signal to illustrate relative relationships between these two sets of signals.

The driving waveform demonstrated in FIG. 2 a , is known as Improved Alto-Pleshko driving method (Improved APT, or IAPT for brief). The main characteristic is that the COM scanning pulses are “folded” such that the driving total voltage dynamic range is reduced as compared to the plain APT, as show in FIG. 2 b . This reduced voltage range is considered to be advantageous in the conventional design technique used in CMOS integrated driver IC, where low MOS transistor break down voltage (caused by thin gate oxide used in fine gate geometry circuits and devices) would otherwise make the circuit design very difficult.

From the waveform of these signals it is observed that although the IAPT driving method reduces the voltage dynamic range for the drivers, but the power is increased as a consequence. This is because the LCD is a pure AC device and the capacitive load on column (SEG) electrodes can be quite significant. However, the current driving the column (SEG) electrodes also need to flow through the entire voltage range, although the column (SEG) electrode voltage swing, V 6 −V 4 , or V 3 −V 1 as shown in FIG. 2 a (these two value needs to be the same), as measured from “majority” COM electrode voltage (which is substantially the same as the non-scanning voltage V 5 in Field 2×N and V 2 in Field 2×N+1) is far smaller than the total supply voltage used in a conventional IAPT driving scheme (V 6 −V 1 in FIG. 2 a .).

According to conventional design principal, the ratio between (V 6 −V 1 ) and (V 3 −V 1 ) can be estimated roughly by

M ⁢ ⁢ u ⁢ ⁢ x + 1 2 ,

where Mux is the multiplexing rate (or duty factor), which is determined by the number of row/COM electrodes. Using this formula, for a moderate sized LCD of 81 rows (with 81 row/COM electrodes), the above ratio is 5×, and therefore, the power wasted for driving SEG electrodes (which is proportional to voltage V, assuming current I stays unchanged) can be as high as 80%.

As there will be only one COM electrode scanning while all SEG electrodes can change at each row scanning period, SEG/column electrode capacitive loading current can be more than ten times higher than COM/row electrode loading current. This obviously makes the low utilization of supplied SEG/column power very undesirable.

One of the most frequently heard complaints from users of portable computers, cellular phones and personal digital assistants is that these devices consume too much power so that one has to constantly change batteries, which is inconvenient. It is, therefore, desirable to provide a power saving scheme for driving LCD displays, especially for displays used in such portable devices.

This invention is based on the recognition that by using two separate power supplies to generate suitable electrical potentials for driving the row and column electrodes, the current driving the column (SEG) electrodes does not need to flow through the total supply voltage (V 6 −V 1 in FIG. 2A ), so that the power consumed by the LCD can be significantly reduced. Preferably, one of the electrical potentials caused to be generated using the two power sources and applied to the row and column electrodes floats with the voltage supplied by one of the power sources. This allows the dynamic range of electrical potentials driving the LCD to be reduced, thereby also allowing the size of semiconductor devices in a power circuit to be reduced. This enables cheaper driver systems to be manufactured for driving LCD displays.

Since the LCD is a pure AC device, signal pulses driving the LCD will be higher than a reference voltage such as ground in some field addressing cycles (e.g. positive going pulses) and lower than the reference voltage (e.g. negative going pulses) in other field addressing cycles. In one embodiment, by providing a voltage differential which is in turn used for generating both types of pulses, this ensures that no significant DC offset would develop across LCD pixels that can cause ionization of the liquid crystal material and damage the LCD permanently. In some embodiments, such voltage differential may be supplied directly by a voltage supply.

Preferably, an energy storage device is used in the low power driving scheme of this invention for generating electrical potentials suitable for driving the row and column electrodes. In a first phase of the operation of the scheme, one or more energy storage devices are charged, and in a second later phase, the energy stored is then used to drive the row and/or column electrodes. In some embodiments, power from the power sources may be used to both charge the energy storage devices as well to the drive row and/or column electrodes during the first phase.

In embodiments where one or more energy storage devices are employed, some of the current employed for driving the column electrodes in a field addressing cycle may be reused in a subsequent cycle for driving column electrodes.

FIG. 1 is a schematic view of a LCD panel and its row electrodes labeled COM 1 , . . . COM n in FIG. 1 , and column electrodes shown as vertical rectangles labeled SEG 1 ˜SEGk in FIG. 1 .

FIG. 2 a is a graphical illustration of the conventional Improved Alto-Pleshko (IAPT) waveform for the row or COM electrodes and column or SEG electrodes.

FIG. 2 b is a graphical plot of the conventional Alto-Pleshko driving waveform for row (COM) and column (SEG) electrodes.

FIG. 3 a is a schematic circuit diagram of a power supply circuit generating suitable electrical potentials for driving the row and column electrodes of a LCD to illustrate one embodiment of the invention.

FIGS. 3 b – 3 d are schematic circuit diagrams of portions of a power supply circuit generating electrical potentials suitable for driving the row and column electrodes of an LCD display to illustrate further embodiments.

FIG. 4 a is a schematic circuit diagram of a power supply circuit for generating electrical potentials for driving a LCD with electrical potentials that float with a voltage supplied by a power supply to illustrate yet another embodiment of the invention.

FIGS. 4 b and 4 c are graphical plots of signal waveforms employed in the embodiment of FIG. 4 a.

FIGS. 5 a and 5 b together illustrate a power supply circuit for generating electrical potentials suitable for driving the row and column electrodes of an LCD to illustrate a preferred embodiment of the invention.

For simplicity in description, identical components are labeled by the same numerals in this application.

Referring to FIGS. 2 a and 2 b , it is observed that in both IAPT ( FIG. 2 a ) and APT ( FIG. 2 b ) driving schemes, during the period of one field, such as field 2×N or field 2×N+1 in FIGS. 2 a , 2 b (N being a positive integer), the SEG/column electrode voltage swings have a very limited dynamic range as compared to the COM/row electrode voltage swings. This invention involves the use of separate power supply systems to provide narrow range, voltage power supply for SEG/column drivers, and wide range voltage power supply for the COM/row drivers.

Floating V COM Embodiments

In an embodiment of the invention for obtaining the signals illustrated in FIG. 2 b , one floating high voltage V COM supply or two fixed high voltage V COM supplies can be used for the COM electrodes (discussed below). Either way, due to the fact that the current used to supply power the column electrodes are driven through a very limited dynamic range, this causes the power consumption of such a modified system to be lower than the conventional one-power supply driving systems by as much as 80% (see calculation in the last paragraph).

Floating V BIAS Embodiments

In one embodiment of the invention for obtaining the signals illustrated in FIG. 2 a , one floating low voltage supply system 12 in FIG. 3 a provides electrical potentials V B+ /V 0 /V B− that are used to supply the power for SEG/column switching. This V BIAS supply 12 , by proper control of switches, will be switching between three states:

Charge: where a power source, such as a charge pump or an buffer amplifier, is used to charge up capacitors connected between V B+ /V 0 /V B− periodically. The capacitors then provide two “operating voltages” for driving the column electrodes.

V-Low: where the V B− is connected to V 1 and V 0 /V B+ will provide V 2 , and V 3 .

V-High: where the V B+ is connected V 6 and V 0 /V B− will provide V 5 , and V 4 .

As will be discussed in detail in the following paragraphs, a floating V COM structure may be simpler than a floating V BIAS structure. In addition, there will be some minor power consumption for switching V BIAS between the three different states. However, a practical implementation of floating V COM structure in a single chip CMOS IC implementation may call for the use of triple well CMOS process, while the floating V BIAS structure can be achieved in the more conventional twin well CMOS process. Therefore the former approach (i.e. floating V COM ) is more suitable for larger LCDs where a multiple-chip solution is required to handle the driving loads, while the latter approach (i.e. floating V BIAS ) is more suitable for smaller LCD where single chip solution is more economical.

Either of these two scheme will achieve very significant power savings compared to conventional single power supply system by utilizing the power more efficiently.

Floating V COM Embodiments

Using Two Fixed V COM Supplies:

One of the embodiments of the invention involves the use of non-folding, APT driving scheme, ( FIG. 2 b ) and utilizes two fixed V COM supplies as illustrated in FIG. 3 a and FIG. 3 b . AS will be understood by those in the art, while the driver circuit for driving only one row or column electrode is shown in the description below in reference to FIGS. 3 a – 3 d , 4 a – 4 c and 5 a , 5 b , similar circuits may be employed for driving other row and column electrodes. While all of the column electrodes need to be driven at the same time, in some embodiments, only one row electrode is scanned at any one time, so that by means of a switching circuit, only one driver may be adequate for driving sequentially all of the row electrodes.

In FIG. 3 a , the COM or row electrode is scanned by application of either V 0 <=>V COM+ pulses or V 0 <=>V COM− pulses, depending on the polarity of the row being scanned. These pulses are supplied to the connection node COM of each row electrode by applying appropriate timing signals S+, S 0 , S− to control the switches I 0 , I 1 , I 2 . The driving potential V B+ or V B− is applied to a connection node SEG for each column electrode by applying suitable timing signals SS+(j), SS−(j) to switches I 3 , I 4 . The notations “SS+(j), SS−(j)” indicate timing signals suitable for the jth column electrode, where j ranges from 1 to the maximum number of column electrodes. The power consumption of the system is very efficient as compared to conventional single power supply IAPT driving system. As the power consumed by the SEG/column electrodes will be supplied by a dedicated V BIAS low voltage power supply, therefore the current loading of the SEG/column electrodes will have a lower V multiplier factor and therefore the system power requirements are reduced.

However, in this embodiment, V COM+ , V COM− are permanently connected to the rest of the driver circuit and therefore require the switch circuit 10 and 12 to tolerate a breakdown voltage of |V COM+ −V COM− |. Since |V COM+ −V 0 |=|V 0 −V COM− |=V COM and can be as high as 15˜18V, the total breakdown requirement can be as much as 30˜36V, which is quite expensive to achieve in fine geometry CMOS process. An improvement in this respect is therefore desirable.

FIG. 3 b is a schematic view of a circuit diagram illustrating a portion of a power supply for generating electrical potentials suitable for driving a LCD. The portion of the power supply shown in FIG. 3 b is for generating a suitable voltage for driving the row electrodes; the portion of the circuit used for generating electrical potentials for driving the column electrodes is similar to that of circuit block 12 of FIG. 3 a . To simplify FIG. 3 b , such circuit block is omitted, it being understood that such circuit block is connected to node V 0 of FIG. 3 b in the same manner as shown in FIG. 3 a . The same is true for FIG. 3 c . In FIG. 3 b , an improved scheme is illustrated. In this scheme, there are still two fixed high voltage supplies, V COM+ and V COM− . However, two pairs of switches (I 1 /I 5 and I 4 /I 3 ) are used to select the power supply for all the row/COM electrode driving circuits. With these switches and the control signal F 1 a , F 2 a (where F 1 a is basically the inverse of F 2 a ), according to APT driving technique, at any single time, only V COM+ , or only V COM− is applied, but never both. As a consequence, the voltage across switches I 0 and I 2 will be limited to |V COM | rather than 2×|V COM |. For example in field 2N, only V 0 and V COM− are applied. The break down requirement is therefore reduced by two as compared to FIG. 3 a embodiment. In addition, all four power supply switches (I 5 , I 6 , I 7 , I 8 ) only went through one |V COM | transition, and therefore is also required to tolerate one V COM for break-down tolerance.

The embodiment of FIG. 3 b still requires two separate power supplies V COM+ and V COM− . A further enhancement to FIG. 3 b is show in FIG. 3 c . In this embodiment, only one voltage supply V COM+ is used. In the positive cycle, signal F 1 a is High and switches I 9 , I 11 are ON. The V+ connection node will connect to V COM+ and V− will connect to V 0 , while capacitor C 0 will be charged to V COM+ . In the negative cycle, F 2 a will be high, switch I 10 will be ON, and the electrical potentials from COM/row scanning system 20 is supplied by capacitor C 0 , which was charged to V COM+ during the positive cycle. With I 10 turned ON, C 0 's top terminal is connected to V 0 , and therefore push C 0 's bottom terminal to −V COM+ , or V COM− . As a result, by connecting different terminals of C 0 to power supply V COM+ and to reference node V 0 , and using the other terminal as V COM+ or V COM− , only one voltage source is required for the scanning of all row/COM electrode. This is possible because at any single moment of time, there will be only one row/COM electrode scanned in the APT driving scheme. This one single voltage source can supply the voltage required for both the polarity of row/COM scanning pulses.

This technique can be applied equally well to field inversion APT driving scheme (where the polarity will stay the same for all rows/COMs within one field, and change to another polarity for all rows/COMs for the next field), for row inversion APT driving scheme (where the polarity for one field will be +−+−+− for one field, and −+−+−+ for the next field, etc.) or other inversion driving scheme. Another important advantage of this single V COM scheme is the natural ability to provide balanced voltage supply to both of the polarity of driving signals. This balance is important as any significant DC offset applied across LCD pixels can cause ionization of LC (liquid crystal) material and damage the LCD permanently. By using only one supply voltage for V COM , this balance is automatically established; otherwise, this may require additional high breakdown voltage feedback control circuits and may be difficult and costly to accomplish.

Yet another improvement to FIG. 3 c , is illustrated in FIG. 3 d . In this embodiment, the connection to V 0 is replaced by connection to V B+ and V B− . In addition V B− is connected to GND while V B+ is connected to one single power Supply V B2 . This improved scheme further reduces the complexity of power supply for V B+ , V B− . In addition, the connection of V COM power supply to V B+ and V B− allows the current used in supplying V COM to flow through the storage capacitor for V B+ (and V B− ) and the capacitor formed by the row and column electrodes COMi, SEGj (shown in dotted lines in FIG. 3 d ) that are addressed at a particular pixel and be reused by the column/SEG electrode drivers for subsequent addressing. A further advantage of moving V COM connection away from V 0 is that V 0 serves the critical role of establishing balance between V B+ and V B− in order to minimize DC voltage as seen across pixel electrodes. If the loading of VCOM is through node V 0 , then all the row/COM scanning current will be loaded on V 0 , which make balancing more difficult to achieve and a strong voltage follower necessary to drive V 0 . When the VCOM is connected to V B+ and V B− , V 0 loading will come completely from column/SEG via LCD pixel capacitance coupling (e.g. COMi, SEGj in FIG. 3 d ), which is, by definition of capacitor coupling, DC free, and a device driving node V 0 can be very weak (just enough to handle C B0 leakage and the unbalanced part of the coupled signals).

Current Reuse

It will be noted that in FIG. 3 b , 3 c or 3 d , the low voltage supply system V BIAS involves the use of capacitor C B+ and C B− . When a SEG electrodes swing from V B+ to V B− , or vise versa, a current is coupled to the node V 0 via the LCD panel capacitance. This current will be a “source” current (flowing out from V 0 node) for V B+ to V B− , transition and “sink” current (flowing into V 0 node) for V B− to V B+ transition. As just discussed above, these currents are intrinsically balanced, and therefore result in no DC in the long term. Now, if a sufficiently large capacitor (for example over 150× the total LCD panel load capacitance) is connected between V 0 and ground, then another very important characteristics will emerge, which is current reuse: the current used by one row of pixels for transitions from, say V B+ to V B− in one field will supply the same row's transition from V B− to V B+ in the next field. Essentially, the currents pulses will be used twice in two consecutive fields, but temporarily stored in the capacitor connected to V 0 . This is especially true for almost all passive LCD display applications where the displayed image is essentially static and field to field image change is very limited. Another way of looking at the current reuse, is to see the voltage being halved at each of the above transition (flowing first from V B+ to V 0 and then from V 0 to V B− , and the V 0 will stay essentially unchanged, assuming the load current produce negligible DC drift on V 0 ). In either perspective, the power consumption is cut in half by the C B+ /C B capacitor connected to V 0 .

Yet another aspect of this invention is related to the two capacitors C B+ /C B− connected between V B+ to V 0 and V 0 to V B− . The importance of C B− in terms of current reuse has been discussed above. The significance of C B+ can be explained as follows. In order for the above current reuse scheme to work, the V 0 node can not be “driven” within two consecutive filed (in other word, V 0 can only be driven fairly infrequently, with an average frequency much lower than the field rate, ideally under 15˜20 Hz, or about 20% of the field rate) and certain small percentage of V 0 drifting (1˜2%, +/− balanced) has to be allowed. This low frequency driving requirement is intrinsically conflicting with the requirement of V 0 being the mid-point between V B+ and V B− , which comes from the requirement of no net DC voltage being applied across pixel electrodes, as this will require V 0 being controlled at all time.

The addition of C B+ , which is of substantially the same capacitance as C B− , will therefore be important for the accomplishment of the current reuse scheme, as a capacitor voltage divider will be formed by C B− and C B+ , and any fluctuation occurring across V B+ to V B− , will automatically be reflected to V 0 via the capacitor voltage divider, and therefore help V 0 maintain its potential at (V B+ −V B− )/2. Without C B+ , the fluctuation of V B+ will be applied to only one side of V 0 and a net DC voltage can easily develop across LCD pixels. Other than using an extremely precise voltage source for V B+ , which will be costly, the other way to overcome this DC problem is to use a fairly strong driver to fixate V 0 at (V B+ −V B− )/2. Since this driver can not differentiate between unwanted drifting and the “good drifting” caused by currents to be reused, it may diminish any power savings, and render the current reuse scheme inoperable.

Floating VBIAS Embodiments

The above embodiments will achieve the desirable power saving by utilizing a separate power supply for SEG/column electrodes with the low voltage VBIAS. However, due to the dual polarity nature of the circuit structure, the CMOS implementation of these schemes in a single chip LCD controller IC still requires the use of triple-well CMOS process (N-Well for P-MOS, when P-MOS operates in positive voltage, and P-Well for N-MOS, when N-MOS operates in the negative voltage). Triple-Well CMOS process can be ˜20% more expensive as compared to a otherwise equal twin-Well CMOS process (equal in terms of break down voltage, minimum geometry, layers of conductors, etc.) It is therefore desirable to modify the scheme to allow the more economical process to be used.

Referring the field-inversion IAPT driving scheme in FIG. 2 a , it is observed that, during each field, the voltage swing of SEG/column is limited to be a relatively small voltage, on both sides of (i.e. above and below) the non-scanning voltage (either V 5 or V 2 , depends on the polarity of scanning COM/row pulses). It is therefore desirable to provide a “floating” VBIAS power supply system for the column/SEG switching needs (referring to FIG. 4 a ) during each field in such a way that, this “floating” power supply will substantially maintain its source voltage (V B+ /V B0 /V B− , or VBIAS for short) stability and supply the current necessary to support the electrode swing between V 6 −V 4 during even fields and V 1 –V 3 during odd fields. With this “floating” VBIAS power supply, then the IAPT folded driving scheme can be used and this allows a complete LCD driving system to be build using a single polarity LCD driving system to be built using twin-well CMOS process.

A preferred embodiment of this “floating” VBIAS supply system 100 comprises a dedicated fixed high voltage VCOM power supply, a VBIAS power supply and a switching circuit for generating certain appropriate electrical potentials for driving the COM or row and SEG or column electrodes. System 100 is shown in FIG. 4 a , where node V 6 is connected to a dedicated fixed high voltage VCOM power supply supplying a voltage V 6 , and nodes V 3 /V 2 /V 1 are connected to a VBIAS power supply to supply the three voltages V 3 /V 2 /V 1 . The voltage level for V 1 is typically GND and V 3 −V 2 =V 2 −V 1 =VBIAS. Control signal F 2 b is the inverse of F 1 b ( FIG. 4 b ), with a tiny gap between the ON portions of these two signals to guarantee that no simultaneous turn ON of both power paths is possible.

In the odd fields, F 2 b is “1”, switches 122 , 124 , 126 are ON, and capacitors C B+ /C B− are connected to V 3 /V 2 /V 1 , and system 100 will supply the voltage source to produce SEG/column driving signals between V 1 V 3 , and COM/row scanning pulses between V 2 V 6 .

In the even fields, F 1 b is “1”, capacitors C B+ /C B− are disconnected from V 3 /V 2 /V 1 , and switch I 23 connects the top terminal C B+ t of C B+ to V 6 , which pulls up the other two terminals V bo , C B− b of capacitors C B+ /C B− , assuming C B+ /C B− capacitance is substantially higher than the loading current on nodes V 5 and V 4 generated by switching activities of SEG/column drivers I 31 /I 32 , then C B+ /C B− will function as a steady voltage source for V 5 and V 4 through switch I 21 and I 25 . With V 6 , V 5 , V 4 , the system 100 driving SEG/column electrodes (only one pair of drivers is shown for one channel) will produce driving signals between V 6 V 4 , while the system 100 will produce V 5 V 1 scanning pulses.

During the even field, since the SEG/column driving power comes entirely from capacitors C B+ /C B− , for the above system to operate properly under all display patterns, the capacitance of C B+ /C B− , needs to be substantially (20ט50×) larger than (the sum of the pixel capacitance)×(maximum possible SEG/column electrode transitions). For a 100×200 pixel LCD panel, assuming each pixel has a cell capacitance of 2 pF, then the above calculation will imply the capacitance of C B+ /C B− needs to be

(20ט50×)×2 pF×100×200×50=40˜100 uF,

where 50=100/2 is the maximum possible SEG/column transition,

happen when the pattern is black/white interleaved lines or checker board.

This capacitance requirement is very high and capacitors with such high capacitance values are generally high leakage, electrolytic type capacitors, and therefore are undesirable for ultra-low power battery operated devices.

An improvement based on the same circuit as the embodiment of FIG. 4 a is to modify the power source management signal F 1 b /F 2 b , and insert “recharge pulses” in F 2 pulses during the even field such that C B+ /C B− will be recharged periodically ( FIG. 4 c ). For example, by inserting such recharge pulses per row scanning period, the calculation for the capacitor required will reduce to: (20ט50×)×2 pF×100×200×50/100=0.4˜2 uF. This range of capacitance can be provided by ceramic capacitor which has negligible leakage current and are in very compact SMD (surface mount device) packages.

Another important factor for this scheme to function is the utilization of the intrinsic capacitances of LCD panels. During the brief periods where the recharging pulses are asserted during the even field, in order for the intrinsic capacitance of the LCD to perform as the holding capacitor for the SEG/column signal until capacitor C B+ /C B− is reconnected to produce V 5 /V 4 . To achieve this, the output of SEG/column driver portion is temporarily turned-off by setting both SS+ and SS− to “0”, and therefore render the SEG/column drivers at a high impedance state to preserve the charge stored in the intrinsic capacitance of the LCD.

With the above structure, all control signals and switches will operate in the positive (or negative) voltage range (relative to GND). This is particularly advantageous where the structure is implemented as an integrated circuit, since the operating voltages can be all positive or negative in reference to the substrate potential. Therefore, other than the capacitors C B+ /C B− , all control signals and switches can be implemented by a conventional twin-Well CMOS process.

Practically all varieties of commercial passive LCD driving systems involve an orthogonal driving waveform which generally comprises a low voltage swing SEG/column driving system, and a high voltage pulses COM/row scanning system. The relative magnitude between SEG/column and COM/row scanning is generally decided by √{square root over (Mux)}, where Mux is the multiplexing rate. For single row scanning system such as APT or IAPT driving schemes, the Mux rate equals the number of rows of the LCD. In MLA (multiple line addressing) driving schemes, Mux=Row/L, where L is the number of rows driven simultaneously at each row scanning period.

Because of significant difference of voltage levels between these two voltage requirements, it is usually undesirable to share one voltage supply between the SEG/column drivers and COM/row drivers. This invention introduces several embodiments for driving passive LCDs using two sets of power supplies to reduce the total power consumption of the LCD display system (including the power consumed by the LCD panel and by the driver). In addition, this invention describes several suitable circuit structures and control signal techniques for CMOS implementation to allow effective IC implementation of the introduced concept/method.

Although the above discussion is limited in its scope, the application of the power system structure system can be expanded to other types of passive LCD driving systems such as pulse-width modulation of SEG/column signals, frame-rate corrected gray-shade modulation and various MLA or active addressing methods. In each of the derived applications, the voltage levels need to be adjusted to optimally conserve the power, and the interaction with driving signals (especially SEG/column) needs to be properly managed to minimize the impact of the image quality.

In the embodiments of FIGS. 3 a – 3 d , a first power supply is used to supply electrical potentials dedicated for driving row or column electrodes, and a second power supply separate from the first is used to generate electrical potentials dedicated and suitable for driving a column or SEG electrodes. In the embodiment of FIGS. 4 a – 4 c , however, it will be noted that the power sources V 6 , V 3 , V 2 and V 1 are used in combination for generating electrical potentials suitable for driving both row and column electrodes. Thus as described above, capacitors C B+ /C B− in combination with the voltage sources V 6 , V 3 , V 2 and V 1 are used to generate electrical potential V 5 for driving the row electrodes as well as electrical potential V 4 for driving the column electrodes.

It will be noted that in the description herein concerning embodiments employing capacitors, a power supply supplying a particular voltage is described as charging the capacitor to the same voltage. In practical circuits, however, it is understood that a capacitor is charged in a practical time frame to a desired voltage which is typically lower than the voltage supplied by the power supply. For example, if the two capacitors C B+ and C B− are to be charged to 1.2 volts across each of the two capacitors, the voltage supply that is used to charge the two capacitors may need to supply a voltage of about 3.0 volts, rather than 2.4 volts in a practical implementation. It will be understood that, in all of the embodiments of the invention described herein involving the charging of capacitors, even though the description of such embodiments may indicate that the capacitors are charged to the same voltage as that supplied by the power supply, it will be understood that in actual practice, the two voltages are only substantially the same, preferably, with the voltage supplied by the power supply slightly higher than that of the desired voltage to which the capacitor is to be charged.

FIGS. 5 a and 5 b together are a schematic circuit diagram of a power supply circuit for driving the LCD to illustrate the preferred embodiment of the invention. As shown in FIGS. 5 a and 5 b , the overall circuit of the power supply system may be naturally divided into two portions: a first portion 200 a for generating electrical potentials suitable for driving row and/or column electrodes and a second portion 200 b for applying the electrical potentials supplied or generated by portion 200 a to the row and column electrodes at the appropriate times. The first portion 200 a is shown in FIG. 5 a . As shown in FIG. 5 a , three voltages are provided by two or more power sources: V 6 , VC and V 1 , where V 1 may simply be ground potential. Two capacitors C 1 and C 2 are employed for storing energy during a first phase of the operation of combined circuit 200 a , 200 b . During the second phase, the energy stored in the capacitors is then used, together with the power sources V 6 , V 1 , for generating electrical potentials suitable for driving row and/or column electrodes.

The voltage VC is chosen so that the voltage difference between VC and V 1 is substantially equal to the amplitude of the voltage difference between non-scanning row electrodes and column electrodes. Thus, during the first phase of operation of the combined circuit 200 a , 200 b , the control signal F 3 c is applied to switches I 34 , I 36 , I 38 and I 40 , turning on these switches, so that capacitors C 1 and C 2 are connected in parallel to the voltage VC and V 1 . Terminals C 1 t and C 2 t of C 1 and C 2 are thus charged to voltage VC and the remaining terminals C 1 b and C 2 b of the two capacitors are at the reference voltage V 1 .

During the second phase of the operation of the combined circuit 200 a , 200 b , control signal F 3 c is pulled low thereby turning off switches I 34 –I 40 . Then the control signal F 1 c or F 2 c is pulled high. Switches I 44 , I 48 are of the type that they will turn on whenever either F 1 c or F 2 c is high. For convenience in description, it is assumed that F 1 c is pulled high first and not F 2 c . Then switches I 42 , I 44 , I 48 , I 50 , I 56 , I 60 , I 64 and I 68 are turned on. This causes terminal C 1 t of capacitor of C 1 to be pulled to voltage V 6 . Since capacitor C 1 has previously been charged during phase 1 to a voltage difference of (VC−V 1 ) between its terminals, then the other terminal C 1 b of capacitor C 1 is thereby also pulled to a value V 5 so that the voltage difference (V 6 −V 5 ) equals (VC−V 1 ). The voltage V 5 , however, will be floating since it is not connected to any one of the three voltage supply nodes V 6 , VC and V 1 . Node VM will therefore be at voltage V 5 through open switch I 44 . Terminal C 2 t of capacitor C 2 is also connected to node VM so that it is pulled to voltage V 5 and its other terminal C 2 b is pulled to a value V 4 so that the voltage difference (V 5 −V 4 ) is equal to the voltage difference (VC−V 1 ). This is the case since the capacitor C 2 has been charged during the previous phase 1 to this voltage difference. Thus, the voltage V 5 passes through switch I 44 and appears at node VM and the voltage V 4 passes through switch I 48 and appears at node 202 .

In reference to FIG. 5 b , the voltage V 5 appearing in node VM passes through switch 156 and appears at node VC+ and reference voltage V 1 passes through switch I 60 to appear at node VC−. Therefore, by controlling switches I 0 and I 2 by means of control signals S+ and S− as before, the voltages V 6 and V 1 are applied to one or more COM or row electrodes. The voltage V 6 also passes through switch I 64 and appears at node VS+ and the voltage V 4 at node 202 passes switch I 68 to appear at node VS−. As before, by applying suitable timing control signals SS+(j) and SS−(j) to control switches I 32 and I 31 , appropriate pulses of V 6 <=>V 4 are applied to the corresponding column electrode SEGj. In reference to FIG. 2 a , the above described driving voltage waveforms are the ones suitable for field 2×N, where the electrical potentials applied to the COM electrodes are between V 5 and V 1 and those applied to the column electrodes are between V 6 and V 4 . As noted above, the voltages V 5 and V 4 are not connected to any power supply during this time and, therefore, float in reference to voltage V 6 through the capacitors C 1 and C 2 .

During the second phase, during another field addressing cycle, such as field 2×N+1 in FIG. 2 a , the control signal F 3 c remains low, control signal F 1 c is pulled low and control signal F 2 c is pulled high. This turns off switches I 42 , I 48 , I 56 , I 60 , I 64 and I 68 , and turns on switches I 46 , I 52 , I 54 , I 58 , I 62 and I 66 . Switches I 44 and I 50 remain on whenever either one of the control signals F 1 c and F 2 c is high. Terminal C 2 b of capacitor C 2 is pulled to V 1 through switch 152 . Since the capacitor C 2 has previously been charged during the first phase to (VC−V 1 ), the terminal C 2 t will be pulled to a voltage V 2 where (V 2 −V 1 ) is equal to (VC−V 1 ), where V 2 floats in relation to V 1 through capacitor C 2 . This voltage V 2 passes switch 150 and appears at node VM. Terminal C 1 b of capacitor C 1 is connected to VM through open switch I 44 so that terminal C 1 b is also at voltage V 2 . Since the capacitor C 1 has previously been charged to a value (VC−V 1 ) during the first phase, the terminal C 1 t of capacitor C 1 will be pulled to a value V 3 , where (V 3 −V 2 ) is equal to (VC−V 1 ), where V 3 , therefore, also floats with V 2 and V 1 through capacitors C 1 and C 2 .

The voltage V 3 passes through switch I 46 and appears at node 204 . In reference to FIG. 5 b , voltage V 2 appearing at node VM passes through switch I 58 and appears at node VC− through switch I 58 and the voltage V 6 passes through switch I 54 to appear at node VC+. Therefore, by means of timing control signals S+ and S−, the voltages V 6 and V 2 are applied through switches I 0 and I 2 to a selected COM electrode. Reference voltage V 1 passes through switch I 66 and appears at node VS− and the voltage V 3 passes switch I 62 to appear at node VS+. As before, by means of timing control signals SS+(j) and SS−(j) controlling switches I 32 and I 31 , respectively, the voltages V 3 and V 1 are applied to the corresponding electrode SEGj, where j ranges from 1 to the maximum number of column electrodes, such as k in FIG. 1 . The operation of the combined circuit 200 a , 200 b of FIGS. 5 a , 5 b during the two phases is summarized in the table below, where the underlined voltages are the ones that are floating:

With the above structure in FIGS. 5 a , 5 b , all control signals and switches will operate in the positive (or negative) voltage range (relative to GND). This is particularly advantageous where the structure is implemented as a single-chip integrated CMOS circuit, since the operating voltages can be all positive or negative in reference to the substrate potential. Therefore, other than the capacitors C 1 and C 2 , all control signals and switches can be implemented by a conventional twin-Well CMOS process.

In the embodiment of FIGS. 5 a , 5 b , the operation of the circuit has two distinct phases: a first phase during which one or more capacitors is charged and during which no electrical potentials are applied to the row or column electrodes. This is followed by phase 2 where one of the two terminals of each capacitor is connected to a voltage supply so that the electrical potential of the remaining terminal of the capacitor is pulled to a value equal to the voltage difference (VC−V 1 ) from that of the voltage supply. One or more of the voltage supplies V 6 and V 1 from the power supplies and one or more of the generated floating voltages at such other terminal of each of the two capacitors are then used to control and drive the row and column electrodes.

In other embodiments described above, such as those in FIGS. 3 c , 3 d and 4 a , there are also two phases where during the first phase, one or more capacitors is charged, and where during the second phase, a floating voltage at a terminal of the capacitor(s) and one or more supply voltages are used for driving row and/or column electrodes. In such embodiments, however, the supply voltage or voltages are also used during the first phase to drive the row and/or the column electrodes. All such variations are within the scope of the invention.

In the embodiment of FIG. 4 a , it may be important to employ capacitors C B+ and C B− that are of substantially equal value and employ voltage supplies V 3 , V 2 , V 1 so that (V 3 −V 2 ) is substantially the same as (V 2 −V 1 ). This is the case to maintain a zero voltage offset at the column electrodes. In the embodiment of FIGS. 5 a , 5 b , this is assured since the capacitors C 1 and C 2 are charged in parallel during the first phase to the same voltage difference. This reduces the tolerances for components that may be used in the drivers so that lower cost components may be used. In the embodiment of FIG. 4 a , the two capacitors are charged when they are placed in series whereas in the embodiment of FIGS. 5 a , 5 b , the two capacitors C 1 and C 2 are charged when they are placed in parallel between the same two voltage sources.

Thus, the feature common to the embodiments in FIGS. 3 c , 3 d , 4 a , 5 a and 5 b is that two or more power supplies together with a circuit including an energy storage device are employed to generate electrical potentials for driving row and column electrodes. The circuit causes at least one of the electrical potentials so generated to float with a voltage supplied by one of the power supplies. Thus, in the embodiment of FIGS. 3 c , 3 d , when the reference voltage V 0 is connected to node V+, thereby putting one terminal of the capacitor C 0 to the reference voltage, the other terminal of capacitor. C 0 is pulled to the floating value—VCOM+ or VCOM−.

In the embodiment of FIG. 4 a , when the capacitors C B+ and C B− are pulled up by voltage supply V 6 , this causes the node between the two capacitors and the remaining terminal of capacitor CB to also be pulled to floating values useful for driving the row or column electrodes. Thus, the voltage value at the node between the two capacitors is pulled to a value V 5 where (V 6 −V 5 ) is substantially equal to (V 3 −V 2 ) which is the voltage difference by which the capacitor C B+ has been charged during the previous phase. At the same time, the voltage at node VS− will also be pulled up to the voltage at the bottom terminal C B−t which is at a voltage V 4 , where (V 5 −V 4 ) is substantially the same as (V 2 −V 1 ). This is the case since capacitor C B− has previously been charged during the previous phase to (V 2 −V 1 ).

Yet another feature common to the embodiments of the invention in FIGS. 3 c , 3 d , 4 a , 5 a and 5 b is that the driver circuit as a whole experiences a voltage dynamic range which does not substantially exceed the amplitude of the voltage pulses applied to the row electrodes. In reference to FIG. 2 b , for example, where two separate voltage sources are employed to generated the positive and negative going voltage pulses for application to row electrodes, the power supply circuit would experience a voltage dynamic range equal to the sum of the amplitudes of the positive and negative going pulses. Since the positive and negative going pulses should have equal amplitudes for zero DC offset, this means that such power circuit would experience twice the amplitude of the voltage pulses applied to the row electrodes. In the example shown in FIG. 2 b , the dynamic range experienced by the power circuit would be equal to V COM+ which is equal to V COM− . In the embodiments of FIGS. 3 c , 3 d , 4 a , 5 a and 5 b , since capacitors have been used to enable a single power supply to generate both the positive and negative going voltage pulses for row electrodes, the voltage dynamic range seen or experienced by the power supply circuit as a whole is substantially equal or not significantly higher than the amplitude of the positive and negative going pulses applied to the row electrodes. In other words, such feature enables the total voltage dynamic range to be reduced as in the case of IAPT, while at the same time vastly reducing the power consumption by the driver when compared to IAPT.

While the invention has been described above by reference to various embodiments, it will be understood that changes and modifications may be made without departing from the scope of the invention, which is to be defined only by the appended claims and their equivalents.