Ferroelectric non-volatile memory cell integrated in a semiconductor substrate

This invention relates to a ferroelectric non-volatile memory cell, and, more specifically, the invention relates to ferroelectric non-volatile memory cells that are used in a serial configuration, and that have a stacked-type structure that includes a MOS device connected in parallel to a ferroelectric capacitor.

Semiconductor integrated ferroelectric electronic non-volatile memory devices comprise a plurality of ferroelectric non-volatile memory cells organized into a matrix, that is, laid into rows or wordlines and columns or bitlines.

Each ferroelectric non-volatile memory cell comprises a MOS transistor and a ferroelectric capacitor.

Conventionally, the processes for fabricating these memory cells includes, once the MOS transistor is integrated into a semiconductor substrate, forming an insulating layer over the entire chip surface.

The ferroelectric capacitor is then formed on top of this insulating layer. This capacitor has conventionally a lower electrode of metal disposed on the insulating layer.

A layer of ferroelectric material covers the lower electrode, and an upper electrode of metal is disposed on the ferroelectric layer.

Ferroelectric cells can be classed basically according to two configurations, namely a strapped or a stacked configuration.

In the former instance, the capacitor is formed outside the active area of the transistor and is connected to the latter by a metal interconnection between a conduction electrode of the transistor and one electrode of the ferroelectric capacitor.

In the latter instance, the ferroelectric capacitor is formed in the active area of the transistor and connected to the latter by a buried contact connecting a conduction electrode of the transistor to the lower electrode of the ferroelectric capacitor.

In this “stacked” configuration, the dimensions of the ferroelectric capacitor are material to a cell area optimization, since this is the configuration that is regarded most appropriate to fill the demands for integration of new CMOS technologies.

However, including special metallizations for the connections between adjacent cells in the same column BL in the matrix increases the size of the memory matrix, and requires process steps otherwise unnecessary.

Embodiments of the invention provide ferroelectric non-volatile memory cells with such constructional and functional features as to allow improved integration to CMOS devices and overcome the drawbacks with which prior memory cells are still beset.

Presented is a device that includes a semiconductor substrate having a ferroelectric non-volatile memory cell which includes a MOS transistor and a ferroelectric capacitor. The ferroelectric capacitor has electrodes connected directly between the conduction terminals of the MOS transistor. The upper electrode of the ferroelectric capacitor is formed above the second conduction terminals of two adjacent MOS transistor and connected electrically thereto, and is arranged to extend over the ferroelectric material to at least partially overlap the lower electrode. Also presented is a non-volatile memory matrix that includes a plurality of the ferroelectric memory cells that are organized into rows and columns, as well as methods for forming both the memory cells and the memory matrix.

The features and advantages of the structure of a memory cell according to the invention will be apparent from the following description of an embodiment thereof depicting memory cells of the ferroelectric type being arranged in a stacked type of structure and used in a serial configuration, and the ensuing description will make reference to this application field for convenience of illustration only.

FIG. 1 is a schematic diagram of a portion of a memory matrix which comprises a plurality of ferroelectric memory cells of the serial type.

FIG. 2 is a top plan view of a portion of a semiconductor substrate accommodating a plurality of serial ferroelectric memory cells in an integrated form, according to an embodiment of the invention.

FIG. 3 is an enlarged top plan view of a portion of a semiconductor substrate wherein a single ferroelectric memory cell of the serial type is provided in an integrated form, according to another embodiment of the invention.

FIG. 4 is a cross-sectional view of FIG. 2, taken along a line II—II.

A ferroelectric memory cell according to this invention will now be described with reference to the drawing views. Directional language such as “above,” “below,” “in front” and “behind” are used in conjunction with one orientation of the described devices, and maintain their relative bearings no matter which particular orientation the described devices sit. Discussion of processes or structures well known to those skilled in the art has been abbreviated or eliminated for brevity.

FIG. 1 shows a schematic diagram for an integrated electronic circuit which incorporates a memory matrix 1 of the serial type comprising a plurality of nonvolatile ferroelectric memory cells 2 and plural addressing and decoding devices for selection 3 .

Each memory cell 2 comprises a MOS transistor 4 having a ferroelectric capacitor 5 parallel-connected thereto. More particularly, the ends of the ferroelectric capacitor are respectively connected to the conduction terminals of the transistor 4 .

The memory matrix 1 comprises memory cells 2 that are organized into rows (wordlines) WL and columns (bitlines) BL, as well as selection devices 3 .

The plurality of memory cells 2 are identified at the intersections of the bitlines and the wordlines.

FIGS. 2 and 3 show, schematically to an enlarged scale and as viewed from above, an embodiment of a portion of a serial memory matrix 1 comprising a plurality of ferroelectric non-volatile memory cells 2 integrated in a semiconductor substrate 6 , as well as an individual non-volatile memory cell, respectively.

Referring to FIG. 4, which shows a cross-section along the II—II line of FIG. 2, shown is a series of MOS transistors 4 formed in the semiconductor substrate 6 . As those skilled in the art will recognize, each MOS transistor 4 has first and second conduction terminals 7 , formed in respective source and drain regions of the substrate 6 for the transistor 4 .

A gate (or control) polysilicon electrode 9 overlies the substrate region extending between the conduction terminal pair 7 , and is isolated from the surface of the substrate 6 by a thin oxide layer.

In this serial configuration, adjacent transistors 4 in the same column BL have a conduction terminal in common.

An insulating layer 10 , e.g., of doped oxide with boron and phosphorus (BPSG), is then formed over the entire semiconductor surface.

Openings are made through the insulating layer 10 at the locations of the conduction terminals to conventionally provide respective contacts 8 .

Advantageously in this embodiment, ferroelectric capacitors 5 are provided at each MOS transistor 4 . Each ferroelectric capacitor 5 has a lower electrode 11 of a metal such as platinum disposed on the insulating layer 10 at the locations of the first conduction terminals 7 . Advantageously, the lower electrode 11 overlaps the control electrode 9 at least in part.

A layer 12 of ferroelectric material covers the lower electrode 11 . Advantageously, the layer 12 of ferroelectric material should cover the entire surface of the semiconductor.

In this case, openings are then defined through the ferroelectric material layer 12 above the second conduction terminals.

Thereafter, an upper electrode 13 of a metal such as platinum is disposed on said layer 12 of ferroelectric material.

The upper electrode 13 is patterned to partially overlap two lower electrodes 11 of adjacent cells 5 and contact the second conduction terminals 8 .

Thus, a plurality of ferroelectric memory cells 2 are formed, each comprising a MOS transistor 4 with a ferroelectric capacitor 5 connected in parallel.

Subsequently to the above, the memory matrix 1 is completed conventionally with the deposition of an insulating layer 14 .

In conclusion, the ferroelectric memory cell structure of this invention obviates the need to have metallizations formed in the matrix, the connections between adjacent cells in the same column BL being provided by local interconnections using the electrodes of the ferroelectric capacitor.

This structure offers improved integration of the ferroelectric capacitors to the CMOS devices by that substantially a single contact element 8 is provided for each of the cells 2 .

Changes can be made to the invention in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims, but should be construed to include all methods and devices that are in accordance with the claims. Accordingly, the invention is not limited by the disclosure, but instead its scope is to be determined by the following claims.