Passive ceramic component

The invention relates to a pasive ceramic component with a carrier substrate, at least one first electrode, at least a first barrier layer, at least one dielectric, and at least one second electrode.

Thin film capacitors usually comprise a carrier substrate, a dielectric, and two electrodes. Silicon provided with a passivating layer, a ceramic material, a glass-ceramic material, or a glass material may be used for the carrier substrate. The electrodes of a thin film capacitor may be made from a noble metal or a non-noble metal. Only well-insulating materials such as, for example, ceramic materials or insulating layers provided by a thin film technique are suitable for the dielectric.

The components are subjected to temperatures of 200 to 600° C. in the manufacture of thin film capacitors. These high temperatures are necessary for ensuring a sufficient adhesion of the individual layers of the thin film capacitors to one another, and in particular of the lower layer to the carrier substrate or the passivating layer, if present. These temperatures are necessary furthermore for improving the electrical quality of the dielectric.

Different coefficients of thermal expansion of the individual layers may cause cracks in the dielectric at these high temperatures. Metal atoms of the electrodes may diffuse into these hollow cracks and in an extreme case cause a short-circuit between the two electrodes of the thin film capacitor. Without the formation of cracks, however, it is also possible for metal atoms of the electrodes to diffuse into the dielectric and cause short-circuits there, given the elevated manufacturing temperatures.

To counteract this problem, a so-called barrier layer may be provided between the dielectric and an electrode. A thin film capacitor is known from U.S. Pat. No. 3,596,370, wherein a barrier layer of aluminum oxide or aluminum chromate is applied between the lower electrode and the dielectric.

A disadvantage of the described thin film capacitor is that on the one hand aluminum chromate is toxic and on the other hand aluminum oxide is a material with a considerable surface roughness, which may enter into undesirable reactions with the dielectric. In addition, aluminum oxide is itself a dielectric with an ∈ r value, so that a stack of dielectrics is present in this thin film capacitor which can influence the characteristics of the thin film capacitor.

The invention has for its object to provide an improved thin film capacitor.

This object is achieved by means of a passive ceramic component with a carrier substrate, at least one first electrode, at least a first barrier layer, at least one dielectric, and at least one second electrode, in that the barrier layer comprises:

Ti x W y (0≦x≦1, 0≦y≦1),

Cr,

Cr x O y (0≦x≦1, 0≦y≦1),

Nb,

Ta,

Ti,

W,

Ni x Mo y (0≦x≦1, 0≦y≦1),

Ir x Ta y (0≦x≦1, 0≦y≦1),

Ir x Zr y (0≦x≦1, 0≦y≦1),

Fe x W y (0≦x≦1, 0≦y≦1),

Ni x Nb y (0≦x≦1, 0≦y≦1),

W x Si y (0≦x≦1, 0≦y≦1),

Pt x Si y (0≦x≦1, 0≦y≦1),

Ta x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Ti x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Mo x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Co x Si y (0≦x≦1, 0≦y≦1),

Cr x Si y (0≦x≦1, 0≦y≦1),

Cr x Si y N z (0≦x≦1, 0≦y≦1),

Cr x Si y O z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Ti x N y (0≦x≦1, 0≦y≦1),

W x N y (0≦x≦1, 0≦y≦1),

Ti x W y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Hf x N y (0≦x≦1, 0≦y≦1),

Ta x N y (0≦x≦1, 0≦y≦1),

Ru x O y (0≦x≦1, 0≦y≦1),

Mo x O y (0≦x≦1, 0≦y≦1),

Ir x O y (0≦x≦1, 0≦y≦1) or

Ni x Cr y Al z (0≦x≦1, 0≦y≦1, 0≦z≦1), or combinations of these materials.

This thin film capacitor has the advantage that the barrier layer comprises a material without interfering dielectric properties.

In a preferred embodiment, a further barrier layer is present between the dielectric and the second electrode, which further barrier layer comprises:

Ti x W y (0≦x≦1, 0≦y≦1),

Cr,

Cr x O y (0≦x≦1, 0≦y≦1),

Nb,

Ta,

Ti,

W,

Ni x Nb y (0≦x≦1, 0≦y≦1),

Ni x Mo y (0≦x≦1, 0≦y≦1),

Ir x Ta y (0≦x≦1, 0≦y≦1),

Ir x Zr y (0≦x≦1, 0≦y≦1),

Fe x W y (0≦x≦1, 0≦y≦1),

W x Si y (0≦x≦1, 0≦y≦1),

Pt x Si y (0≦x≦1, 0≦y≦1),

Ta x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Ti x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Mo x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Co x Si y (0≦x≦1, 0≦y≦1),

Cr x Si y (0≦x≦1, 0≦y≦1),

Cr x Si y N z (0≦x≦1, 0≦y≦1),

Cr x Si y O z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Ti x N y (0≦x≦1, 0≦y≦1),

W x N y (0≦x≦1, 0≦y≦1),

Ti x W y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Hf x N y (0≦x≦1, 0≦y≦1),

Ta x N y (0≦x≦1, 0≦y≦1),

Ru x O y (0≦x≦1, 0≦y≦1),

Mo x O y (0≦x≦1, 0≦y≦1),

Ir x O y (0≦x≦1, 0≦y≦1),

Ni x Cr y Al z (0≦x≦1, 0≦y≦1, 0≦z≦1), or combinations of these materials. This barrier layer prevents undesirable reactions between the dielectric and the second electrode. In addition, the above materials have no dielectric properties which interfere with the characteristics of the thin film capacitor.

It may furthermore be preferred that an adhesion layer of Ti, Cr, Ni x Cr y (0≦x≦1, 0≦y≦1) or Ti x W y (0≦x≦1, 0≦y≦1) is provided between the carrier substrate and the first electrode. This adhesion layer improves the adhesion between the carrier substrate and the first electrode.

It is also advantageous when at least a first and a second current supply contact are provided at mutually opposed sides of the component. Each thin film capacitor can be electrically connected to further components of a circuit by means of said current supply contacts. Depending on the type of application or mounting method, an electroplated SMD end contact, a bump end contact, or a via may be used for this. The use of SMD end contacts or bump end contacts renders possible the manufacture of discrete thin film capacitors, while the use of vias enables a direct integration of the component in ICs.

Preferably, a ceramic material, a glass-ceramic material, a glass material, or silicon is used for the carrier substrate. A carrier substrate of a ceramic or glass-ceramic material or a glass substrate can be inexpensively manufactured, so that the process cost for the relevant components can be kept low. The carrier substrate will be made of silicon if multiple-component units are to be incorporated in ICs.

Preferably, the dielectric comprises Si 3 N 4 ,

Ta 2 O 5 ,

SiO 2 ,

Si x N y O z (0≦x≦1, 0≦y≦1, 0≦z≦1),

SiO 2 /Si 3 N 4 /SiO 2 ,

Ba 1−x Sr x TiO 3 (0≦x≦1)

SrTi 1−x Zr x O 3 (0≦x≦1) with and without Mn as a dopant,

BaO—Ln 2 O 3 —TiO 2 (Ln=La. Ce, Nd, Sm or Eu),

Al 2 O 3 ,

Ba 2 Ti 9 O 20 ,

Ba 2 Ti 9−x Zr x O 20 (0≦x≦1) with and without Mn as a dopant,

BaTi 5 O 11 ,

BaTi 4 O 9 ,

Nb 2 O 5 ,

TiO 2 ,

(Ta 2 O 5 ) x —(Al 2 O 3 ) 1−x (0≦x≦1),

(Ta 2 O 5 ) x —(TiO 2 ) 1−x (0≦x≦1),

(Ta 2 O 5 ) x —(Nb 2 O 5 ) 1−x (0≦x≦1),

(Ta 2 O 5 ) x —(SiO 2 ) 1−x (0≦x≦1),

(Sr,Ca)(Ti,Zr)O 3 ,

BaO—SrO—CaO—Nd 2 O 3 —Gd 2 O 3 —Nb 2 O 3 —TiO 2 ,

CaSm 2 Ti 5 O 14 ,

Zr(Ti,Sn)O 4 ,

BaO—PbO—Nd 2 O 3 —Pr 2 O 3 —Bi 2 O 3 —TiO 2 ,

Ba(Zr,Zn,Ta)O 3 ,

CaTiO 3 —LaAlO 3 ,

(Bi 3 (Ni 2 Nb)O 9 ) 1−x (0≦x≦ 1 ),

(Bi 2 (ZnNb 2(1+d)y O 3+6y+5yd ) x ,

(0≦x≦1, 0.5≦y≦1.5, −0.05≦d≦0.05)

Pb(Zr x Ti 1−x )O 3 (0≦x≦1) with and without excess lead,

Pb 1−αy La y (Zr x Ti 1−x )O 3 (0≦x≦1, 0≦y≦0.2, 1.3≦α≦1.5),

Pb 1−αy La y TiO 3 (0≦y≦0.3, 1.3≦α≦1.5),

(Pb,Ca)TiO 3 ,

BaTiO 3 with and without dopants,

BaZr x Ti 1−x O 3 (0≦x≦1),

Ba 1−y Sr y Zr x Ti 1−x O 3 (0≦x≦1, 0≦y≦1),

Ba(Zn,Ta)O 3 ,

BaZrO 3 ,

PbNb x ((Zr 0.6 Sn 0.4 ) 1−y Ti y )) 1−x O 3 (0≦x≦0.9, 0≦y≦1),

Pb(Mg 1/3 Nb 2/3 )O 3 ] x —[PbTiO 3 ] 1−x (0≦x≦1) or

(Pb,Ba,Sr)(Mg 1/3 Nb 2/3 ) x Ti y (Zn 1/3 Nb 2/3 ) 1−x−y O 3 ,

(0≦x≦1, 0≦y≦1, x+y≦1) or

a) Pb(Mg 1/2 W 1/2 )O 3 ,

b) Pb(Fe 1/2 Nb 1/2 )O 3 ,

c) Pb(Fe 2/3 W 1/3 )O 3 ,

d) Pb(Ni 1/3 Nb 2/3 )O 3 ,

e) Pb(Zn 1/3 Nb 2/3 )O 3 or

f) Pb(Sc 1/2 Ta 1/2 )O 3

as well as combinations of the compounds a) to f) with PbTiO 3 and Pb(Mg 1/3 Nb 2/3 )O 3 with or without excess lead.

It is furthermore preferred that the electrodes comprise Al, Al doped with Cu, Al doped with Si, Al doped with Mg, or Ag, Cu, Ni, Au, W, or combinations of these metals. The layers are structured, for example, by means of lithographical processes in combination with wet and dry etching steps.

It may also be preferred that a protective layer of an organic and/or inorganic polymer is provided on the second electrode. This protective layer protects the subjacent electrodes and the dielectric against, for example, mechanical loads and corrosion.

FIG. 1 diagrammatically depicts the construction of a thin film capacitor according to the invention.

The invention will not be described in greater detail with reference to the figure of the drawing and the embodiments that follow.

In FIG. 1, a thin film capacitor comprises a carrier substrate 1 which is made, for example, from a ceramic material, a glass-ceramic material, a glass material, or silicon. An adhesion layer 2 comprising, for example, Ti, Cr, Ni x Cr y (0≦x≦1, 0≦y≦1) or Ti x W y (0≦x≦1, 0≦y≦1) is present on the carrier substrate 1 , and a first electrode 3 is provided on the adhesion layer 2 . The first electrode 3 comprises, for example, Al, Al doped with Cu, Al doped with Si, Al doped with Mg or Ag, Cu, Ni, Au, W, or combinations of these metals. On this first electrode 3 there is a barrier layer 4 which comprises, for example,

Ti x W y (0≦x≦1, 0≦y≦1),

Cr,

Cr x O y (0≦x≦1, 0≦y≦1),

Nb,

Ta,

Ti,

W,

Ni x Nb y (0≦x≦1, 0≦y≦1),

Ni x Mo y (0≦x≦1, 0≦y≦1),

Ir x Ta y (0≦x≦1, 0≦y≦1),

Ir x Zr y (0≦x≦1, 0≦y≦1),

Fe x W y (0≦x≦1, 0≦y≦1),

W x Si y (0≦x≦1, 0≦y≦1),

Pt x Si y (0≦x≦1, 0≦y≦1),

Ta x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Ti x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Mo x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Co x Si y (0≦x≦1, 0≦y≦1),

Cr x Si y (0≦x≦1, 0≦y≦1),

Cr x Si y N z (0≦x≦1, 0≦y≦1),

Cr x Si y O z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Ti x N y (0≦x≦1, 0≦y≦1),

W x N y (0≦x≦1, 0≦y≦1),

Ti x W y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Hf x N y (0≦x≦1, 0≦y≦1),

Ta x N y (0≦x≦1, 0≦y≦1),

Ru x O y (0≦x≦1, 0≦y≦1),

Mo x O y (0≦x≦1, 0≦y≦1),

Ir x O y (0≦x≦1, 0≦y≦1) or

Ni x Cr y Al z (0≦x≦1, 0≦y≦1, 0≦z≦1) or combinations of these materials.

A dielectric 5 , for example made of Si 3 N 4 ,

Ta 2 O 5 ,

SiO 2 ,

Si x N y O z (0≦x≦1, 0≦y≦1, 0≦z≦1),

SiO 2 /Si 3 N 4 /SiO 2 ,

Ba 1−x Sr x TiO 3 SiO 2

SrTi 1−x Zr x O 3 (0≦x≦1) with and without Mn as a dopant,

BaO—Ln 2 O 3 —TiO 2 (Ln=La. Ce, Nd, Sm or Eu),

Al 2 O 3 ,

Ba 2 Ti 9 O 20 ,

Ba 2 Ti 9−x Zr x O 20 (0≦x≦1) with and without Mn as a dopant,

BaTi5O 11 ,

BaTi 4 O 9 ,

Nb 2 O 5 ,

TiO 2 ,

(Ta 2 O 5 ) x —(Al 2 O 3 ) 1−x (0≦x≦1),

(Ta 2 O 5 ) x —(TiO 2 ) 1−x (0≦x≦1),

(Ta 2 O 5 ) x —(Nb 2 O 5 ) 1−x (0≦x≦1),

(Ta 2 O 5 ) x —(SiO 2 ) 1−x (0≦x≦1),

(Sr,Ca)(Ti,Zr)O 3 ,

BaO—SrO—CaO—Nd 2 O 3 —Gd 2 O 3 —Nb 2 O 3 —TiO 2 ,

CaSm 2 Ti 5 O 14 ,

Zr(Ti,Sn)O 4 ,

BaO—PbO—Nd 2 O 3 —Pr 2 O 3 —Bi 2 O 3 —TiO 2 ,

Ba(Zr,Zn,Ta)O 3 ,

CaTiO 3 —LaAlO 3 ,

(Bi 3 (Ni 2 Nb)O 9 ) 1−x (0≦x≦1),

(Bi 2 (ZnNb 2 ( 1+d)y O 3+6y+5yd ) x (0≦x≦1, 0.5≦y≦1.5, −0.05≦d≦0.05)

Pb(Zr x Ti 1−x )O 3 (0≦x≦1) with and without excess lead,

Pb 1−αy La y (Zr x Ti 1−x )O 3 (0≦x≦1, 0≦y≦0.2, 1.3≦α≦1.5),

Pb 1−αy La y TiO 3 (0≦y≦0.3, 1.3≦α≦1.5),

(Pb,Ca)TiO 3 ,

BaTiO 3 with and without dopants,

BaZr x Ti 1−x O 3 (0≦x≦1),

Ba 1−y Sr y Zr x Ti 1−x O 3 (0≦x≦1, 0≦y≦1),

Ba(Zn,Ta)O 3 ,

BaZrO 3 ,

PbNb x ((Zr 0.6 Sn 0.4 ) 1−y Ti y )) 1−x O 3 (0≦x≦0.9, 0≦y≦1),

Pb(Mg 1/3 Nb 2/3 )O 3 ] x —[PbTiO 3 ] 1−x (0≦x≦1) or

(Pb,Ba,Sr)(Mg 1/3 Nb 2/3 ) x Ti y (Zn 1/3 Nb 2/3 ) 1−x−y O 3 (0≦x≦1, 0≦y≦1, x+y≦1) or

a) Pb(Mg 1/2 W 1/2 )O 3 ,

b) Pb(Fe 1/2 Nb 1/2 )O 3 ,

c) Pb(Fe 2/3 W 1/3 )O 3 ,

d) Pb(Ni 1/3 Nb 2/3 )O 3 ,

e) Pb(Zn 1/3 Nb 2/3 )O 3 ,

f) Pb(Sc 1/2 Ta 1/2 )O 3

as well as combinations of the compounds a) to f) with PbTiO 3 and Pb(Mg 1/3 Nb 2/3 )O 3 with and without excess lead is provided on said barrier layer 4 . On the dielectric 5 there is a further barrier layer 6 which comprises, for example,

Ti x W y (0≦x≦1, 0≦y≦1),

Cr,

Cr x O y (0≦x≦1, 0≦y≦1),

Nb,

Ta,

Ti,

W,

Ni x Nb y (0≦x≦1, 0≦y≦1),

Ni x Mo y (0≦x≦1, 0≦y≦1),

Ir x Ta y (0≦x≦1, 0≦y≦1),

Ir x Zr y (0≦x≦1, 0≦y≦1),

Fe x W y (0≦x≦1, 0≦y≦1),

W x Si y (0≦x≦1, 0≦y≦1),

Pt x Si y (0≦x≦1, 0≦y≦1),

Ta x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Ti x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Mo x Si y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Co x Si y (0≦x≦1, 0≦y≦1),

Cr x Si y (0≦x≦1, 0≦y≦1),

Cr x Si y N z (0≦x≦1, 0≦y≦1),

Cr x Si y O z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Ti x N y (0≦x≦1, 0≦y≦1),

W x N y (0≦x≦1, 0≦y≦1),

Ti x W y N z (0≦x≦1, 0≦y≦1, 0≦z≦1),

Hf x N y (0≦x≦1, 0≦y≦1),

Ta x N y (0≦x≦1, 0≦y≦1),

Ru x O y (0≦x≦1, 0≦y≦1),

Mo x O y (0≦x≦1, 0≦y≦1),

Ir x O y (0≦x≦1, 0≦y≦1) or

Ni x Cr y Al z (0≦x≦1, 0≦y≦1, 0≦z≦1) or combinations of these materials.

A second electrode 7 is provided on the barrier layer 6 . This second electrode 7 comprises, for example, Al, Al doped with Cu, Al doped with Si, Al doped with Mg or Ag, Cu, Ni, Au, W, or combinations of these metals. A protective layer 8 made from an organic and/or inorganic polymer is provided over this second electrode. The organic polymer used may be, for example, polyimide, and the inorganic polymer, for example, Si 3 N 4 .

Alternatively, at least one first and one second current supply contact may be provided on mutually opposed sides of the passive ceramic component. An electroplated SMD end contact of Cr/Ni, Ni/Sn or Cr/Cu, Cu/Ni/Sn or a Pb/Sn alloy, or a bump end contact, or a via may be used as the current supply contact.

Embodiments which represent possibilities for realizing the invention in practice will now be explained in detail.

An adhesion layer 2 of Cr is present on a glass carrier substrate 1 . A first electrode 3 of Cu is deposited on this adhesion layer 2 . A barrier layer 4 of Ti 0.1 W 0.9 is provided on this lower electrode 3 . On this barrier layer are disposed a dielectric 5 of Si 3 N 4 and a further barrier layer 6 of Ti 0.1 W 0.9 . A second Cu electrode 7 and over this second electrode 7 a protective layer 8 of polyimide are provided on the barrier layer 6 .

An adhesion layer 2 of Cr is present on a glass carrier substrate 1 . A first electrode 3 of Ni is deposited on this adhesion layer 2 . A barrier layer 4 of Ti 0.1 W 0.9 is provided on this lower electrode 3 . On this barrier layer are disposed a dielectric 5 of SiO 2 /Si 3 N 4 /SiO 2 and a further barrier layer 6 of Ti 0.1 W 0.9 . A second Ni electrode 7 and over this second electrode 7 a protective layer 8 of polyimide are provided on the barrier layer 6 .