Digital processing of pilot-tone amplitudes

This application claims the benefit of U.S. Provisional Application No. 60/150,081 filed Aug. 20, 1999 for “Digital Detection Method for Pilot-Tone Servo” by Rosser S. Wilson and Michael R. Spauer.

This invention relates to servo positioning the read heads of a video cassette recorder (VCR), and particularly to detecting pilot-tones from adjacent tracks or stripes and digitally processing pilot-tone information for centering the head on the track being followed.

Video cassette recorders record audio and video signals in stripes across the width of the tape, the stripes being arranged in parallel at an incline to the direction of the tape travel. As illustrated in FIG. 1, the stripes are recorded such that every other stripe along the length of the tape contains information modulated to produce a tone at either of two pilot-tone frequencies, f 1 and f 2 . The f 0 stripes are interleaved between the f 1 and f 2 stripes such that each f 0 stripe is bounded by adjacent f 1 and f 2 stripes. Each f 0 stripe contains specific notches at the f 1 and f 2 frequencies. Track following occurs only when the head is attempting to track the f 0 stripes. As shown in FIG. 1, the head senses the pilot-tones of the adjacent f 1 and f 2 stripes. The amplitude of each pilot-tone f 1 or f 2 sensed is largely affected by the position of the head in relation to the f 1 and f 2 stripes. If the head detects an f 1 pilot-tone amplitude greater than an f 2 pilot-tone amplitude, the head is off the center of the f 0 stripe toward the f 1 stripe. Differential averaging techniques are employed to quantify the off-center condition of the head and to operate a servo mechanism based on the f 1 and f 2 pilot-tone amplitudes to move the head relative to the f 0 stripe until the head is centered on the f 0 stripe and the f 1 and f 2 pilot-tone amplitudes are equal.

Prior pilot-tone detection and processing employed analog technology using bandpass filters that pass signal amplitudes centered on the pilot-tone frequencies. The amplitude of each filtered signal was detected and the difference between them was a measure of servo mis-position. The difference signal was ultimately converted to a digital form to operate the servo control microprocessor. However, pilot-tone frequency can vary by as much as ±10% due to variations in tape speed, such as in a “trick” play mode. Therefore, bandpass filters associated with pilot-tone detection necessarily had to be wide enough to accommodate expected frequency variations of the pilot-tones. Wider bandpass filters resulted in a greater likelihood of detection of noise with the pilot tone, resulting in inaccurate amplitude detection of the pilot-tone. Inaccuracies in pilot tone amplitude detection resulted in errors in operating the servo to center the head on the f 0 stripe. Moreover, certain servo algorithms cannot process wide bandwidths, making the wide bandpass filters infeasible in some systems. Narrow bandpass filters could be employed but required switching to define the bandwidths of the actual tones, thereby adding to the complexity of the detection and processing of pilot-tones. The present invention is directed to a digital technique for digitally processing the pilot tone frequencies to inaccuracy of less than about 0.5%, over a range of ±10% of the nominal pilot-tone frequency. As a result, pilot-tone amplitude is more accurately detected, resulting in greater accuracy of the head positioning over the f 0 stripes, and the quantity of expensive analog circuitry can be reduced.

According to the present invention, the amplitudes of at least two signals having mutually exclusive frequencies are digitally determined from an input digital representation of an input signal set containing the two signals. Digital representations are locally derived representing the nominal frequencies of the two signals, from which digital representations of the sine and cosine functions of each locally derived frequency are derived. The derived digital representations of the sine and cosine functions of each frequency are mixed with the input digital representation to determine a product of the input signal with the sine and cosine functions of each of the locally derived frequencies. The resulting four digital representations are processed to derive digital representations of the amplitudes of each of the two signals.

In one form of the invention, the digital representations of the frequencies are derived by establishing a number representative of the respective frequency and repeatedly advancing a count in an accumulator by the number to establish a digital ramp having a slope representative of the frequency. One accumulator is provided for each frequency f 1 and f 2 . The digital representations of the sine and cosine functions of each of the two locally derived frequencies are stored in a look-up table or an array of look-up tables, and the sine or cosine value is based on an instantaneous value of the count in the accumulator. The sine and cosine functions of each frequency are multiplied with the input signal, and the output of each multiplier is processed in a separate digital low-pass filter to extract the baseband component thereof. The outputs of the low-pass filters processing the sine and cosine functions of frequency f 1 are combined in each channel in root-sum-of-squares fashion to yield a signal representative of the amplitude of the f 1 component of the input signal. In similar fashion, the outputs of the low-pass filters processing the sine and cosine functions of frequency f 2 are combined in root-sum-of-squares to yield a signal representative of the amplitude of the f 2 component of the input signal. The signals representative of the amplitudes of f 1 and f 2 are subtracted and the result is provided in digital form to the servo control microprocessor of the VCR that regulates head position.

Another form of the invention employs time-sharing techniques to derive the digital representations of the sine and cosine functions and to perform the mixing, low-pass filtering and root-sum-of-squares combining operations, thereby achieving significant savings in the hardware volume utilized to implement the invention. The amplitudes of at least two signals having mutually exclusive frequencies are digitally determined from an input digital representation of an input signal set containing the two signals. Digital representations are derived representing the frequencies of the two signals at frequencies f 1 and f 2 . As in the first form of the invention, these representations are obtained by incrementing an accumulator at an appropriate rate for each frequency, and two accumulators are therefore provided. A sine/cosine look-up table, mixer, low-pass filter and root-sum-of-squares combinor are employed sequentially and in pipeline fashion to process the four channels of information representing sine and cosine functions of signals for both frequencies f 1 and f 2 . State memory is employed to store the states associated with each channel.

FIG. 1 is a block diagram of a VCR system that also illustrates the layout of stripes along a VCR recording tape.

FIG. 2 illustrates the principles of amplitude detection of pilot-tone frequencies according to the present invention.

FIG. 3 is a block diagram of a circuit for digitally identifying pilot-tone amplitudes according to one embodiment of the present invention.

FIG. 4 is a block diagram of the arithmetic logic units for the circuit of FIG. 3

FIG. 5 is a block diagram of a circuit for digitally identifying pilot-tone amplitudes according to a second, preferred embodiment of the present invention.

FIG. 6 is a diagram illustrating the control of the circuit illustrated in FIG. 5 for pipelining the processing of digital detection of pilot-tone amplitudes.

FIG. 7 is a block diagram of the time-sliced bi-quad filter utilized in the circuit illustrated in FIG. 5 .

FIG. 8 is a diagram illustrating the operation of the arithmetic logic unit (ALU) of the time-sliced bi-quad filter shown in FIG. 7 .

FIG. 1 is a block diagram of a VCR system within which the present invention is implemented. Head 1 is positioned over an f 0 stripe between an f 1 stripe and an f 2 stripe, and preamplifier 2 is connected to head 1 to amplify analog playback data in a manner known in the art. Record channel 3 decoded the analog playback data and delivers the decoded data to controller 4 . The data are coded into 24/25 format as is known in the art, and contain embedded pilot tones and pilot tone notches. Automatic track follower (ATF) 5 also receives playback data provides an indication of the relative amplitude of the f 1 and f 2 tones to servo control microprocessor 6 . Servo control microprocessor 6 utilizes the relative amplitude indications from ATF 5 to control reel motor 8 and head-wheel motor 9 (with signals converted to analog form by digital-to-analog converter and power amplifier 7 ), thereby causing head 1 to be centered on the f 0 ) stripe of the tape.

FIG. 2 illustrates the principles of amplitude detection of pilot-tone frequencies according to the present invention. The input signal I(t) is read by the head (FIG. 1) and is a complex analog signal represented by I  ( t ) =    A     cos  [ ω 1  ( 1 + α )  t ] + B     cos  [ ω 2  ( 1 + α )  t ]    ( 1 ) =    ( A / 2 )  (  j     ω  1  ( 1 + α )  t +  - j     ω  1  ( 1 + α )  t ) + ( B / 2 )  (  j     ω  2  ( 1 + α )  t +  - j     ω  2  ( 1 + α )  t ) ,       ( 2 )

where ω 1 =2πf 1 , ω 2 =2πf 2 , f 1 and f 2 are the pilot tone frequencies, A and B are the amplitudes of the respective pilot tone frequencies f 1 and f 2 , and α is a frequency tolerance of ±10% (i.e., −0.1≦α≦+0.1). For each pilot tone frequency, a carrier is generated in the form of

c ( t )= e −jωt =cos ω t−j sin ω t,   (3)

where ω is ω 1 or ω 2 , as the case may be. The carrier for ω 1 is mixed at 10 with the input signal to yield

I ( t )· e −jω1t =( A /2){ e jω1t +e −jω1(2+α)t }+( B /2)( e j[ω2(1+α)·ω1]t +e −j[ω2(1+α)+ω1]t ),  (4)

for the f 1 pilot-tone frequency. This signal is lowpass filtered at 12 to remove the

(A/2)(e −jω1(2+α)t ) and (B/2)(e j[ω2(1+α)−ω1]t +e −j[ω2(1+α)+ω1]t ) terms leaving

I ( t )· e −ω1t =( A /2)( e jω1t ).  (5)

The square root of the absolute value of the result of equation 5 is derived at 14 resulting in a measure of the magnitude of amplitude A:

It will be appreciated that the carrier for ω 2 is mixed at 12 with the input signal to yield I(t)·e −jω2t for the f 2 pilot-tone frequency, which is processed as indicated in equations (5) and (6) to yield B/2, a measure of the magnitude of amplitude B.

A discrete-time formulation of the above equations is appropriate to the present case, and sets t=nT, where T is the sample interval (16 divided by 41.85 MHz) and n is a sample index. Consequently, the twice-f 2 frequency (2·697.5 KHz=1.395 MHz) will reflect around the half-Nyquist frequency (1.85 MHz divided by 32, which is 1.308 MHz) and alias to 1.308 MHz minus (1.395 MHz minus 1.308 MHz) which is 1.22 MHz, which is effectively removed by the digital lowpass filters in both f 2 quadrature channels. The twice-f 1 component lies within the Nyquist band, and hence is not subject to aliasing.

FIG. 3 is a diagram of a circuit for performing the determination of amplitude of the f 1 and f 2 tones. An analog portion 20 detects and digitizes the input signal I(t). The input signal is input to variable gain amplifier (VGA) 22 whose gain is established by a register (not shown). The analog signal is processed by a bandpass filter 24 and provided to variable gain amplifier 26 having a gain established by another register (not shown). The output signal, in the form of an analog signal, is provided to analog-to-digital converter 28 which is clocked by a sample frequency Fs, which is {fraction (1/16)} (or some other suitable fraction) of the clock frequency (Fc). As will be evident below, the clock frequency is preferably 41.85 MHz in an exemplary embodiment, so the sample frequency is 2.616 MHz for a sample period of about 0.4 microseconds. Filter 24 serves to suppress signals that would unnecessarily interfere with the dynamic range of ADC 28 , and acts as an anti-aliasing filter. The digital output of ADC 28 is provided as input to the digital portion of the circuit, shown in the lower portion of FIG. 3, and particularly to mixers 30 , 32 , 34 and 36 .

Direct digital synthesizers 40 and 42 receive inputs representative of the actual pilot-tone frequencies f 1 and f 2 , such as from the tape servo control microprocessor or from a frequency register of a data read channel that employs digital timing interpolation. The synthesizers are clocked by a clock signal Fc, preferably 41.85 MHz, to provide digital representations of the pilot-tone f 1 and f 2 frequencies, respectively. Each synthesizer includes an accumulator comprised of a register and an adder which periodically adds Δφ f to the register. Each Fc sample cycle provides a sample period of about 24 nanoseconds, during which the count in the register is advanced by an amount (Δφ f ) proportional to the pilot-tone frequency. The incremental count Δφ f added to each accumulator in synthesizers 40 and 42 in each clock period can be represented by 2 N ·f/Fc, where N is the accumulator length in bits, f is the pilot tone frequency and Fc is the clock frequency. Consequently, a nominal frequency of 465 KHz is represented by the decimal value 728 so that the value in the accumulator of synthesizer 40 increases by decimal 728 during each 24 nanosecond clock period. The amount of the increase of the accumulated count during each 0.4 microsecond sample period determines the slope of the ramp for f 1 . When the value of the accumulated count reaches the maximum value (2 16 −1), the accumulated count rolls over to zero and additional accumulation is added to zero, thereby operations as a modulo 2 N accumulator. Hence, synthesizer 40 produces a sawtooth waveform comprising a series of ramps whose average period as the ramp traverses the range of the accumulator is representative of the f 1 pilot-tone frequency. Similarly, the incremental count Δφ f for f 2 at the nominal frequency of 697.5 KHz is represented by the decimal value 1092. Synthesizer 42 produces a sawtooth waveform comprising a series of ramps whose average period as the ramp traverses the range of the accumulator is representative of the frequency of the f 2 pilot-tone. Moreover, the incremental count added to the accumulator each clock period for pilot-tone f 1 will vary by about decimal ±4 for each ±0.5% change in f 1 frequency as the f 1 pilot-tone varies over the tolerance range of ±10% between 418.5 and 511.5 KHz. Similarly, the incremental count added to the accumulator each clock period for pilot-tone f 2 will vary by about decimal ±5 for each ±0.5% change in f 2 frequency as the f 2 pilot-tone varies over the tolerance range of ±10% between 627.75 and 767.25 KHz.

The output of synthesizer 40 is a digital ramp whose period is representative of the f 1 pilot-tone frequency and the output of synthesizer 42 is a digital ramp whose period is representative of the f 2 pilot-tone frequency. In both cases, the ramps can be scaled and viewed as executing excursions between a minimum value of zero and a maximum value of 2π, as is known in the digital synthesizer art. Look-up tables 44 - 50 contain digitized representations of sine and cosine functions that are addressed and retrieved based on the instantaneous values of the digital ramp for the respective f 1 and f 2 pilot-tone frequencies. Because the six least significant bits of the count accumulated in synthesizers 40 and 42 provide little distinguishing value, only the ten most significant bits of the instantaneous values accumulated in the synthesizers are forwarded to look-up tables 44 , 46 , 48 and 50 .

In the first embodiment of the invention, look-up tables 44 , 46 , 48 and 50 are memories containing the sine and cosine values over an input phase range corresponding to zero to 2π, as described above. Using the ramp values from synthesizers 40 and 42 as addresses, tables 44 - 50 retrieve and output digital representations of the sine and cosine values of signals f 1 and f 2 , respectively, for each sampled phase angle φ over the 2π cycle of the sample period. The outputs are 8-bit representations of those functions and are provided to the respective mixer 30 , 32 , 34 and 36 . Hence, the output of look-up table 44 is a digital representation of the sine function for the f 1 pilot-tone frequency identified in equation 3 over the 2π cycle of the sample period, and the output of look-up table 46 is a digital representation of the cosine function for the pilot-tone frequency f 1 over the 2π cycle. Similarly, the outputs of tables 48 and 50 are the digital representations of the sine and cosine functions for the pilot-tone frequency f 2 .

Each table 44 - 50 provides an 8-bit output representative of the sine or cosine function of the f 1 or f 2 pilot-tone. Since the sawtooth ramps supplied to the tables are digitized to ten bits, each table must have a capacity of 2 10 ×8 bits, or 8192 bits. The data stored in look-up tables 44 - 50 can be compressed several ways, well known in the art. One straightforward technique is to simply store values for only one quadrant, 0≦φ≦π/2, in each table, and selectively switch the input and output polarities to map the other three quadrants. This technique reduces the size of each table to 2 8 ×7 bits (1792 bits). Another technique is to store the difference between the input ramp and the sine (or cosine) output function, rather than the sine (or cosine) function alone. This technique saves an additional two bits and reduces each table to 1280 bits, but requires an additional 7-bit adder. Other data compression techniques may be used, such as coarse/fine interpolation, etc.

The 8-bit sine or cosine outputs from look-up tables 44 - 50 are mixed with the input signal from analog-to-digital converter 18 by mixers 30 , 32 , 34 and 36 (which act as multipliers), resulting in digital representations of the signals represented by equation 4. These signals are individually filtered by bi-quadratic filters 52 , 54 , 56 and 58 and provided to identical arithmetic logic units 60 a and 60 b which determine the root sum of the squares for each of the respective f 1 and f 2 signal amplitudes. Filters 52 , 54 , 56 and 58 are lowpass filters which reject the sum component arising from the mixing operation, with two filters in the f 1 channel and two filters in the f 2 channel assigned to the sine and cosine functions of each frequency. The result is a digital representation of the signals represented by equation 5. (The effects of tolerance α are largely removed due to suitable choice by the servo control microprocessor of the input to synthesizers 40 and 42 .) Arithmetic logic unit 60 a mathematically squares the digital values from filters 52 and 54 , sums the values for the f 1 representations, and mathematically determines the square-root of the result, which yields a baseband (DC) component of the signal that is representative of the amplitude of the f 1 signal in the input signal. Similarly, arithmetic logic unit 60 b mathematically squares the digital values from filters 56 and 58 , sums the values for the f 2 representations, and mathematically determines the square-root of the result, which yields a baseband (DC) component of the signal that is representative of the amplitude of the f 2 signal in the input signal.

FIG. 4 illustrates the details of arithmetic logic units 60 a and 60 b . Digital squaring logics 62 , 64 , 66 and 68 square the signals received from respective filters 52 , 54 , 56 and 58 . The outputs of squaring logics 62 and 64 are added by digital summing logic 70 and the outputs of squaring logics 66 and 68 are added by digital summing logic 72 . The square-root of the output of summing logic 70 is derived by square-root logic 74 and the square-root of the output of summing logic 72 is derived by square-root logic 76 . The results of logics 74 and 76 are digital representations of the amplitude of the pilot-tone frequencies f 1 and f 2 , respectively, in the input signal. More precisely, the digital representation outputs from logics 74 and 76 represent one-half the amplitude of the pilot-tone frequencies.

As shown in FIG. 3, the outputs of arithmetic logic units 60 a and 60 b are provided to difference circuit 78 which subtracts the output of square root logic 74 from the output from square root logic 76 , and left shifts the digital result one place to multiply by decimal 2 (binary 10). The output, which is representative of the difference in amplitude between f 1 and f 2 is supplied digitally at output 80 , and through digital-to-analog converter 82 in analog form at output 84 .

Synthesizers 40 a and 40 b , look-up tables 44 , 46 , 48 and 50 , mixers 30 , 32 , 34 and 36 , bi-quad filters 52 , 54 , 56 and 58 and arithmetic logic units 60 a and 60 b jointly implement a digital tuned bandpass filter in each channel, having a passband established by filters 52 , 54 , 56 and 58 and a center frequency established by the frequency delivered to synthesizers 40 and 42 . By implementing this filter digitally as described above, the center frequency and passband are able to be defined with extremely high resolution, which improves the overall performance of the servo control system as it operates to position the head appropriately with respect to the recording medium.

FIG. 5 is a block diagram of the preferred time-sliced implementation of the present invention. The analog portion 20 and synthesizers 40 and 42 are identical to analog portion 20 and synthesizers 40 and 42 shown in FIG. 3 . In this version of the invention, the output from digital-to-analog converter 28 is provided as an input to time-sliced look-up table and mixer 100 which receives the digital representations of ramp functions representing the actual f 1 and f 2 pilot-tone frequencies. Table and mixer 100 provides an output to time-sliced lowpass bi-quad filter 102 , provides an output representative of the filtered sine and cosine functions of f 1 and f 2 to time-sliced vector-summer 104 . The bandwidth of bi-quad filter 102 can in one embodiment be established by a register set by the servo controller. Vector-summer 104 provides digital outputs representative of the f 1 and f 2 amplitudes through buffers 106 and 108 to summer 78 , as previously described. Time-sliced control 110 receives the clock signal Fc and provides the sample signal Fs to analog-to-digital converter 28 as well as control and timing signals to synthesizer 100 , filter 102 , vector summer 104 , and buffers 106 and 108 .

Operation of the circuit illustrated in FIG. 5 may best be explained with reference to the timing diagram of FIG. 6 which illustrates one exemplary version of the control and pipeline timing for the embodiment of FIG. 5 . FIG. 6 illustrates the operation of the circuit during two sample periods, each containing 16 clock cycles. Since the clock signal has a frequency of 41.85 MHz, the sample cycles have a frequency of about 2.616 Mhz, and each sample period is approximately 0.4 microseconds in duration. This sample period is the time interval allotted for each block in FIG. 5 to perform its assigned function.

Time-sliced look-up table and mixer 100 operates in a manner quite similar to look-up tables 44 , 46 , 48 and 50 , and mixers 30 , 32 and 34 of FIG. 3, except that table and mixer 100 operates during separate portions of the sample period to process the sine and cosine functions of the f 1 and f 2 center frequencies. Thus, table and mixer 100 receives and computes the f 1 cosine function and mixes the result with the input signal from analog-to-digital converter 28 during clock cycles 0 - 3 to provide an output to time-sliced biquad filter 102 . Similarly, LUT and mixer 100 processes the f 1 sine function during clock cycles 4 - 7 , the f 2 cosine function during clock cycles 8 - 11 , and the f 2 sine function during the clock cycles 12 - 15 . The look-up table is a single table having a capacity of 2 10 ×8 bits, or 8192 bits. Using data compression techniques as previously described, the look-up table may be reduced to as small as 1792 bits or even smaller.

As illustrated in FIG. 6, the time-sliced biquad filter processes the f 1 cosine function during clock cycles 4 - 7 , processes the f 1 sine function during clock cycles 8 - 11 , processes the f 2 cosine function during clock cycles 12 - 15 , and processes the f 2 sine function during clock cycles 0 - 3 of the next sample period. If an optional gain is used, it is staged into the pipeline at this point, employing four clock cycles. Provision of f 1 or f 2 channel-dependent gain may be advantageous to compensate inherent differences in the amplitude of the f 1 or f 2 tone when the head is centrally positioned over the f 0 track. During clock cycles 12 - 15 , the (f 1 cosine) 2 function is derived and loaded in the vector-summer logic 104 . During clock cycles 0 - 3 of the next sample period, the (f 1 sine) 2 function is derived and added to the (f 2 cosine) 2 function in the vector-summer logic 104 . Similarly, the (f 2 cosine) 2 function is loaded during the clock cycles 4 - 7 of the second sample period and the (f 2 sine) 2 function is added to the (f 2 cosine) 2 function during clock cycles 8 - 11 of the second sample period. Vector-summer 104 calculates the square root of the sum of the (f 1 cosine) 2 and (f 1 sine) 2 functions simultaneously with the loading of the (f 2 cosine) 2 function during the clock cycles 4 - 7 of the second sample period to output a digital representation of the f 1 amplitude at clock period 8 . Similarly, vector-summer 104 calculates the square root of the sum of the (f 2 cosine) 2 and (f 2 sine) 2 functions simultaneously with the loading of the (f 1 cosine) 2 function during the clock cycles 12 - 15 of the second sample period to output a digital representation of the f 2 amplitude at clock period 0 of the third sample period. The square root operation is implemented in one exemplary embodiment as a cellular array as generally described in Computer Arithmetic: Principles, Architecture and Design by K. Hwang, New York: John Wiley, 1979, pp. 360-366. As illustrated in FIG. 5, the f 1 and f 2 functions are loaded into buffers 106 and 108 under the control of time-sliced control 110 and the difference is determined at difference circuit 78 for output at 80 , as previously described.

FIG. 6 is only one example of the control and pipelining of the time-sliced embodiment illustrated in FIG. 5 . More particularly, as previously mentioned, boosting the gain of the various functions subsequent to processing by the bi-quad filters may not be necessary, in which case the loading and adding of the squared functions maybe accomplished immediately following operation of the bi-quad filter, thereby shiffing the outputs to four clock cycles earlier. As a result, the f 1 and f 2 outputs would occur following the third and eleventh clock cycles in the second sample period. Likewise, some vector processing operations permit simultaneous loading and summing of the squared functions so the last two steps illustrated in FIG. 6 can be combined so the f 1 and f 2 outputs may be derived four clock cycles earlier, as early as the beginning of the 0 and 8 clock cycles of the second sample period.

Although the apparatus has been described in FIG. 6 in conjunction with sixteen clock cycles for each sample period, resulting in a sample period of approximately 0.4 microseconds, it may be possible, in some cases, to reduce the number of clock cycles for each step of the process to three, thereby requiring twelve clock cycles for each sample period. Reduction of the number of clock cycles to twelve for a sample period, results in reduction of the sample period to approximately 0.3 microseconds.

FIG. 7 is a block diagram of time-sliced bi-quad filter 102 utilized in the circuit illustrated in FIG. 5 . Time-sliced bi-quad filter 102 includes register 120 comprised of one or more D flip-flops for coupling the output of time-sliced look-up table and mixer 100 to the input of pipelined bi-quad arithmetic logic unit (ALU) 122 . The output of ALU 122 is connected to the input of pipelined gain block 124 . ALU 122 has a REALPOLEVAL input and an IMAGPOLEVAL input receiving real and imaginary coefficients from coefficient/gain register block 126 , and gain block 124 has a GAIN input receiving a programmed gain amount from coefficient/gain register block 126 as well. The real and imaginary coefficients in coefficient/gain register block 126 are predetermined based on the desired filter cutoff frequency. Coefficient/gain registers 126 are controlled by a time-slice control input from the serial port to provide appropriate gain and coefficient values for each of the f 1 and f 2 channels. State RAM 128 is a 4 by 3 word memory that is provided to store the states of ALU 122 as the circuit operates. State storage is required, since each of the four filter channels must remember its state for the previous sample of that channel. The STATE 1 OUT output of ALU 122 is connected to the DA input of RAM 128 , the STATE 2 OUT output of ALU 122 is connected to the DB input of RAM 128 , and the NUMSTATE 2 OUT output of ALU 122 is connected to the DC output of RAM 128 . The QA output of RAM 128 is connected to the STATE 1 IN input of ALU 122 , the QB output of RAM 128 is connected to the STATE 2 IN input of ALU 122 , and the QC output of RAM 128 is connected to the NUMSTATE 2 IN input of ALU 122 . The output of time-sliced bi-quad filter 102 is the output of gain block 124 .

FIG. 8 is a diagram illustrating the operation of ALU 122 of time-sliced bi-quad filter 102 shown in FIG. 7 . The STATE 1 IN input and the REALPOLVAL input to ALU 122 are input to multiplier 132 , and the STATE 1 IN input and the IMAGPOLEVAL input to ALU 122 are also input to multiplier 134 . The STATE 2 IN input and the REALPOLVAL input to ALU 122 are input to multiplier 136 , and the STATE 2 IN input and the IMAGPOLVAL input to ALU 122 are also input to multiplier 138 . The output of multiplier 132 is added to and the output of multiplier 138 is subtracted from the IN input to ALU 122 at summer 130 , yielding the STATE 1 OUT output of ALU 122 . The outputs of multipliers 134 and 136 are added together at summer 140 , yielding the STATE 2 OUT output of ALU 122 . The STATE 2 IN input to ALU 122 is simply passed through as the NUMSTATE 2 OUT output. The STATE 2 IN input is also left-shifted by one bit at block 142 , and the output of block 142 is added to the STATE 2 OUT output and the NUMSTATE 2 IN input to yield the OUT output of ALU 122 . Thus, the configurations shown in FIGS. 7 and 8 are employed to realize time-sliced bi-quad filter 102 as shown in FIG. 5, operating in the manner shown in FIG. 6 . Word widths within the filter are best determined by simulation, taking into account roundoff noise and the desired precision. In general, data path widths within the filter will vary, as is known in the art.

The time-sliced version of the invention described in connection with FIGS. 5-8 time shares among four channels the functions of signal mixers, the bi-quad filters, and the arithmetic unit, by means of pipelining and time-sharing techniques. Accordingly, nearly a four-fold reduction in the hardware volume is achieved relative to the first embodiment of the invention.

The apparatus and process of the present invention provide digital representations of the pilot-tone amplitudes for direct application to the digital servo system. The invention facilitates dynamic changes in pilot-tones, as well as provides a stable and cost-effective implementation of digital processing detection and processing of pilot-tones. It will be clear to those skilled in the art that the invention is operable with any number of pilot tones, and also may be interconnected with either a conventional read channel variable frequency oscillator (VFO) or with the frequency control register of a channel using the known technique of interpolated timing recovery.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.