Voltage regulation employing a composite feedback signal

The present invention relates to switching power supplies, and in particular, to the switch control circuitry in a switching power supply.

Low-voltage, high-speed computer processors present an array of complex power supply design challenges including multiple voltages, high currents, precise regulation, low noise, fast response, tight space, and cost constraints. For example, the core of a 300 MHz Intel Pentium® II processor draws up to 14.2A at a typical voltage of 2.8v, and can generate current transients of up to 13A at 30A/μsec. Future processors are likely to produce even higher rates of current consumption and even more severe load transients. Maintaining desirable regulation under such high current loads and such wide load swings pushes beyond the practical limits of conventional linear regulators. Their efficiency is too low, producing excessive heat, and requiring costly power dissipation hardware. Consequently, the trend for such applications has been to use DC—DC switching regulators, or converters, e.g., synchronous and nonsynchronous buck converters.

A buck converter works by varying the duty cycle of the power MOSFET switch it drives. For example, in a synchronous topology as shown in FIG. 1 ( a ), switch Q 1 turns on at the start of each switching cycle. A voltage equal to the supply voltage less the output voltage appears across the inductor, L. The resulting inductor current climbs and flows through the load as long as the switch Q 1 is closed. The current ramp is approximated by:

where ΔI ON is the current through the inductor, t ON is the switch on time, ΔV is the voltage across the inductor, and L is the inductance. When Q 1 is off, Q 2 , the synchronous rectification transistor, turns on and energy stored in the inductor L generates current through Q 2 and the load. The output voltage appears across the inductor, causing a current ramp approximated by:

During each switching cycle, the inductor's steady-state current ramps between maximum and minimum values, yielding an average current of:

I DC =(I MAX +I MIN )/2

Because ΔI ON =ΔI OFF ,

Thus, the volt-second product is the same during the power switch's on and off times. However, because the average inductor current equals the load current, inductor ripple current can flow through the load to ground during the power switch's off time, degrading efficiency. This is not the case for a nonsynchronous buck converter, as shown in FIG. 1 ( b ), which replaces Q 2 with a diode.

Input voltage and output voltage are related to duty cycle, which is the ratio of the power switch's on time over the total switching period:

Duty Cycle=V OUT /V IN

Duty cycle is a function of the input and output voltages, and is independent of the load. In practice, under heavy loads, voltage across the inductor is reduced by resistive losses in the two MOSFET switches, circuit board traces, and the inductor itself. In addition, input voltage tends to drop with increased load. These loading losses can cause duty cycle to vary by 25% or more.

Compared to linear regulators, buck converters, because of their switching inductance, have an inherently slower output current slew rate. However, a converter's finite transient response time can be enhanced by bulk output capacitance, improving overall response to instantaneous load changes. The minimum theoretical transient response is given by:

where ΔI is the change load current, ΔV is the voltage across the inductor, and L is the inductance. For example, if V IN =5v, V OUT =2.8v, and L=2 μH, and load changes from 0.5A to 13A, the minimum transient response time is 11.4 μs.

However, the duty cycle control loops of conventional buck converters tend to operate at relatively low frequencies, and, therefore, theoretical minimum transient response times are not approached. Typically, the linear loops adjust to load changes over hundreds of microseconds and many switching cycles. To meet the fast response time of modern computer processors, such buck converter circuits require many costly, low equivalent series resistance (ESR) capacitors. A review of the most common control schemes illustrates the problem.

Of the three common control methods for buck converters—voltage mode, current mode, and ripple regulation—voltage mode control, shown in FIG. 2, is widely favored for its simple feedback loop. An error amplifier compares the regulator output voltage to a reference voltage, and generates a control voltage which drives one input of a comparator. The other input to the comparator is connected to a sawtooth wave generator oscillator. The comparator and its inputs serve as a pulse-width modulator (PWM) circuit that controls the MOSFET switch on-time and, therefore, its duty cycle and output voltage.

At the start of each switching cycle, with the MOSFET switched on, the sawtooth voltage ramps upward from its minimum level. When the sawtooth reaches the error amplifier output voltage level, the comparator turns off the MOSFET. This method of control requires that the error amplifier adjust its output voltage in response to line and load changes. Changes in the control voltage pass through the error amplifier and cause corresponding changes in the output voltage. For DC accuracy and stability, voltage mode control requires the control loop to have a relatively high gain and low frequency response, thereby limiting transient response.

Current mode control, shown in FIG. 3, employs dual feedback loops and offers improved line regulation. As with voltage control, this technique uses an error amplifier to generate a PWM control voltage. However, the current through the inductor becomes the source of the PWM sawtooth waveform. Because changes in input voltage immediately affect the slope of the inductor ramp current, duty cycle is inherently adjusted without requiring a change in the error amplifier output. Changes in the load, however, do not affect inductor current or the PWM ramp. Consequently, as with voltage mode control, load regulation requires changes in the error amplifier output voltage. Also, current mode control needs an accurate (and often bulky and costly) current sense resistor to produce a stable PWM ramp voltage, thereby reducing efficiency.

Ripple regulation, shown in FIG. 4, uses output voltage ripple as the PWM sawtooth which is fed to the PWM comparator. The control signal at the other comparator input is a fixed voltage. As a result, ripple regulation requires no error amplifier and achieves a fast response without the need for loop compensation. The MOSFET duty cycle adjusts quickly, pulse by pulse. Changes in line current immediately affect the inductor current and correct the output voltage. Changes in load correct the output directly. The design is simple and its component count low. The main drawback of ripple regulation, however, is that it controls the peak output ripple voltage. Thus, DC accuracy is determined by the mean output ripple voltage, and, as a result, regulation suffers. Related regulation problems include increased output voltage caused by PWM comparator and switch delays, as well as output voltage decreases caused by aging output capacitors.

A fourth method of buck converter control—V 2 ™ control—combines the simple, fast response, and low component count of ripple regulation with the DC accuracy of voltage mode control. The V 2 ™ method, shown in FIG. 5, adds an error amplifier to the ripple regulator topology, resulting in dual feedback loops as in current mode control. The output voltage generates both the ramp signal and the error signal. The V 2 ™ method of control uses a ramp signal generated by the ESR of the output capacitors. This ramp is proportional to the AC current in the inductor and is offset by the DC output voltage. V 2 ™ inherently compensates for variation in both line and load conditions since the ramp signal is generated from the output voltage. This differs from traditional methods such as voltage mode control, where an artificial ramp signal must be generated, and current mode control, where a ramp is generated from inductor current.

The ramp signal also contains the DC portion of the output voltage, allowing the control circuit to drive the output switch from 0% to about 90% duty cycle. Changes in line voltage will change the current ramp in the inductor, affecting the ramp signal and causing the V 2 ™ control loop to adjust the duty cycle. Since a change in inductor current changes the ramp signal, the V 2 ™ method has the characteristics and advantages of current mode control for line transient response. Changes in load current will affect the output voltage and thus will also change the ramp signal. A load step will immediately change the state of the comparator output that controls the output switch. In this case, the comparator response time and the transition speed of the switch limit load transient response time. The reaction time of the V 2 ™ loop to a load transient is not dependent on the crossover frequency of the error signal loop whereas traditional voltage mode and current mode methods are dependent on the compensation of the error signal loop.

The V 2 ™ error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The “slow” error signal loop provides DC accuracy. Low frequency roll-off of the error amplifier bandwidth will significantly improve noise immunity. This also improves remote sensing of the output voltage, since switching noise picked up in long feedback traces can be effectively filtered.

V 2 ™ line regulation and load regulation are improved because there are two separate control loops. A voltage mode controller relies on a change in the error signal to indicate a change in the line and/or load conditions. The error signal change causes the error loop to respond with a correction that is dependent on the gain of the error amplifier. A current-mode controller has a constant error signal during line transients, since the slope of the ramp signal will change in this case. However, regulation of load transients still requires a change in the error signal. V 2 ™ control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both.

One embodiment of the present invention includes a novel gate drive circuit for a switching power supply. The power supply has an output inductor connected at one end to a power switch circuit having a duty cycle, the other end of the output inductor having a regulated output voltage. The gate drive circuit includes an error amplifier that produces an error signal representative of the difference between a reference voltage and a voltage feedback signal representative of the regulated output voltage. A pulse width modulator comparator that compares the error signal to a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of output inductor current, the composite signal having an ac component and a dc component, the comparator output resulting in a gate drive signal that controls the duty cycle of the power switch circuit to maintain the regulated output voltage.

In a further such embodiment, an adaptive voltage positioning circuit adjusts the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when the output inductor current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when the output inductor current is more than the nominal current. The adaptive voltage positioning circuit may use a resistance network, and/or, control output impedance of the power switch circuit based on scaling of the current sensing signal.

An embodiment may further include an overcurrent protection circuit that causes the comparator to turn off the power switch circuit when the current sensing signal exceeds a maximum current reference voltage. The comparator output may determine when the gate drive signal turns off the power switch circuit, in which case, a constant frequency oscillator signal may determine when the gate drive signal turns on the power switch circuit.

Another embodiment of the present invention includes a novel method of generating a gate drive signal for a switching power supply, the power supply having an output inductor connected at one end to a power switch circuit having a duty cycle, the other end of the output inductor having a regulated output voltage, The method includes producing an error signal representative of the difference between a reference voltage and a voltage feedback signal representative of the regulated output voltage; and comparing the error signal to a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of output inductor current, the composite signal having an ac component and a dc component, to produce a signal for generating a gate drive signal that controls the duty cycle of the power switch circuit to maintain the regulated output voltage.

A further such embodiment, may also include adjusting the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when the output inductor current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when the output inductor current is more than the nominal current. Adjusting the voltage feedback signal may include using a resistance network, and/or, use scaling of the current sensing signal to control output impedance of the power switch circuit.

An embodiment may further include providing overcurrent protection by causing the gate drive signal to turn off the power switch circuit when the current sensing signal exceeds a maximum current reference voltage. The signal produced by comparing may determine when the gate drive signal turns off the power switch circuit, in which case, the gate drive signal may turn on the power switch circuit according to a constant frequency oscillator signal.

Another embodiment of the present invention includes a multi-phase gate drive circuit for a switching power supply, the power supply having a plurality of parallel output inductors, each inductor being connected at one end to an associated power switch circuit having a duty cycle, the other end of each inductor being connected to an electrically common point having a regulated output voltage. The gate drive circuit includes an error amplifier circuit that produces an error signal representative of the difference between a reference voltage and a voltage feedback signal representative of the regulated output voltage; and a pulse width modulator comparator for each power switch circuit, each comparator comparing the error signal to a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of current of the associated output inductor, the composite signal having an ac component and a dc component, each comparator producing a signal for generating a gate drive signal that controls the duty cycle of the associated power switch circuit to maintain the regulated output voltage.

Such an embodiment may further include an adaptive voltage positioning circuit that adjusts the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when output current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when output current is more than the nominal current. The adaptive positioning circuit may use a resistance network, and/or, control output impedance of the associated power switch module based on scaling of the associated current sensing signal.

In a further embodiment, each of the plurality of parallel output inductors may be limited to the same peak current based on output impedance of the associated power switch circuit. An overcurrent protection circuit may cause a comparator to turn off its associated power switch circuit when the associated current sensing signal exceeds a maximum current reference voltage. A current limiting circuit may cause each comparator to turn off its associated power switch circuit when a signal representing a sum of the average current of each power switch circuit exceeds an overcurrent reference signal. The signal produced by each comparator may determine when the associated gate drive signal turns off its associated power switch circuit, in which case, a constant frequency oscillator signal may determine when each gate drive signal turns on its associated power switch circuit.

An embodiment of the present invention includes a switching power supply for producing a regulated output voltage. The power supply includes an output inductor connected at one end to a power switch circuit having a duty cycle, the other end of the output inductor having a regulated output voltage. A voltage feedback circuit voltage feedback circuit coupled to the other end of the output inductor produces a voltage feedback signal representative of the regulated output voltage. A current feedback circuit coupled to both ends of the output inductor produces a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of output inductor current, the composite signal having an ac component and a dc component. An error amplifier produces an error signal representative of the difference between a reference voltage and the voltage feedback signal. A pulse width modulator comparator compares the error signal to the composite signal, the comparator output resulting in a gate drive signal that controls the duty cycle of the power switch circuit to maintain the regulated output voltage.

In a further embodiment, the current feedback circuit may include an RC filter, or a voltage divider. The power switch circuit may further include two semiconductor switches connected in series to form a common terminal connected to the output inductor. An adaptive voltage positioning circuit may adjusts the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when the output inductor current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when the output inductor current is more than the nominal current. The adaptive voltage positioning circuit may use a resistance network, and/or, control output impedance of the power switch circuit based on scaling of the current sensing signal.

A further embodiment may include an overcurrent protection circuit that causes the comparator to turn off the power switch circuit when the current sensing signal exceeds a maximum current reference voltage. The comparator output may determine when the gate drive signal turns off the power switch circuit, in which case, a constant frequency oscillator signal may determine when the gate drive signal turns on the power switch circuit.

An embodiment of the present invention includes a multi-phase switching power supply for producing a regulated output voltage. The power supply includes a plurality of output inductors connected in parallel, each inductor being connected at one end to an associated power switch circuit having a duty cycle, the other end of each inductor being connected to an electrically common point having a regulated output voltage. A voltage feedback circuit coupled to the electrically common point that produces a voltage feedback signal representative of the regulated output voltage. A current feedback circuit for each output inductor, coupled to both ends of each respective inductor, that produces a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of current of the associated output inductor, the composite signal having an ac component and a dc component. A pulse width modulator comparator for each power switch circuit compares the error signal to the associated composite signal to produce a signal for generating a gate drive signal that controls the duty cycle of the associated power switch circuit to maintain the regulated output voltage.

In a further embodiment, the current feedback circuit includes, for each output inductor, an RC filter, or a voltage divider. Each power switch circuit may include two semiconductor switches connected in series to form a common terminal connected to the associated output inductor. In addition, an adaptive voltage positioning circuit may adjust the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when output current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when output current is more than the nominal current. The adaptive voltage positioning circuit may uses a resistance network, and/or, control output impedance of a power switch module based on scaling of the associated current sensing signal.

An embodiment may also include an overcurrent protection circuit that causes a comparator to turn off its associated power switch circuit when the associated current sensing signal exceeds a maximum current reference voltage. A current limiting circuit may cause each comparator to turn off its associated power switch circuit when a signal representing a sum of the average current of each power switch circuit exceeds an overcurrent reference signal. The comparator output may determine when the gate drive signal turns off its associated power switch circuit, in which case, a constant frequency oscillator signal may determine when the gate drive signal turns on its associated power switch circuit.

The present invention will be more readily understood by reference to the following detailed description taken with the accompanying drawings, in which:

FIGS. 1 ( a )-( b ) illustrates simple synchronous and non-synchronous buck converters.

FIG. 2 illustrates voltage mode control of a buck converter.

FIG. 3 illustrates current mode control of a buck converter.

FIG. 4 illustrates ripple regulation control of a buck converter.

FIG. 5 illustrates V 2 ™ mode control of a buck converter.

FIG. 6 illustrates the voltage feedback and current feedback configuration in a single phase embodiment.

FIG. 7 illustrates how adaptive positioning works.

FIG. 8 illustrates a preferred embodiment integrated circuit chip which operates as a multi-phase buck CPU controller.

FIG. 9 shows a typical application circuit employing the IC of FIG. 8 for a three-phase buck-configured step-down voltage regulator.

FIG. 10 is an alternate version of the circuit of FIG. 6 in which a resistive sensing arrangement is used to sense output current.

FIG. 11 illustrates a current transient showing various signal waveforms in the circuits of FIG. 6 and FIG. 10 .

A preferred embodiment of the present invention includes a three-phase, fixed frequency, enhanced V 2 ™ architecture buck converter controller with an adaptive voltage positioning circuit for improved transient current response. Each phase is delayed from the previous phase by a programmable time period. In a synchronous buck converter, the high side gate signal normally transitions high at the beginning of each oscillator cycle. Inductor current ramps up until the combination of the current sense signal and the output ripple trip the PWM comparator and bring the high side gate signal low. (Normally, the current sense signal is designed to dominate during steady state operation.) Once the high side gate signal goes low, it remains low until the beginning of the next oscillator cycle. While the high side gate signal is high, the enhanced V 2 ™ loop will respond to line and load transients. Once the high side gate signal is low, the loop will not respond again until the beginning of the next cycle. Thus, the response of any phase to a positive step in load current can be delayed by up to one switching cycle. The response to a negative step in load current is immediate.

FIG. 6 illustrates the voltage feedback and current feedback configuration in a single phase embodiment. In a multi-phase embodiment, the current of each individual phase is sensed, and an additional input is added to the enhanced V 2 ™ loop for each phase. In FIG. 6, L is the buck inductance, and R L is the parasitic resistance of the buck inductor. If the values of R 1 and C 1 are chosen so that L/R L =R 1 *C 1 , then the voltage signal CS will represent the instantaneous value of inductor current. If a more accurate current sense is required, current can be sensed through a resistor instead of across the inductor. The embodiment shown in FIG. 6 represents an enhancement of the original V 2 ™ architecture which used the regulated output voltage for both a fast feedback signal and a slow feedback signal. Like a traditional current sensing regulator, a current feedback loop is used, but unlike traditional current mode sensing, the current feedback signal is a composite signal including an ac component representing inductor current and a dc component representing output voltage. As a result, changes in output current are sensed without delay and the regulator circuit as a whole reacts more quickly. In a multi-phase version of the simplified circuit shown in FIG. 6, as current increases the voltage on the positive pin of the PWM Comparator rises and tends to terminate the PWM cycle earlier, providing negative feedback for each phase. As long as each phase is working from the same COMP and feedback pin there will be current sharing.

For applications with fast transient currents, the output filter is often larger than required to handle output ripple, in order to reduce voltage excursions during load current transients. Adaptive voltage positioning (AVP) can reduce peak-peak output voltage deviations during load transients and allow for a smaller output filter. The output voltage is set higher than nominal at light loads to reduce output voltage sag when the load current is stepped up, and set lower than nominal at heavy loads to reduce overshoot when the load current is stepped down.

FIG. 7 illustrates how adaptive positioning works. The waveform labeled normal shows output voltage for a converter without adaptive positioning. On the left, output voltage sags when the output current is stepped up, and later overshoots when current is stepped back down. With fast (ideal) adaptive positioning, the peak to peak excursions are cut in half. In the slow adaptive positioning waveform, the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded.

For low current applications, a droop resistor can provide fast accurate adaptive positioning. However, at high currents, the loss in a droop resistor becomes excessive. For example, in a 50 A converter a 1 mW resistor to provide a 50 mV change in output voltage between no load and full load would dissipate 2.5 Watts. Lossless adaptive positioning is an alternative to using a droop resistor, but the circuit must respond quickly to changes in load current.

FIG. 8 illustrates an integrated circuit chip which operates as a multi-phase buck CPU controller according to a preferred embodiment. FIG. 9 shows a typical application circuit employing the IC of FIG. 8 for a three-phase buck-configured step-down voltage regulator. As shown in FIG. 9, each output phase uses dual synchronous n-channel MOSFETs Q 1 -Q 6 to drive an output inductor L 1 -L 3 which all share an electrically common output side that supplies current to a load having an output voltage V CORE . The upstream side of each output inductor is sensed at IL 1 , IL 2 , and IL 3 and developed by respective compensation networks R 5 /C 6 , R 6 /C 7 , and R 7 /C 9 . The compensation network reduces, but does not eliminate, the ac and dc components of the signal, and leaves a composite ac and dc signal representing the output current being supplied by the associated output inductor, L 1 -L 3 ; in other words, a current feedback signal. Specifically, one side of each series RC capacitor, C 6 , C 7 , and C 9 , is connected to the output voltage V CORE while the other side of each capacitor which is connected to an associated compensation resistor, R 5 , R 6 , and R 7 , and supplies the composite signal representing the associated output inductor current, thereby creating composite current sensing signals CS 1 -CS 3 inputs to the IC chip U 1 in FIG. 9 .

Within the IC chip itself, as shown in FIG. 8, each current sensing signal CS 1 -CS 3 is applied to the non-inverting input of current sensing instrumentation amplifier 10 CSA 1 - 3 . The CS REF signal to the inverting input of each current sensing instrumentation amplifier (CSA 1 - 3 ) 10 , acts as a current sensing reference signal and is equivalent to the regulated output voltage V CORE (see FIG. 9 ). The output of each current sensing instrumentation amplifier 10 is a current offset signal CO 1 -CO 3 . The current offset signals CO 1 -CO 3 are used in the pulse width modulation (PWM) circuitry, and also are summed together to generate a total average current signal V ITOTAL which is used in the overcurrent limit comparator 11 .

The total average current signal V ITOTAL is also summed with the voltage setting reference DAC OUT and input to the adaptive voltage positioning amplifier (AVPA) 12 . The AVP offset voltage V DRP output from the AVP amp 12 is connected, via a resistor external to the chip, to the V FB signal line to set the amount of AVP desired in a specific application. The offset of V DRP above the DAC voltage is proportional to load current. The voltage feedback signal line V FB input to the chip is integrated with the AVP circuitry. A resistor connected between V FB and V CORE sets the AVP offset for light load currents. The input current of the V FB pin and the resistor value selected determine output voltage offset for zero output current. The V FB signal is used in the PWM circuitry, and also is compared with DAC OUT by the error amplifier (EA) 13 to produce the error amplifier output COMP, which is also used in the PWM circuitry.

The PWM circuit determines the actual timing and maximum duration of the gate drive signals to control the duty cycle of the each pair of the synchronous buck drivers Q 1 -Q 6 in the application circuit, as shown in FIG. 9 . For each phase, a PWM latch 14 generates the gate drive signals for MOSFET switches Q 1 -Q 6 . The non-inverting output of the PWM latch 14 turns on its associated high side driver Q 1 -Q 3 when the set input receives an oscillator output pulse PH 1 - 3 from the phase-sequenced oscillator (OSC) 15 . The inverting output of the PWM latch 14 turns off the associated high side driver Q 1 -Q 3 and turns on the associated low side driver Q 4 -Q 6 when the reset input receives an input pulse from the associated PWM OR-gate 16 . During normal operation, each PWM OR-gate 16 is controlled by its associated PWM comparator 17 . The inverting input of each PWM comparator 17 is the COMP from the error amplifier 13 ; in essence, a relatively “slow” dc feedback signal that maintains high dc accuracy in the enhanced V 2 architecture of a preferred embodiment. The non-inverting input to each PWM comparator 17 is the sum of the respective current sensing signal CO 1 -CO 3 with an +0.5 v offset feedback voltage V FB .; in essence, a relatively “fast” ac current ramp signal representing instantaneous output inductor current.

A preferred embodiment provides two levels of overcurrent protection. Whenever the voltage on a Current Sense pin (CS 1 - 3 ) exceeds CS REF by more than a single phase pulse by pulse current limit, the max current comparator 18 turns off the associated high side driver Q 1 -Q 3 via the PWM OR-gate 16 and the reset input of the PWM latch 14 . This provides fast peak current protection for individual phases. The outputs of all currents are also summed and filtered to form an averaged current signal V ITOTAL which is compared to the voltage on the current limiting threshold pin I LIM by the overcurrent limit comparator 11 . If the I LIM voltage is exceeded, the overcurrent fault latch 19 trips. This turns off the associated high side driver Q 1 -Q 3 via the PWM OR-gate 16 and the reset input of the PWM latch 14 . In addition, the COMP capacitor is discharged by a 5 μA source until the COMP pin reaches 0.2 v. Then, a soft-start begins and the converter will continue to operate in this mode until the fault condition is corrected.

A preferred embodiment uses two methods to provide fast and accurate adaptive voltage positioning (AVP). For low frequency positioning, the V FB and V DRP pins are used to adjust the output voltage with varying load currents. For high frequency positioning, the current sense input pins (CS 1 - 3 ) can be used to control the power stage output impedance. The transition between fast and slow positioning is adjusted by the COMP pin.

For low frequency adaptive positioning, the input bias current of the V FB pin and the V DRP output can be used to provide output voltage adjustment based on the output current of the converter. The output voltage can be set higher than nominal at light output loads by connecting a properly selected resistor between the output and V FB . The output can be set lower during heavy loads by connecting a properly selected resistor between V DRP and V FB . The output of the V DRP pin equals DAC OUT +(Current Sense to V DRP Gain*Σ(CSx−CS REF )). The speed at which this pin responds is related to the time constant formed by the output filter and the converter output impedance and current sense networks. Once the time constants of the output filter and current sense elements have settled, the difference between V DRP output and DAC OUT are proportional to the output current.

F or high frequency adaptive positioning, the response within the first μsec after a transient typically will be determined by the output filter equivalent series resistance (ESR) and equivalent series inductance (ESL). During the next several μsec after a transient, the output impedance of the converter can be controlled using the current sense network and compensation of the error amplifier 13 . Because the current sense signal is added to the voltage signal at the PWM comparator 17 the output impedance of the converter can be adjusted by changing the scaling of the current signal.

FIG. 11 illustrates a current transient showing various signal waveforms in the circuits of FIG. 6 and FIG. 10, with the horizontal axis being time. For simplified analysis, we assume that in FIG. 6, OFFSET is zero. Waveform A, labeled SWNODE, shows the on/off switching of the power switch circuit. Waveform B, labeled Vout, shows the regulated output voltage. Waveform C, labeled (CS−Vout)*CSA Gain, shows the current feedback signal from the current sensing amp, CSA. Waveform D, labeled COMP, represents the output of the error amp, EA, which is the difference between the voltage feedback signal (Vout itself in this case) and a reference voltage, DAC OUT. Waveform E, labeled Vout+(CS−Vout)*CSA Gain, is the summer output—a composite waveform having and ac component, (CS−Vout)*CSA Gain, riding on top of a dc component, Vout (or, in other words, Waveform B +Waveform C).

With respect to simplified FIG. 6 and waveform FIG. 11, each PWM cycle is terminated, as shown by Waveform A, when the summer output Waveform E exceeds the COMP voltage Waveform D. If load current steps up, as occurs at time T 1 , and output voltage sags (as shown in Waveform B), the PWM on-time will continue until the current sensing signal Waveform C increases enough to make up for the loss in voltage, at time T 2 .

If ideal compensation of the current sense network is assumed, the output impedance of a 3 phase power stage with a 1 mΩ inductor resistance (or a 1 mΩ sense resistor) will be:

R POWER STAGE =R L *CSA Gain/# of Phases=1 mΩ*3.7/3=1.2 mΩ.

Initially this impedance appears in parallel with the output filter ESR. If the power stage was run open loop the (with the COMP pin held in one place) the output filter would discharge with a time constant of (R POWER STAGE +ESR FILTER )*C FILTER until the entire output resistance would appear to be R POWER STAGE .

FIG. 10 is an alternate version of the simplified circuit of FIG. 6 in which a resistive current sensing network is used. If the COMP pin is held steady for a given change in output voltage, there will be a corresponding opposite change in the current sensing signal (CSA output). This change in the current signal reflects a change in peak inductor current. Ultimately, the output impedance of the converter (SWNODE) will be: Z OUT = Δ     V OUT Δ     I OUT = Δ     V OUT Δ     I L

And, ΔV OUT =ΔCSA OUT because the current sensing amplifier CSA output changes the same magnitude as V OUT . Thus: Z OUT = Δ     CSA OUT Δ     I L = Δ     I L × R SENSE × CSA GAIN Δ     I L

Again assuming that OFFSET is zero (or at least ignored for simplified analysis), then, I OUT ( per_phase  _peak ) = COMP - V OUT Z OUT

Thus, in a multi-phase system in which each phase shares the same COMP and V OUT (V FB ) pins, and assuming same value R SENSE and CSA gain, all the phases will have the same peak inductor current.

There is a transition between the effects of high frequency and low frequency adaptive positioning. The COMP network component values should be chosen to smooth this transition and can be done empirically. If the COMP network impedance is too low, the RC time constant of the output filter will be visible in the transient response and the output will continue to sag or overshoot until the slow adaptive positioning takes over. If the value is too high the output will drift back to the previous level until the slow adaptive positioning takes over.

Although various exemplary embodiments of the invention have been disclosed, it should be apparent to those skilled in the art that various changes and modifications can be made that will achieve some of the advantages of the invention without departing from the true scope of the invention. These and other obvious modifications are intended to be covered by the appended claims.