USPatent applicationPatented

Solder interconnect techniques

Granted 19 Feb 2002 · 3 office actions

Application· this page
9430965
filed 1 Nov 1999
Publication
Not published
not published
Patent
US 6,347,901
granted 19 Feb 2002

Life of the application

10 dated events
⤢ drag to zoom20002002200420062008201020122014201620182020ProsecutionOwnershipTerm & fees
ProsecutionOwnershipTerm & feeshover for detail · click to open

Abstract

A method and article of fabrication is described featuring a solder layer having a serpentine, interrupted, or interdigitated boundary. The non-planar design of the boundary layer increases the fatigue life of the solder joint by limiting the damage caused by micro-cracking. This irregularity of the solder boundary constrains the propagation of cracks by creating obstacles along the crack path, redirecting the crack away from the intermetallic layer, or by increasing the path along which the crack propagates.

Description

6 parts
›FIELD OF THE INVENTION

The present invention relates to soldering techniques and, more particularly, to a solder method that enhances solder interconnects by eliminating solder joint failures caused by micro-cracking at or near the solder intermetallic interface.

›BACKGROUND OF THE INVENTION

The fatigue life of solder interconnects is often poor, because cracks develop near an intermetallic layer. The damaging process is due to the build-up of inelastic deformation (creep) that leads to cavity nucleation, growth, and coalescence along grain boundaries. The increasing damage tends to produce micro-cracks at the boundaries. These boundary micro-cracks are disposed roughly normal to the direction of maximum tensile stress.

The factors that influence the aforementioned damage include: (a) the shape of the joint, which influences the stress concentration at the free joint boundaries; (b) the build-up of intermetallics, which are known to locally increase stress in solder at and above the intermetallic layer; and (c) the local coefficient of thermal expansion (CTE) mismatch between the pad and the solder.

It is also observed that dissolved copper, gold, or other metallic pad coating materials locally contaminate solder. The contaminants increase the solder brittleness, making the solder susceptible to micro-cracking, when compared with bulk behavior.

The present invention seeks to increase the fatigue life of the solder joint, by limiting the damage caused by micro-cracking in the solder joint. This objective is achieved by redistributing the stresses in solder, thus constraining the cracks. Such containment can be accomplished by creating obstacles along the crack path, redirecting the crack away from the intermetallic layer, or by increasing the path length along which the crack is to propagate. The solder layer can be designed to include a serpentine, interrupted, or interdigitated boundary. The method can be applied to ball grid arrays, column grid arrays, surface mount technology (SMT) joints, etc.

›DISCUSSION OF THE RELATED ART

In U.S. Pat. No. 5,242,569, issued to Kang et al, on Sept. 7, 1993, for THERMOCOMPRESSION BONDING IN INTEGRATED CIRCUIT PACKAGING, a thermocompression bonding method is described that allows bonding to be achieved at lower temperatures. The process produces a soft, deformable layer of metal that is free of dendritic protrusions.

In U.S. Pat. No. 5,172,473, issued to Burns et al, on Dec. 22, 1992, for METHOD OF MAKING CONE ELECTRICAL CONTACT, a method of achieving improved electrical contact is illustrated. Contact is improved by generating cone-shaped projections upon a mating surface. The cones enhance ohmic contact by intermeshing and wiping.

In U.S. Pat. No. 5,118,299, issued to Burns et al, on Jun. 2, 1992, for CONE ELECTRICAL CONTACT, an electrical interconnection is shown featuring two detachable surfaces having intermeshing cone projections. The cones

In U.S. Pat. No. 3,881,799, issued on May 6, 1975, to Elliott et al, for RESILIENT MULTI-MICRO POINT METALLIC JUNCTION, a dynamic interfacing contact device is disclosed. The device provides multiple points of contact between opposing parallel surfaces of a pair of conductors. The points of contact are provided by a number of spaced-apart, metal protrusions.

In U.S. Pat. No. 4,751,563, issued to the common assignee, a microminiaturized electrical interconnection device is described. Electrical connection on a first pad is tangentially raised at about sixty degrees and brought into intimate contact with a second metallic layer.

›SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided a method and article of fabrication, featuring a solder layer that comprises a serpentine, interrupted, or interdigitated boundary. The non-planar design of the boundary layer increases the fatigue life of the solder joint, by limiting the damage caused by micro-cracking. This irregularity of the solder boundary constrains the propagation of cracks by creating obstacles along the crack path, redirecting the crack away from the intermetallic layer, or by increasing the path length along which the crack propagates.

It is an object of this invention to provide a method and article of fabrication that improves the fatigue life of solder joints.

It is another object of the invention to produce a solder joint that constrains cracking along the intermetallic boundary.

›BRIEF DESCRIPTION OF THE DRAWINGS

A complete understanding of the present invention may be obtained by reference to the accompanying drawings, when considered in conjunction with the subsequent detailed description, in which:

FIG. 1 illustrates a side view of the edge of the solder boundary of a prior art metallic pad;

FIG. 2 depicts a plan view of the micro-crack propagation at the solder boundary layer, using the solder configuration of FIG. 1;

FIG. 2 a is a greatly enlarged photograph of actual solder pads with defects represented in FIG. 2;

FIGS. 3 a through 3 g show a plan view of seven embodiments of the pad configuration of this invention; and

FIG. 4 illustrates a plan view of the micro-crack propagation at the solder boundary layer, using the pad configuration of FIG. 3 a.

›DESCRIPTION OF THE PREFERRED EMBODIMENT

Generally speaking, the invention features a method as well as solder pad configurations which increase the fatigue life of the solder joint. The method and pad configurations reduce the damage which is normally caused by micro-cracking at the solder and near intermetallic interface. This irregularity of the pad surface constrains the propagation of cracks by creating obstacles along the crack path, redirecting the crack away from the intermetallic layer, or by increasing the path along which the crack propagates.

Now referring to FIG. 1, a plan view of a prior art metallic pad 10 is illustrated. The straight edge 12 of the solder boundary experiences adjacent micro-cracking 14 in solder near the intermetallic layer, as shown in FIG. 2 . The micro-crack 14 tends to propogate, because there is no constraint against its growth.

Referring to FIGS. 3 a through 3 g , a plan view of a plurality of irregularly shaped strips of solder 16 , 17 , 18 , 19 , 21 , 22 , and 23 respectively, is depicted. FIG. 3 a depicts an undulating or serpentine strip of pad 16 ; FIG. 3 b shows an undulating or serpentine strip of solder 17 having a straight base strip 17 a ; FIG. 3 c illustrates an interdigitated strip of pad 18 ; FIG. 3 d depicts a strip of pad 19 having a curved edged, central digit 19 a ; FIG. 3 e depicts a pad having raised, concentric walls 21 a and 21 b , FIG. 3 f shows a pad 22 having a raised cross-shaped feature 22 a ; and FIG. 3 g illustrates a pad 23 having a plurality of foreshortened substantially cylindrical protrusions 23 a disposed perpendicularly with respect to the major plane of the pad 23 .

Referring to FIG. 4, a solder joint at the intermetallic boundary is shown, using the serpentine solder configuration depicted in FIG. 3 a . It will be observed that the respective micro-cracking 20 at each intermetallic boundary is following a circuitous or meandering path. The lengthening of the crack pathway increases the useful life of the solder joint. Other pad configurations are shown in FIGS. 3 b through 3 d . As before, this results in micro-crack pathways which are interrupted, lengthened, or constrained. In similar manner, these configurations are expected to increase fatigue life of the solder joint, as is that of the solder design shown in FIG. 3 a.

Since other modifications and changes varied to fit particular operating requirements and environments will be apparent to those skilled in the art, the invention is not considered limited to the examples chosen for the purpose of disclosure, and covers all changes and modifications which do not constitute departures from the true spirit and scope of this invention.

Having thus described the invention, what is desired to be protected by Letters Patent is presented in the subsequently appended claims.

Claims as granted

2 claims

Log in to read the claims of this application.

Log in to unlock

Classifications

14 codes
IPC · International Patent Classification
Section B — Performing operations; transporting
  • B23K35/02
  • B23K35/14
  • B23K3/06
Section H — Electricity
  • H05K3/34
  • H01L23/498
  • H01L21/60
  • H05K1/11
  • H01L21/48
  • H01L23/485
USPC · US Patent Classification
403/270228/163403/272228/56.3228/141.1

Claim changes

Soon
Coming soonHow the claims changed between publication and grant

See which claims were amended, added or cancelled during examination, with every added and removed word marked.

AmendedAddedCancelledUnchanged

The published claims of this application are not paired with the granted ones in what we hold.

File wrapper

⤢ drag to zoomOct 1999Jan 2000Apr 2000Jul 2000Oct 2000Jan 2001Apr 2001Jul 2001Oct 2001Jan 2002Apr 2002USPTOApplicantRestriction requirementResponse after non-finalResponse after non-final
USPTOApplicanthover for detail · click to open
Pendency
2.3 y
841 days filing → grant
Office actions
2
after a restriction
Responses
2
no RCE
Examiner
Lynne H. Browne
art unit —
Citations: 16 back · 8 forward

See the full prosecution history — every USPTO and applicant action on this file, in order.

Log in to unlock

Documents

Log in to open the documents of this file: the application as filed, every office action and response, the notice of allowance.

Log in to unlock

Chain of title

⤢ drag to zoom20002002200420062008201020122014201620182020Owner 1
Titlehover for detail · click to open

See the full assignment history — every owner this patent has passed through, with recordation dates and reel/frame numbers.

Log in to unlock