Carrier recovery and doppler frequency estimation

This invention relates to estimation of Doppler shift for, and recovery of a carrier signal for, a received signal.

In a traditional satellite communication system, the satellites are located in a geo-stationary orbit, approximately 35,784 km from the center of the Earth, and move at the same angular velocity as the Earth's surface, approximately 7.292×10 −5 radians per second. The Doppler frequency offset for a signal received from a transmitter located on such a satellite is small, usually much less than the symbol rate for the received signal. This small frequency offset reduces the requirements for carrier signal recovery at the receiver, assumed to be located on or near the Earth's surface. However, because of the great distance between a geo-stationary (GEO) satellite and a ground receiver, the signal round trip time propagation time is relatively long, at least about 0.1 sec, and such a transmission system offers a correspondingly reduced data transmission rate and requires relatively high transmitter power.

An alternative to the GEO system, referred to as a low Earth orbit or LEO system, locates one or more transmitting satellites closer to the Earth's surface, for example, at a distance of about 350 miles above the surface, and the satellites move with a greater angular velocity than does a GEO satellite, the corresponding Doppler frequency offset is higher, the round trip signal propagation time is reduced, the permitted data transmission rate is increased, and the required transmission power is reduced. A LEO satellite is moving faster than the in-view receiver, and the larger Doppler frequency offset is often larger than the symbol rate for the received signal. Estimation of the Doppler frequency offset and recovery of the carrier signal is a challenging task and usually requires a more complex receiver design.

Automatic frequency control (AFC), phase locked loop (PLL) processing, fast Fourier transform (FFT) processing and linear prediction (LP) are possible candidates for processing a Doppler-shifted received signal. AFC and/or PLL are presently used for cellular communications with GEO satellites, where the Doppler shift is at most a few hundred Hz. The maximum Doppler frequency offset that can be corrected using AFC or PLL is about 10 percent of the symbol rate, and the symbol rate is likely to be as low as 10-50 KHz. Further, the frequency acquisition time for AFC and/or PLL will depend strongly on the signal-to-noise ratio (SNR) or bit energy-to-noise ratio (E b /N o ) and is generally much longer than the available time interval (e.g., a time slot length) when the Doppler frequency offset is large. Thus, use of AFC and/or PLL alone will not allow fast or reliable acquisition of a Doppler-shifted signal.

An FFT approach can be used to assist in carrier recovery by estimating a large frequency offset in a fixed time period. However, an FFT approach is complex, requires performance of a set of computations that is approximately proportional to N·log(N), where N is the number of signal samples used for the estimates, and must operate in a block mode for computations so that all samples must be collected before computations begin. This will require complex processing and will not allow estimation of a Doppler frequency offset within a short time interval.

An LP approach can also be used to assist in carrier recovery by estimating a large frequency offset in a fixed time period. LP requires performance of a set of LP computations that is approximately proportional to N and operates in serial mode so that computations can begin before all signal samples are collected. However, the accuracy of an LP approach depends upon the frequency estimation range (larger ranges produce poorer accuracy) and upon the SNR. For medium to low SNR with a frequency estimation range larger than the symbol rate, an LP approach cannot estimate frequency offset to better than to within 5 percent of symbol rate with high probability.

What is needed is a system for Doppler frequency offset estimation and carrier signal recovery that has relatively low complexity and that provides an estimate within a time interval allotted to transmission of a few symbols in a time slot (a time interval enclosing one information unit, including a preamble, a unique word or other identifying indicium, and a payload). Preferably, the system should be able to estimate a Doppler frequency offset of any size, even one that is greater than the symbol transmission rate, should have a relatively short signal interrogation time for such estimation, should be accurate to within one percent for a received signal interrogated within an assigned time slot, should work quickly to provide a Doppler frequency offset estimate before the information unit has been completely received, should work with a bit energy ratio E b /N o as low as 4.5 dB, and should have relatively low complexity.

These needs are met by the invention, which provides a simple, multi-stage Doppler frequency offset estimation system that (1) provides an estimate of Doppler frequency offset within one percent of the correct value, (2) provides this estimate within the present time slot and with relatively simple computations. The system uses first and second stage LP analysis with different parameter sets chosen for each of these stages, followed by a decision feedback PLL third stage that acquires and subsequently tracks the Doppler-shifted received signal. The first two stages provide down-conversion of the estimated Doppler frequency offset to a residual shift that can be captured and tracked by the PLL. The third stage uses decision feedback, second order PLL to acquire and track the residual frequency offset and phase angle. The final Doppler frequency offset is calculated from the results of all three stages, which operate serially and continuously. The system is especially useful for receipt of low orbit satellite signals with small to medium SNR.

FIG. 1 illustrates the environment in which the invention is used.

FIGS. 2, 3 , 4 , 5 and 6 illustrate apparatus suitable for practicing the invention.

FIG. 7 illustrates application of the invention to a time slot.

FIG. 8 graphically illustrates residual error using the invention.

FIG. 9 is a schematic view of a computer system suitable for implementing the invention.

FIG. 1 illustrates ah environment in which the invention can be used. A satellite 11 , moving with an angular velocity of ω sat and an orbit radius of r=r sat ≈{M·G/ω sat 2 } 1/3 , transmits a signal s(t) that is received, after a suitable signal propagation delay, by a receiver 13 moving approximately with the Earth's surface, at a radius r rec from the Earth's center C. Here, M=6.099×10 12 Kgm is the Earth's mass and G=6.66×10 −5 cm 3 −sec −2 −Kgm −1 is the Earth's gravitational constant.

A signal transmitted s(t) transmitted by the satellite 11 is assumed to include a preamble of a selected length Δt(pre) that is pure carrier signal, with no message modulated thereon. This preamble, and the subsequent message modulated onto the carrier signal, is received by the receiver 13 and processed according to the invention to determine the present Doppler frequency offset f D at which the pure carrier signal is being received. The pure carrier signal may be represented as

s ( t; carr)= s 0 ( t )exp(2 πj·f D t )+ n 1 ( t )  (1)

at a particular time t, where n 1 (t) represents noise associated with the received signal at time t. Preferably, but not necessarily, the carrier signal frequency f carr is known at the receiver. In a first stage of an embodiment of the invention, the receiver 13 samples this received signal at a rate of 1/T s per second, computes a correlation signal s(kT s ;carr)·s((k−K)T s ;carr)*, and forms a sum S 1 of a selected number N 1 of these computed correlation signals: S1  ( N1 ; K1 ; carr ) =    ∑ k = 1 N1  s  ( k · T s ; carr ) · s  ( ( K1 - k ) · T s ; carr ) * =    N1 · s 0 · exp     ( 2     π     j · K1 · f D · T s ) + n2 , ( 2 )

where K 1 is a selected integer and n 2 represents cumulative noise associated with the sum S 1 in Eq. (2). The receiver now forms the function

tan −1 {S 1 ( N 1 ; K 1 ;carr}/(2 π·K 1 · T s )= f D1 +n 3 ,  (3)

where n 3 represents noise associated with the function computed in Eq. (3). This noise may be removed by appropriate low pass filtering, if the sampling rate 1/T s is much lower than the rate of change associated with the noise n 3 , thus providing a first estimate, f D1 of the Doppler frequency offset at which the carrier signal is received. This first stage will, in most circumstances, provide an estimation of the Doppler frequency offset f D that is within 10 percent of the symbol rate for the total signal s(t) (carrier plus message).

In a second stage, a first frequency-shifted carrier signal

s 2 ( t; carr)= s ( t; carr)exp(−2 πj·f D1 ·t )+ n 4 ( t )  (4)

is formed, where n 4 (t) represents noise. A second correlation S 2 is computed, given by S2  ( N2 ; K2 ; carr ) =    ∑ k = 1 N2  s2  ( k · T s ; carr ) · s2  ( ( K2 - k ) · T s ; carr ) * =    N2 · s 0 · exp     ( 2     π     j · K1 · f D2 · T s ) + n5 , ( 5 )

where N 2 and K 2 are selected integers and n 5 represents cumulative noise. Optionally, the delay parameters N 1 and N 2 may be chosen to be equal but are preferably distinct. Optionally, the delay parameters K 1 and K 2 may be chosen to be equal but are preferably distinct. The receiver now forms the function

tan −1 {S 2 ( N 2 ; K 2 ;carr}/(2 π·K 2 · T s )= f D2 +n 6 ,  (6)

where n 6 represents noise associated with the function computed in Eq. (6) and is removable by appropriate low pass filtering. This second stage will, in most circumstances, provide an estimation of a residual f D2 of the total Doppler frequency offset, f D2 +f D1 . This sum, f D2 +f D1 , is within 1 percent of the symbol rate for the Doppler-shifted preamble signal s(t;carr).

In a third stage, a second frequency-shifted total signal

s 3 ( t )= s ( t )exp(−2 πj ·( f D2 +f D1 )· t )+ n 7 ( t )  (7)

is formed, where n 7 (t) represents noise, and the signal s 3 (t) is processed by a decision feedback phase locked loop (DFPLL) to acquire and track the residual carrier frequency and phase offset. If the transmitted symbols are modulated using quadrant phase shift keying (QPSK), the receiver preferably uses nonlinear processing to remove the QPSK modulation and to retrieve the unmodulated residual carrier for subsequent tracking.

As an example, a LEO communication satellite may transmit at a symbol rate of 25 Hz, and a sampling rate of f s =1/T s =150 KHz (six times oversampling) may be used, with an associated maximum Doppler frequency offset Δf D =±37.5 KHz. Channel multiplexing occurs using a time division multiple access (TDMA) format, with each time slot having a time slot including 64 preamble symbols, followed by 12 symbols representing a unique word, followed by 384 symbols representing the payload. As indicated in the preceding, the preambles are assumed to be unmodulated to allow for carrier recovery. The unique word section may use binary phase shift keying (BPSK) for timing and time slot synchronization, and the payload section may use differential-encoded quadrant phase shift keying (DE-QPSK) signals. More generally, the sampling rate f s may be any suitable rate (e.g., up to 1 MHz, or even higher) that the receiver can process, consistent with the known or estimated carrier frequency.

In one approach, 60 samples (N 1 =60) are provided during a first 10-preamble-symbol-interval to compute a first estimate f D1 of the Doppler frequency offset of the received signal, and a time delay corresponding to K 1 =1 is provided. A second group of 180 samples (N 2 =180) are provided during a second 30-preamble-symbol-interval, with a choice of time delay K 2 =20, to compute a second, more accurate estimate, f D2 +f D1 , of the Doppler frequency offset of the received signal. This approach uses 40 of the 64 preamble symbols in any time slot to provide an estimate of the Doppler frequency offset that is estimated to be within 1 percent of the true Doppler frequency offset, after the second stage. The over-sampling ratio (6:1), the time delay and the symbol length of the first and second intervals may be varied, consistent with the requirements for reliable statistics for the averaged signals and correlations. In the first stage, the magnitude of the Doppler offset estimation range is ±f s /2, or about ±75 KHz, with an estimation error of no more than 1 KHz for E b /N o ≧4.5 dB. An estimated Doppler-shifted signal produced by the first stage is fed back to correct a first intermediate center frequency so that the magnitude of the offset frequency for the preamble signal s 2 (t) presented to the second stage is no more than about 100 Hz. The delay parameter K 1 used for the first stage computations is preferably in the range K 1 =1-20 symbols so that, if desired, all computations can be completed using only the measurements taken from a single time slot.

The maximum frequency estimation range for the second stage is f 2 /2/20, or a maximum frequency range of ±3.75 KHz with E b /N o ≧4.5 dB. An estimated Doppler-shifted signal for the second stage is fed back to correct a second intermediate center frequency so that the magnitude of the offset frequency for the preamble signal s 3 (t) presented to the third stage is no more than about 100 Hz. The signal s 3 (t) is acquired and subsequently tracked by a DFPLL or other suitable tracking system. After the third stage is completed, the estimated Doppler offset residual is less than 10 Hz, with E b /N o ≧4.5 dB. This numerical example is illustrative and does not limit the ranges of the selected parameter values K 1 , K 2 , N 1 , N 2 , f carr , symbol rate, f s , oversampling rate, and other parameter values that may be selected for use with the invention.

FIG. 2 illustrates suitable first stage downconverter apparatus 21 associated with the receiver 13 for practicing one embodiment of the invention. A preamble of an incoming time slot information unit s(t) is provided as an in-phase signal s I (t;carr) and a quadrature signal s Q (t;carr) at input terminals, 22 I and 23 Q, respectively. The in-phase input signal s I (t;carr) provided at the input terminal 23 I is sampled at a selected sampling time interval 1/T s and is time delayed by a selected time interval K 1 ·T s by a time delay module 24 I. This time delayed version and the original version of the in-phase input signal s I (t;carr) are received at, and multiplied together by, a first multiplier module 27 I; the issued product s I (t−K 1 ·T s ;carr)s I (t;carr) is received at a first input terminal of a first sum module 29 I. The time delayed version of the signal provided at the input terminal 22 I and a non-time delayed version of a quadrature input signal s Q (t;carr) provided at the input terminal 23 Q are received at a second multiplier module 31 I, which forms and issues a product signal s I (t−K 1 ·T s ;carr)·s Q (t;carr). The product signal issued by the second multiplier module 31 I is received at one input terminal of a second sum module 33 Q.

The quadrature signal s Q (t;carr) provided at the input terminal 23 Q is time delayed by the time interval K 1 ·T s at a time delay module 25 Q and is received by a first input terminal of a third multiplier module 35 Q, which also receives the in-phase signal s I (t;carr) provided at tie input terminal 22 I. The product of these signals, s Q (t−K 1 ·T s ;carr)·s I (t;carr), is received by and summed at the second sum module 33 Q. The time-delayed and non-time-delayed versions of the quadrature signal s Q (t;carr) received the input terminal 23 Q are received and multiplied together by a fourth multiplier module 37 Q, and the product issued by this multiplier module is received at a second input terminal of the first sum module 29 I.

The sum produced by the first sum module 29 I is received at a third sum module 39 I, which forms one component of the first correlation signal S 1 (N 1 ;K 1 ;carr), using feedback with delay provided by a third time delay module 43 I, which has an associated time delay of K 1 units. The second sum module 39 I and the third time delay module 43 I serve as a first intermediate time delay loop 44 I for the sum formed at the module 39 I.

The sum produced by the second sum module 33 Q is received at a fourth sum module 41 Q, which forms another component of the first correlation signal S 1 (N 1 ;K 1 ;carr), using feedback with delay provided by a fourth time delay module 45 Q, which has an associated time delay of K 1 units. The fourth sum module 41 Q and the fourth time delay module 45 Q serve as a second intermediate time delay loop 46 Q for the sum formed at the module 41 Q.

The summed outputs of the third and fourth sum modules, 39 I and 41 Q, are received by an arctangent module 47 that forms and issues the function tan −1 {S 1 (N 1 ;K 1 ;carr)}. The output of the arctangent module 47 is received multiplied by the quantity {2π.K 1 ·T s } −1 at a fifth multiplier module 49 to produce a first estimated Doppler frequency offset f D1 for the carrier signal. The original carrier signals s I (t;carr) and s Q (t;carr) are also received at a first converter module 51 , where the carrier signals are multiplied by a downconversion signal that uses the first estimated Doppler frequency offset. A first converted in-phase carrier signal,

s I,1 (t;carr)=s I (t;carr)·cos{2 πj·f D1 ·t}+s Q (t;carr)·sin{2 πj·f D1 ·t}   (8)

and a first converted quadrature carrier signal,

s Q,1 ( t; carr=− s I ( t; carr)·sin{2 j·f D1 ·t}+s Q ( t; carr)·cos{2 πj·f D1 ·t},   (9)

defined as in Eq. (4), are issued by the converter module 51 .

In FIG. 3, the first converted carrier signals, s I,1 (t;carr) and s Q,1 (t;carr), are received at in-phase and quadrature input terminals, 63 I and 63 Q, respectively, of a second stage downconverter apparatus 61 that processes the received signal exactly as did the first stage converter apparatus 21 , but with possibly different parameters N 2 and K 2 replacing the corresponding parameters N 1 and K 1 , respectively. The result is a second estimated Doppler frequency offset f D2 , determined as in Eqs. (5) and (6). A second converter module 91 receives the signals f D2 , s I,1 (t;carr) and s Q,1 (t;carr) and forms and issues a second converted in-phase carrier signal

s I,2 ( t; carr)= s I,1 ( t; carr)·cos{2 πj·f D2 ·t}+s Q,1 ( t; carr)·sin{2 πj·f D2 ·t}   (10)

and a second converted quadrature carrier signal

s Q,1 ( t; carr)=−s I,1 ( t; carr)·sin{2 πj·f D2 ·t}+s Q,1 ( t; carr)·cos{2 πj·f D2 ·t}.   (11)

The second converted in-phase and quadrature signals are received at input terminals of a DFPLL system 101 , shown in FIG. 6 .

FIG. 4 illustrates suitable first stage downconverter apparatus 121 associated with the receiver 13 for practicing one embodiment of the invention. A preamble of an incoming time slot information unit s(t) is provided as an in-phase signal s I (t;carr) and a quadrature signal s Q (t;carr) at input terminals, 122 I and 123 Q, respectively. The in-phase input signal s I (t;carr) provided at the input terminal 122 I is sampled at a selected sampling time interval 1/T s and is time delayed by a selected time interval K 1 ·T s by a time delay module 124 I. This time delayed version and the original version of the in-phase input signal s I (t;carr) are received at, and multiplied together by, a first multiplier module 127 I; the issued product s I (t−K 1 ·T s ;carr)·s I (t;carr) is received at a first input terminal of a first sum module 129 I. The time delayed version of the signal provided at the input terminal 122 I and a non-time delayed version of a quadrature input signal s Q (t;carr) provided at the input terminal 123 Q are received at a second multiplier module 131 I, which forms and issues a product signal s I (t−K 1 ·T s ;carr)·s Q (t;carr). The product signal issued by the second multiplier module 131 I is received at one input terminal of a second sum module 133 Q.

The quadrature signal s Q (t;carr) provided at the input terminal 123 Q is time delayed by the time interval K 1 ·T s at a time delay module 125 Q and is received by a first input terminal of a third multiplier module 135 Q, which also receives the in-phase signal s I (t;carr) provided at the input terminal 122 I. The product of these signals, s Q (t−K 1 ·T s ;carr)·s I (t;carr), is received by and summed at the second sum module 133 Q. The time-delayed and non-time-delayed versions of the quadrature signal sQ(t;carr) received the input terminal 123 Q are received and multiplied together by a fourth multiplier module 137 Q, and the product issued by this multiplier module is received at a second input terminal of the first sum module 129 I.

The sum produced by the first sum module 129 I is received at a third sum module 139 I, which forms one component of the first correlation signal S 1 (N 1 ;K 1 ;carr), using feedback with delay provided by a third time delay module 143 I, which has an associated time delay of K 1 units. The sum formed at the third sum module 139 I is passed forward by a first interrogation module 153 I if the most significant bit (MSB) of the sum is 0; if the MSB is 1, the sum is shifted right one unit and the resulting modified sum is passed forward. The second sum module 139 I, the first interrogation module 153 I and the third time delay module 143 I serve as a first intermediate time delay loop for the sum formed at the sum module 139 I.

The sum produced by the second sum module 133 Q is received at a fourth sum module 141 Q, which forms another component of the first correlation signal S 1 (N 1 ;K 1 ;carr), using feedback with delay provided by a fourth time delay module 145 Q, which has an associated time delay of K 1 units. The sum formed at the fourth sum module 141 Q is passed forward by a second interrogation module 155 Q if the MSB of the sum is 0; if the MSB is 1, the sum is shifted right one unit and the resulting modified sum is passed forward. The fourth sum module 141 Q, the second interrogation module 155 Q and the fourth time delay module 145 Q serve as a second intermediate time delay loop for the sum formed at the sum module 141 Q.

The sum produced by the first sum module 129 I is received at a third sum module 139 I, which forms one component of the first correlation signal S 1 (N 1 ;K 1 ;carr), using feedback with delay provided by a third time delay module 143 I. The sum produced by the second sum module 133 Q is received at a fourth sum module 141 Q, which forms another component of the first correlation signal S 1 (N 1 ;K 1 ;carr), using feedback with delay provided by a third time delay module 145 Q. The summed outputs of the third and fourth sum modules, 139 I and 141 Q, are received by an arctangent module 147 that forms and issues the function tan −1 {S 1 (N 1 ;K 1 ;carr)}. The output of the arctangent module 147 is received multiplied by the quantity {2π.K 1 ·T s } −1 at a fifth multiplier module 149 to produce a first estimated Doppler frequency offset f D1 for the carrier signal. The original carrier signals s I (t;carr) and s Q (t;carr) are also received at a first converter module 151 , where the carrier signals are multiplied by a downconversion signal, exp{−2πj·f D1 ·t}. First converted in-phase and quadrature carrier signals, s I,1 (t;carr) and s Q,1 (t;carr), defined as in Eqs. (8) and (9), are issued by the converter module 151 .

In FIG. 5, the first converted carrier signals, s I,1 (t;carr) and s Q,1 (t;carr), are received at in-phase and quadrature input terminals, 162 I and 163 Q, respectively, of a second stage downconverter apparatus 161 that processes the received signal exactly as did the first stage converter apparatus 121 , but with possibly different parameters N 2 and K 2 replacing the corresponding parameters N 1 and K 1 , respectively. The result is a second estimated Doppler frequency offset f D2 , determined as in Eqs. (5) and (6). A second converter module 191 receives the signals f D2 , s I,1 (t;carr) and s Q,1 (t;carr) and forms and issues second converted in-phase and quadrature carrier signals, s I,2 (t;carr) and s Q,2 (t;carr), defined as in Eqs. (10) and (11). The second converted in-phase and quadrature signals are received at input terminals of a DFPLL system 201 , shown in FIG. 6 .

Any of the following four combinations of first stage and second stage can be used with the invention: 21 and 61 , 21 and 161 , 121 and 61 , 121 and 161 .

FIG. 6 illustrates a DFPLL third stage 201 for the carrier recovery and Doppler offset estimation process. The signals s I,2 (t;carr) and s Q,2 (t;carr) are received at the I and Q input terminals of an arctangent module 202 . The output phase angle φ(carr) is received at one input terminal of a phase comparator 203 . A second input terminal of the phase comparator 203 is received from an NCO or VCO 205 in a feedback arrangement that forms a phase locked loop (PLL). An output of the phase comparator, representing a phase error signal, is received by a mask module 207 that masks the two most significant bits (MSBs) of the received signal and passes the masked signal to a first multiplier module 221 that has a parameter c 0 that is selected by a first coefficient module 217 . In one embodiment, the parameter c 0 has one selected value, which is used to rotate the signal received from the mask module 113 by ±45°.

The output of the first sum module 215 is received by a loop filter 219 that is part of the feedback loop of the PLL. Within the loop filter 219 , the output of the first sum module 215 is received by a first weighted multiplier module 221 that has a parameter c 1 selected by a second coefficient module 223 . In one embodiment, the parameter c 1 has a first value, c 1 =750 Hz (binary value b00010101 or 00111100), when the PLL is in an acquisition mode and has a second value, c 1 =250 Hz (binary value b101101110), when the PLL operates in a tracking mode. The output of the first multiplier module 221 is received by a second sum module 225 that serves as an integrator.

The output of the first sum module 215 is also received by a second weighted multiplier module 227 that has a parameter c 2 selected by a third coefficient module 229 . In one embodiment, the parameter c 2 has a first value, c 2 =750 Hz (binary value b00010101), when the PLL is in an acquisition mode and has a second value, c 2 =250 Hz (binary value b11000000), when the PLL operates in a tracking mode. The output of the second multiplier module 227 is received by a third sum module 231 that, together with a one-time-step delay module 233 , forms a first intermediate delay-feedback loop 235 within the loop filter 219 . The output of the intermediate loop 235 is received and processed by a mask module 237 , which issues a signal including only the 13 MSBs, and is fed back to the NCO 205 .

The output of the intermediate loop 235 is received by a sampling module 207 within the NCO 205 . The output of the sampling module 207 is received by a third sum module 209 . The sum module 209 , together with a one-time-step delay module 211 , forms a second intermediate delay-feedback loop 212 within the NCO 205 . The output phase signal φ(PLL) of the third sum module 209 is received at the second input terminal of the phase comparator 203 and is received at an input terminal of each of a cosine module 241 and a sine module 243 that form cosφ(PLL) and sinφ(PLL) for subsequent use.

In broad outline, the input signals s I,1 (t;carr) and s I,Q (t;carr) for the DFPLL apparatus 201 are processed by the arctangent module 202 to determine the present carrier phase φ(carr), which is implemented using a CORDIC algorithm. The resulting phase φ(carr) is subtracted from the phase φ(PLL) produced by the NCO 205 to provide an error signal ε that is processed by the PLL. The error signal can be directly fed into a slicer for symbol decision. To remove the accompanying QPSK modulation, the error signal ε is mapped to the first quadrant, then shifted by 45° clockwise so that ε is mapped to ±45°. The phase angles after processing by the arctangent module 202 (±180°) are normalized. By masking the two MSBs of the phase error signal ε in the mask module 113 , the error signal is mapped into the first quadrant and the QPSK modulation is removed. The phase error signal ε is then rotated by 45° clockwise, and the phase error signal is now mapped to ±45°. The mapped error signal ε is then passed through an integrator-type loop filter (which serves as a low pass filter for the PLL), with adjustable bandwidth. The output of the loop filter 219 is fed to the NCO 205 for phase correction. The PLL is updated at a symbol rate of 25 KHz with loop filter bandwidth of 750 Hz for phase acquisition and 250 Hz for phase tracking.

The embodiment of the invention discussed in the preceding includes an LP first stage and an LP second stage, which correct the Doppler-shifted frequency, and a DFPLL third stage, which corrects one or both of Doppler-shifted frequency and phase for the received signal. FIG. 7 graphically illustrates some results of the numerical example discussed in the preceding. A signal preamble, which includes the carrier signal but not the message, includes 64 symbols and is followed by a unique word (UW) including another 12 symbols. A 384-symbol payload section follows the preamble and UW sections of the time slot, as shown. The first LP stage uses 10 preferably consecutive symbols and a delay time of K 1 ·T s =T s to form a correlation function, using these first 10 symbols and an oversampling rate of 6 to provide 60 values at a sampling rate of f s =1/T s , where f s /6 is the symbol rate. The first estimation f D1 for the Doppler frequency offset is computed using the relations (2) and (3).

The second LP stage, uses 30 preferably consecutive symbols from the preamble section, optionally beginning immediately following the last of the 10 symbols used for the first stage, with a delay time K 2 ·T s =20 T s and an oversampling rate of 6 to provide 180 values at a sampling rate of f s . The second (residual) estimation f D2 for the residual Doppler frequency offset is computed using the relations (5) and (6). The computations of f D1 and f D2 may be completed before the receiver 13 (FIG. 1) has received all 64 symbols from the presently received time slot.

The DFPLL third stage preferably uses a loop bandwidth (BW) of 750 Hz, which is switched to 250 Hz after capture and lock occurs, and part or all of the remainder of the preamble section (up to 24 symbols) and part or all of the UW symbols and payload symbols are used to determine the residual f D3 of the total Doppler frequency offset,

f D (est)=f D1 +f D2 +f D3 ,  (12)

where f PLL (n) is a frequency estimation value at the output of the DFPLL system at symbol number n and N is the number of symbols (preamble and/or UW and/or payload) used to estimate the residual Doppler frequency offset within the third stages. Preferably, the integer N is large, in a range of 100-400 in the preceding numerical example.

This estimation of the total Doppler frequency offset is estimated to be accurate to within 10 Hz of the “true” Doppler frequency offset. FIG. 8 graphically illustrates the Doppler frequency offset estimation error (*) and associated standard deviation (o), obtained by simulation, versus the E b /N o ratio for the received signal s(t). For E b /N o greater than or equal to 4.5 dB, the estimation error decreases monotonically from about 2.5 Hz toward 0 and the associated standard deviation decreases monotonically from about 18 Hz toward 0, as the ratio E b /N o increases. Where the statistics are further enhanced by averaging the values for 100 time slots, the estimation error and associated standard deviations are reduced to about 1 Hz and 3 Hz, respectively, for E b /N o ≧4.5 dB, according to the simulation results.

The disclosed invention has relatively low complexity, allowing application of much less computing power than is required for a standard FFT approach. The invention is relatively fast and works with arbitrarily large Doppler offset, f D , and each stage reduces the residual by one or more orders of magnitude. The invention provides an estimate of the total Doppler frequency offset f D (est) that is within 10 Hz, often within 3 Hz, of the true Doppler frequency offset for the received signal, for E b /N o ≧4.5 dB. Finally, the invention is robust and can estimate Doppler shift and allow recovery of carrier frequency and phase under low SNR conditions. The center frequency used for signal acquisition can be shifted by the Doppler frequency offset and the received signal can be subsequently tracked, even where the Doppler offset is changing rapidly.

FIG. 9 shows a block diagram of a general computer system 300 , which may be used to implement various hardware components of the invention, such as a client, an applications server and a database management system. The computer system 300 includes a bus 302 or other communication mechanism for communicating information and a processor 304 , coupled with the bus 302 , for processing information. The computer system 300 also includes a main memory 306 , such as a random access memory (RAM) or other dynamic storage device 308 , coupled to the bus 302 , for storing information and instructions to be executed by the processor 304 . The main memory 306 also may be used for storing temporary variables or other intermediate information during execution of instructions by the processor 304 . The computer system 300 further optionally includes a read only memory (ROM) 310 or other static storage device, coupled to the bus 302 , for storing static information and instructions for the processor 304 . A storage device 312 , such as a magnetic disk or optical disk, is provided and is coupled to the bus 302 for storing information and instructions.

The computer system 300 may also be coupled through the bus to a display 314 , such as a cathode ray tube (CRT), for displaying information to a computer user. An input device 316 , including alphanumeric and other keys, is coupled to the bus for communicating information and commands to the processor 304 . Another type of user input device is a cursor control 318 , such as a mouse, a trackball or cursor direction keys for communicating direction information and command selections to the processor 304 and for controlling cursor movement on the display 314 . This input device typically has one degree of freedom in each of two axes, such as x- and y-axes, that allows the device to specify locations in a plane.

The functionality of the invention is provided by the computer system 300 in response to the processor 304 executing one or more sequences of instructions contained in main memory 306 . These instructions may be read into main memory 306 from another computer-readable medium, such as a storage device 314 . Execution of the sequences of instructions contained in the main memory 306 causes the processor 304 to perform the process steps described herein. In alternative embodiments, hard-wired circuitry may be used in place of, or in combination with, software instructions to implement the invention. Embodiments of the invention are not limited to any specific combination of hard-wired circuitry and software.

The term “computer-readable medium”, as used herein, refers to any medium that participates in providing instructions to the processor 304 for execution. This medium may take many forms, including but not limited to non-volatile media, volatile media and transmission media. Non-volatile media includes, for example, optical and magnetic disks, such as the storage disks 312 . Volatile media includes dynamic memory. Transmission media includes coaxial cables, copper wire and fiber optics and includes the wires that are part of the bus 302 . Transmission media can also take the form of acoustic or electromagnetic waves, such as those generated during radiowave, infrared and optical data communications.

Common forms of computer-readable media include, for example, a floppy disk, a flexible disk, a hard disk, magnetic tape or any other magnetic medium, a CD-ROM, any other optical medium, punchcards, papertape, any other physical medium with patterns of holes or apertures, a RAM, a ROM, a PROM, an EPROM, a Flash-EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can be read.

Various forms of computer-readable media may be involved in carrying out one or more sequences of one or more instructions to the processor 304 for execution. For example, the instructions may initially be carried on a magnetic disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions over a telephone, using a modem. A modem local to the computer system 300 can receive data over a telephone line and use infrared transmitter to convert and transmit the data to the an infrared detector connected to the computer system bus. The bus will carry the data to the main memory 306 , from which the processor receives and executes the instructions. Optionally, the instructions receive by the main memory 306 can be stored on the storage device 312 , either before or after execution by the processor 304 .

The computer system 300 also includes a communications interface 319 , coupled to the bus 302 , which provides two-way data communication coupling to a network link 320 that is connected to a local area network (LAN) or to a wide area network (WAN). For example, the communications interface 319 may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, the communications interface 319 may be a local area network card to provide a data communication connection to a compatible LAN. Wireless links may also be implemented. In any such implementation, the communications interface 319 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information.

The network link 320 typically provides data communication through one or more networks to other data devices. For example, the network link 320 may provide a connection through an LAN 322 to a host computer 324 or to data equipment operated by an Internet Service Provider (ISP) 326 . The ISP, in turn, provides data communication services through the world wide packet data communication network, now commonly known as the “Internet” 328 , served by one or more servers 330 . The LAN 322 and the Internet 328 both use electrical, electromagnetic and/or optical signals to carry the digital data streams. The signals carried by these network, the signals carried on the network link 320 and the signals carried on the communications interface 319 , are examples of carrier waves that transport the information.