System and method for eliminating jitter by using a starve/inspect approach to AAL1

This invention relates to the field of telephony using ATM networks and more particularly to techniques for processing telephony signals communicated over ATM networks using ATM Adaptation Layer 1 (AAL 1 ) telephony.

Asynchronous transfer mode (ATM) is an approach to communicate data in fixed packets or cells. ATM Adaptation Layer 1 (AAL 1 ) is used to carry telephony traffic through an ATM network using ATM cells. In order to transport the analog telephony signal across an ATM network, the telephony signals at the source of the transmission are digitized by sampling the analog signals at regular intervals. For example, 8-bit digital samples of a voice signal may be sampled at regular 125 μs (8 kHz) intervals. The digital information corresponding to the analog signal may then be packed into ATM cells and transported to the destination across the ATM network.

After the cells arrive at the destination, the information contained in the cells is extracted to form frames. Within an AAL 1 data stream, telephony traffic is carried in “frames.” Each frame is the complete set of 8-bit digital samples that are collected during a single 125 μs period for all of the voice channels (DS- 0 s) being carried within the AAL 1 stream. Frames may or may not overlap exactly with the 47 (sometimes fewer) byte payload of an AAL 1 cell. In order to reproduce the transmitted telephony signal at the destination, the frames storing the recurrent sequence of samples are converted back to an analog signal.

As the cells carrying the telephony signal pass through the ATM network, they encounter variable delay, or “jitter.” Jitter results due to dynamically changing buffer fullness in the ATM switches on the AAL 1 cell path, which is in turn due to the presence of other ATM traffic in these switches. Accordingly, jitter causes ATM cells to arrive at irregular intervals at the receive end of the network. Jitter is not acceptable because it prevents proper reconstruction, at regular intervals, of the analog signal. All of the different variants of AAL 1 suffer from jitter problems. Consequently, in order for telephony traffic to be transported using AAL 1 , the jitter associated with ATM AAL 1 cells needs to be eliminated.

Conventional approaches attempt to reduce or eliminate jitter by using various buffering schemes. The level of buffering used by these schemes is based on the overall jitter conditions in the ATM network. However, since the jitter conditions associated with the cells are unknown and variable, in order to use these buffering techniques, a computationally difficult algorithm is typically employed to perform network jitter analysis to determine the optimal buffering level for the network. This process is usually time consuming and expensive. Typically this algorithm is employed at the receive end of the communication.

Thus, there is a need for techniques which can remove jitter associated with AAL 1 telephony traffic without having to perform complex network analysis and which can be adapted to changing network conditions.

The present invention provides techniques for removing jitter associated with ATM cells transported using AAL 1 . In one embodiment, a starve/inspect buffering technique is used to remove jitter while avoiding unneeded buffering that would cause excessive delay.

According to one aspect of the present invention, a first-in-first-out (FIFO) buffer is provided for queuing the frames containing data extracted from the AAL 1 cells. Frames are written to the tail of the buffer and can be read from the head of the buffer for processing purposes. When buffer starvation occurs because of jitter associated with the AAL 1 cells, a replacement frame may be inserted into the buffer and made available to the reader. This increments the average buffer fullness level which can be dynamically increased if jitter conditions increase.

According to another aspect of the present invention, when the jittered cells arrive, the frames corresponding to the jittered cells are inserted into the buffer after the replacement frames. The jittered frames may then be read and processed in subsequent time periods.

According to another aspect of the present invention, an “inspect” approach is used to minimize the increases in the average fullness level of the FIFO, which may result due to infrequent and unusually long jitter. In one embodiment, the present invention maintains a minimum buffer level indicator to keep track of the minimum buffer fullness level for a given time period. The present invention then determines if the minimum buffer fullness level has an optimum value after an observation time period. In one embodiment, the optimal value is zero. If the minimum buffer level indicator has a value higher than the optimal value, then according to the present invention, frames are slipped or removed from the buffer. This reduces the average buffer fullness of the buffer which counteracts creep. Other technical advantages are readily apparent to one skilled in the art from the following figures, description, and claims.

For a more complete understanding of the present invention, and for further features and advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, where like reference numerals represent like parts, in which:

FIG. 1 is a simplified block diagram depicting a network environment for transferring telephony signals via an ATM network using AAL 1 according to an embodiment of the present invention;

FIG. 2 depicts a FIFO buffer according to an embodiment of the present invention; and

FIG. 3 is a flowchart depicting steps performed by a buffer processing system to minimize creep according to an embodiment of the present invention.

FIG. 1 depicts a network environment 10 incorporating the present invention. Network environment 10 facilitates transfer of telephony signals from telephony system 14 to telephony system 22 via ATM network 16 using AAL 1 . Telephony system 14 converts multiple analog telephony signals 12 to ATM AAL 1 cells which are then communicated via ATM network 16 to destination telephony system 22 . Telephony system 14 digitizes analog signals 12 by sampling analog signal 12 at regular time intervals. For example, 8-bit digital samples of analog signals 12 are sampled at regular 125 μs (8 kHz) intervals. The digital information corresponding to analog signals 12 are then packed into ATM cells and transported to destination telephony system 22 via ATM network 16 using AAL 1 .

As the ATM cells pass through ATM network 16 , they experience jitter or delay which causes the cells to arrive at irregular intervals at the receiving port/end 18 of ATM network 16 . As previously stated, jitter introduces errors in the reconstruction of the analog signal from the digital information stored in the ATM cells at the receiving end. In order to reduce the effects of jitter, the ATM cells are first filtered through dejitter system 20 before being forwarded to telephony system 22 for analog conversion. Dejitter system 20 is responsible for extracting the digital information stored in the ATM cells into frames and buffering the frames so as to remove jitter while minimizing the delay introduced by the buffering.

The jitter effects associated with the AAL 1 cells are reduced by using a buffering technique that incorporates a unique starve/inspect approach. The frames that arrive at dejitter system 20 in cell payloads at the AAL 1 SAR layer are controllably buffered in a first-in-first-out (FIFO) buffer to remove jitter. FIG. 2 depicts a FIFO buffer 50 of dejitter system 20 that provides a queuing mechanism for storing a plurality of frames, for example, 125 μs frames 52 , 54 , 56 , 58 , and 60 , each composed of a fixed number of DS- 0 samples. A tail pointer 64 indicates the location of the last or latest frame within buffer 50 . Frames 52 , 54 , 56 , 58 , 60 are extracted from ATM AAL 1 cells as they arrive at dejitter system 20 and are written to the tail of buffer 50 .

A head pointer 62 indicates the location of the first or earliest frame within buffer 50 . Since buffer 50 is a FIFO, head pointer 62 also points to the next frame available to be read from buffer 50 . For example, the head of buffer 50 indicated by head pointer 62 contains frame 52 . Frame 66 represents a frame which has been read from the head of buffer 50 for processing. Frames are read from buffer 50 by telephony system 22 . Buffer 50 can be implemented in a variety of ways, such as using circular buffer format, using link-listed pointers, or by using other techniques known to those of ordinary skill in the art.

A FIFO control circuit 27 manages the head and tail pointers, as well as other FIFO calculations. These include buffer fullness level and minimum buffer fullness level. FIFO control circuit 27 operates under the supervision of a processor 28 which controls dejitter system 20 . Processor 28 couples to a memory 30 , which may be integral or separate volatile or non-volatile storage. Memory 30 maintains program instructions and data accessible by processor 28 to control the operation of dejitter system 20 .

In one embodiment, a frame is regularly read by telephony system 22 from the head of buffer 50 at 125 μs intervals for conversion of the digital signal back to an analog telephony signal. Starvation occurs when AAL 1 cells are delayed due to jitter and buffer 50 has no frames to offer to telephony system 22 when required. In order to prevent such starvation, the frames containing the DS- 0 channels are buffered for an average time period corresponding to their maximum jitter “J,” wherein “J” is rounded up to an integer. In one embodiment, “J” is rounded to an integer number of 125 μs frame periods. For example, a “J” with a value of “2” indicates a maximum jitter of 250 μs frame periods. Given maximum jitter “J,” the required level of FIFO buffering can be determined as (2* J)+1 frames, where the extra frame is used to hold the DS- 0 s being output to telephony system 22 in the current frame period.

However, as previously stated, the value of “J” is unknown and variable for any incoming frame. Accordingly, it is not possible to deterministically set the initial fill level of buffer 50 or the average fullness level of buffer 50 without performing complex network analysis.

Dejitter system 20 solves the above problem by eliminating the need to determine a maximum jitter “J” value. FIFO control circuit 27 initializes buffer 50 to empty and initializes the tail 64 and head 62 pointers to the same empty buffer location. When telephony system 22 expects to read a frame from the head of buffer 50 and no frames are available to be read, the FIFO control circuit 27 configures a replacement frame which is passed to telephony system 22 as a replacement for the missing DS- 0 frame. In one embodiment, the replacement frame may be made up of all “1”s type DS- 0 s or alternatively DS- 0 s from a previous frame.

When the jittered cell (or cells) subsequently arrives, the frame containing the DS- 0 s content for the jittered cell(s) is then loaded into buffer 50 and read by telephony system 22 in subsequent 125 μs frame periods. As a result, there is a “frame slip” that adds a single frame (or more) to the average buffer fullness level. In this manner, the average buffer fullness level can be set and thereafter increased if the jitter conditions increase. The insertion of replacement frames enables telephony system 22 to perform the digital to analog conversion without being affected by the jitter associated with the incoming AAL 1 cells.

A side-effect of the above described starvation based approach is that infrequent and unusually long jitter induced delays can result in the average buffer fullness level being increased to buffer levels beyond an appropriate or necessary level. More specifically, unusually long delays may result in prolonged starvation of buffer 50 , followed by a large burst of the delayed cells. This cell “clumping” increases the average buffer fullness because the frames are read out of the buffer at a deterministic rate regardless of the ingress cell rate. This problem of “creep” can cause excessive and unnecessary delay through buffer 50 .

In order to reduce creep, dejitter system 20 maintains a minimum buffer fullness indicator which indicates the minimum buffer fullness level value for a given time period. Proccessor 28 monitors the buffer fullness level of buffer 50 at regular time intervals.

FIG. 3 is a flowchart 70 depicting steps performed by processor 28 in conjunction with FIFO control circuit 27 to minimize creep. Specifically, processor 28 initializes the minimum buffer fullness indicator (MBFI) in FIFO control circuit 27 to an arbitrary high value, for example, a value larger than the required buffer size (step 72 ). Subsequently, each time it outputs a frame, FIFO control circuit 27 checks the buffer fullness level of buffer 50 (step 74 ). FIFO control circuit 27 then determines if the buffer fullness level value determined in step 74 is lower than the value indicated by the minimum buffer fullness level indicator (step 76 ). If the buffer fullness level determined in step 74 is lower than the value indicated by the minimum buffer fullness level indicator, the minimum buffer fullness indicator is set to the value determined in step 74 (step 78 ). Processor 28 then determines if the predetermined inspection time period has been completed (step 80 ). If not, the buffer fullness level is repeatedly monitored at step 74 . In this manner, the minimum buffer fullness level is monitored over a period of time using the minimum buffer level indicator.

If the predetermined time period has completed, processor 28 then inspects the value of the minimum buffer fullness indicator (step 82 ). Optimally, the minimum buffer fullness indicator should have a value of zero (given a long enough sampling interval). A minimum buffer fullness indicator value of greater than zero indicates that buffer 50 is buffering more frames than required to eliminate the jitter, thus resulting in unnecessary delay through buffer 50 . In response, processor 28 , using the FIFO control circuit 27 , forces one or more frames to be skipped from the head of buffer 50 (step 84 ). The skipping of frames is generally done one at a time, in an orderly manner, over a reasonable period of time. This in effect reduces the average buffer fullness level to appropriate levels and minimizes creep. The process may then be restarted for another time period at step 72 .

As described above, by combining starvation and inspection based approaches, dejitter system 20 facilitates an overall “starve/inspect approach” to AAL 1 dejittering. Unlike other AAL 1 approaches, no calculations have to be performed using network traffic characteristics in order to determine ahead of time how to configure the AAL 1 dejittering system.

Although specific embodiments of dejitter system 20 have been described, various modifications, alterations, alternative constructions, and equivalents are also encompassed within the scope of this application. For example, the structure of buffer 50 is not limited to the embodiment shown in FIG. 2 . Alternate configurations of buffer 50 having more or less subsystems than the embodiment depicted in FIG. 2 are also within the scope of the present invention. In other embodiments, the subsystems of buffer 50 may be combined into one or more subsystems or with other network systems. Further, the names given to the subsystems do not in any way limit the functional scope of the subsystems.

The described invention is not restricted to operation within certain specific data processing environments, but is free to operate within a plurality of data processing environments. Additionally, although the present invention has been described using a particular series of transactions and steps, for example, the flowchart depicted in FIG. 3, it should be apparent to those skilled in the art that the scope of the present invention is not limited to the described series of transactions and steps.

Further, while the present invention has been described using a particular combination of hardware and software, it should be recognized that other combinations of hardware and software are also within the scope of the present invention. The present invention may be implemented only in hardware or only in software or using combinations of hardware and software.