Method and system for error isolation during PCI bus configuration cycles

1. Technical Field

The present invention relates to error analysis in information processing systems. More specifically, it relates to isolation of faulty peripheral component interface (PCI) adapters on a PCI bus during input/output sub-system initialization.

2. Description of the Related Art

When a failure occurs on a PCI bus, after system start-up but before machine check handling has been enabled, it is desirable to automatically determine which adapter is responsible for the fault condition. This procedure is difficult because prior to enabling machine check handling, the error condition will checkstop the system. Since there is no scan out capability on the remote I/O drawers where the PCI devices are located, it is not possible to scan out error registers for interrogation. A conventional service procedure is based on treating every bus adapter as suspect. System configuration is modified to comprise its minimum configuration; and, thereafter each adapter card is sequentially tried until the failure occurs in that configuration.

Such a scheme for recreating an error condition in order to identify the faulty adapter is problematic. The procedure often induces additional errors due to physically plugging and unplugging adapter cards. Further, such a sequential procedure adds considerable time to any error repair scenarios.

Check pointing during system startup to determine faulty components is a procedure known in the art. Typically, in a check point procedure, a periodic copy of a program or the state of a computer system is made so that if a failure occurs, recovery can be initiated from the last saved checkpoint and restarted. This invention uses the concept of checkpoints to save the last known PCI address that was attempted to be accessed during the PCI configuration cycle to identify the probable source of failure. In addition, progress codes are presented by the initial program load read only storage (IPLROS) firmware to indicate the progress of the boot sequence. The progress code will indicate that the PCI bus was being configured and the checkpoint will be used to identify the probable source of the failure.

Commonly assigned co-pending application Ser. No. 08/829,088 entitled “A Method and System for Fault Isolation for PCI Bus Errors” teaches a mechanism for identifying a source of an error condition in the I/O mechanism.

U.S. Pat. No. 5,815,647 to Buckland et al., provides a system which allows a user to identify which of a plurality of feature cards has issued an error signal.

IBM Technical Disclosure Bulletin, Vol. 37, No. 08, page 619, discloses a recursive algorithm for initializing error handling logic for a PCI system.

None of these references provides for saving an address indicator prior to accessing that address.

Thus, it is desirable to have a speedy, certain technique for identifying faulty components which prevent a system from completing system start-up and entering its diagnostic routines.

It is further desirable to isolate and diagnose errors in a manner that eliminates the possible introduction of further error conditions.

The present invention overcomes the shortcomings of the prior art by providing a shared mailbox space in memory for use by a service processor during PCI bus and adapter initialization sequence. The address of an adapter is placed in the shared memory space before an attempt to access that adapter is made. If an error occurs during the access attempt, the service processor retrieves the address saved in the shared mailbox and immediately performs its error isolation procedure for determining the slot at fault. In this way the adapter card causing an I/O subsystem failure, rather than the entire I/O subsystem, may be analyzed.

The above and other features and advantages of a preferred embodiment of the present invention will be described in conjunction with the following drawings wherein:

FIG. 1 depicts a block diagram of a data processing system in which a preferred embodiment of the present invention may be implemented; and

FIG. 2 illustrates the logic executed within processor 18 and service processor 50 of FIG. 1 .

With reference now to the figures and in particular with reference to FIG. 1, there is depicted a block diagram of an illustrative embodiment of a data processing system or information handling system with which the present invention may advantageously be utilized. The illustrative embodiment depicted in FIG. 1 is a workstation or server computer system; however, as will become apparent from the following description, the present invention may also be applied to any other data processing or information handling system.

As illustrated in FIG. 1B, data processing system 10 includes a system planar 12 coupled to one or more processor cards (in this case processor cards 14 a- 14 c ) and one or more input/output (I/O) drawers (in this case drawers 16 a - 6 d ). In the depicted embodiment, each processor card 14 carries four general purpose processors 18 each of which has an on-chip level one (L1) cache (not illustrated) and an associated level two cache 20 that provide low latency storage for instructions and data. Processors 18 on each processor card 14 are all connected to address and control bus 24 and to an associated data bus 22 a - 22 c.

As illustrated, system planar 12 includes a bus arbiter 26 that regulates access to address and control bus 24 by processors 18 , as well as flow control logic 30 and I/O hub 32 , which are each connected to address and control bus 24 . Flow control logic 30 is further connected to dual-ported system memory 34 and data switches 28 a - 28 d, and I/O hub 32 is further connected to data switches 28 by data bus 22 d and to each of I/O drawers 16 a - 16 d by a respective one of primary remote I/O (RIO) buses 40 a - 40 d . Address transactions issued on address and control bus 24 are received by both flow control logic 30 and I/O hub 32 . If an address transaction specifies an address associated with a location in system memory 34 , flow control logic 30 forwards the address to system memory 34 as an access request. Alternatively, if the address transaction specifies a memory mapped I/O address associated with an I/O device contained in one of I/O drawers 16 a - 16 d, I/O hub 32 routes the address transaction to the appropriate I/O drawer 16 via its primary RIO bus 40 . Flow control logic 30 also supplies control signals to data switches 28 to control the flow of data transactions between processor cards 14 and system memory 34 and I/O hub 32 .

Referring now to I/O drawers 16 a - 16 d, each I/O drawer 16 contains an I/O bridge 42 that is directly connected to I/O hub 32 by its respective primary RIO bus 40 and is coupled either directly or indirectly to I/O hub 32 via a secondary RIO bus 46 e.g., either secondary RIO bus 46 a or 46 b ). That is, in embodiments of data processing system 10 in which only a single I/O drawer 16 is installed, I/O bridge 42 is directly connected to I/O hub 32 by both a primary RIO bus 40 and a secondary RIO bus 46 . In other embodiments in which multiple I/O drawers 16 are installed, each I/O drawer 16 is connected to I/O hub 32 by a single primary RIO bus 40 and is connected to another I/O drawer 16 through a secondary RIO bus 46 . Thus, I/O hub 32 has redundant paths through which it can communicate to each installed I/O drawer 16 . Each I/O bridge 42 is connected to up to four peripheral component interconnect (PCI) bus controllers 44 , which each supply connections for up to four PCI devices. As shown in FIG. 1C, the PCI devices in stalled in drawer 16 a include service or local processor 50 and nonvolatile random access memory (NVRAM) 52 . Other PCI devices that may be attached to PCI controllers 44 of I/O drawers 16 a - 16 d include small computer system interface (SCSI) adapters, local area network (LAN) adapters, etc.

Routines for performing analysis on PCI bus initialization errors are resident in service processor 50 . NVRAM 52 is provided for, inter alia, containing the shared mailbox 54 of the present invention. In this manner, direct access to the mailbox is enabled when, in accordance with a preferred embodiment of the present invention, an architected location indicator of a failing PCI device must be retrieved in the course of performing error analysis.

Refer now to FIG. 2, a flow chart of the error isolation logic executed within service processor 50 and system processor 18 , FIG. 1 . Steps 80 through 98 are executed by system processor 18 as part of an initialization process run in preparation for operating system load. Steps 100 through 108 show the error isolation process executed with in service processor 50 .

The error isolation method of the present invention begins at step 80 during system start-up. That step sets the first PCI bus address. At step 82 the PCI bus device address is set equal to zero. At test 84 the logic determines whether the address in question represents a device slot. If the address is that of a device slot, at step 86 that address is stored in the mailbox in NVRAM 52 , FIG. 1 .

If, however, the address is not that of a device slot, then at step 88 the address is probed by having the PCI issue a command and await a response. If at test 90 it is determined by examination of the response that a critical PCI configuration cycle error has occurred, then the logic branches to step 100 . If the result of test 90 is negative, then at step 92 the logic proceeds to the next PCI address. At test 94 the logic determines if it has completed checking all addresses associated with a bus, and if not, the logic returns to test 84 and looks at the next address. If however, all addresses on that bus have been examined, then at test 96 the logic determines if all the buses are done. If not, the logic returns to step 82 where the next PCI bus device address is set to zero. If all buses are finished, then at step 98 the normal boot process continues.

Returning now to test 90 , if it is determined that a critical PCI configuration cycle error has occurred, then at step 100 an interrupt is raised to service processor 50 . At step 104 the service processor displays the address previously stored in the mailbox at step 86 . As is well understood in the art, the display may be an operator panel which, for example, may be a 2 line×16 digit liquid crystal device (LCD).

Various error analysis routines which are not part of the present invention may then be performed. Then at step 108 the system start-up routine is halted. In summary, the present invention performs error isolation by using a combination of the progress code, which indicates that the system was performing PCI configuration, and the address information in mailbox register 54 to provide an architected location code to identify the failing PCI adapter.

In accord with the present invention, the address of the PCI adapter is placed in a mailbox register 54 in NVRAM 52 space which is accessible by both the IPLROS code which is performing PCI bus initialization and by service processor 50 which is responsible for servicing failure scenarios.

The role of service processor 50 is to identify the type of failure and provide isolation to the faulty component. On the occurrence of a PCI failure during the PCI configuration cycle, the system will checkstop, thus preventing system processor 18 from executing any more instructions. Service processor 50 then interrogates mailbox register 54 to determine if a valid PCI address has been saved therein. If so, service processor 50 uses the architected location code in mailbox register 54 to indicate the physical location of the PCI adapter in the remote I/O drawer that caused the failure.

The present invention is also applicable to other bus types, such as ISA, as those skilled in the art will appreciate.

While a preferred embodiment of the present invention has been described having reference to a particular system configuration, modifications in form and detail may be made without departing from the spirit and scope of the invention as described in the following claims.