Delay circuit

The present invention relates of a delay circuit using charging/discharging of a capacitor and to a device using the delay circuit.

An example of a conventional delay circuit using charging/discharging of a capacitor is shown in FIG. 2 . First, the operation of this delay circuit will be described.

At an initial state, since a switch 1 is turned ON (closed) and a switch 2 is turned OFF (opened), a terminal A to which a capacitor 7 is connected has a potential of (V 1 −V 2 ). In order to start the operation of this delay circuit, a signal is supplied to an input terminal 11 . When the signal enters the input terminal 11 , a control circuit 8 turns OFF the switch 1 and turns ON the switch 2 . A constant current source 12 is connected to the terminal A, and the electric charge of the capacitor 7 also connected to the terminal A is discharged.

When the potential of the terminal A reaches a potential V 3 of a reference voltage 5 , the output of a comparator 9 is inverted. Since it takes some time to discharge, this circuit is used as a delay circuit. Here, a time from the start of the operation of the control circuit 8 to the inversion of the output of the comparator 9 becomes a delay time.

This operation is shown in FIG. 3 . The horizontal axis indicates time, and the vertical axis indicates voltage. At the initial state, although the potential at the terminal A in FIG. 2 is (V 1 −V 2 ), the capacitance is discharged through constant current from a time ta when the signal is supplied to the input terminal 11 , so that the potential at the terminal A is lowered. Thereafter, when the potential at the terminal A reaches the potential V 3 of the reference voltage 5 , the output voltage of the comparator is inverted.

When a capacitance value of the capacitor 7 is C 0 , and a constant current value of the constant current source 12 is I 0 , a delay time T 0 may be represented by the following Equation 1:

T 0 = C 0 ×( V 1 − V 2 − V 3 )× I 0   [Equation 1]

When the capacitance value C 0 is made large or the constant current value I 0 is made small, the delay time can be extended. On the other hand, when the capacitance value C 0 is made small or the constant current value I 0 is made large, the delay time can be shortened.

In the case of the delay circuit using charging/discharging of the capacitor shown in FIG. 2 as the prior art, there are problems as described below.

In the delay circuit described thus far, a problem occurs when the terminal A to which the capacitor 7 is connected is short-circuited to an abnormal voltage such as the potential V 1 . In the case where the terminal A to be connected to the capacitor 7 comes to have a voltage higher than (V 1 −V 2 ), the inverted input terminal of the comparator 9 does not become lower than V 3 . Thus, the output of the comparator 9 is not inverted. This means that the delay is not realized, and the delay time is extended without limit. FIG. 4 shows potentials at this time. The terminal A to which the capacitor 7 is connected, is connected in an abnormal state and has the potential V 1 . Thus, the voltage at the terminal A is always at the potential V 1 , and the output of the comparator 9 is not inverted.

This delay circuit is also used as a protecting circuit or an erroneous operation preventing circuit. For example, in a lithium ion battery, when a voltage becomes too high, there is a risk that it may cause a fire. Thus, an overcharge preventing circuit is provided. The delay circuit can also be used for the overcharge preventing circuit. In addition a delay circuit is also used in a charger for lithium ion batteries to set a charging time (charge stop circuit) and the like. Thus, when the terminal A to which the capacitor 7 is connected as shown in FIG. 1 is short-circuited to a voltage higher than (V 1 −V 2 ), the overcharge preventing circuit or the charge stop circuit does not work, and a very dangerous state occurs. If the delay of the charger does not work, charging is continues permanently, and heat generation of the charger and the lithium ion battery is advanced. This causes a very dangerous state such that a fire or heat generation of the apparatus may occur.

In a circuit provided for protection or improvement of safety, even if a problem occurs, some protection must work. A so-called fail-safe must be realized. In the case of the present invention, it is required that even if the delay time is shortened, an output voltage is inverted and a signal is transmitted to the outside.

In a delay circuit using charging/discharging of a capacitor to set a delay time, there is added a voltage detecting circuit for detecting whether a terminal voltage of the capacitor has exceeded a predetermined voltage range.

FIG. 1 is an explanatory view showing an embodiment of a delay circuit of the present invention.

FIG. 2 is an explanatory view showing a conventional delay circuit.

FIG. 3 is an explanatory view showing the state change of the conventional delay circuit.

FIG. 4 is an explanatory view showing the state change of the conventional delay circuit.

FIG. 5 is an explanatory view showing the state change of an embodiment of a delay circuit of the present invention.

FIG. 6 is an explanatory view showing the state change of the embodiment of the delay circuit of the present invention.

FIG. 7 is an explanatory view showing another embodiment of a delay circuit of the present invention.

FIG. 8 is an explanatory view showing the state change of the other embodiment of the delay circuit of the present invention.

FIG. 9 is an explanatory view showing the state change of the other embodiment of the delay circuit of the present invention.

In a delay circuit using charging/discharging of a capacitor to set a delay time, a voltage detecting circuit for detecting whether a terminal of the capacitor has exceeded a voltage range in which charging/discharging is performed, is added so that the delay time is completed without fail.

An embodiment of this is shown in FIG. 1 and the operation of this delay circuit will be described.

At an initial state, a switch 1 is turned ON (closed), and a switch 2 is turned OFF (opened). A terminal A to which a capacitor 7 is connected has a potential obtained by subtracting a potential V 2 of a reference voltage 4 from a potential V 1 of a power source voltage 3 in advance. In order to start the operation of this delay circuit, a signal is supplied to an input terminal 11 . When the signal enters the input terminal 11 , a control circuit 8 turns OFF the switch 1 and turns ON the switch 2 . It is assumed that comparators 9 and 13 are always turned ON. A constant current source 12 is connected to the terminal A, and the capacitance 7 also connected to the terminal A is discharged.

When the potential of the terminal A reaches a potential V 3 of a reference voltage 5 , the output of the comparator 9 is inverted. Since it takes some time to discharge, this circuit can be used as a delay circuit. Here, the time from the start of the operation of the control circuit 8 to the inversion of the output of the comparator 9 becomes a delay time.

When the capacitance of the capacitor 7 is C 0 , and the constant current value of the constant current source 12 is I 0 , the delay time T 0 may be represented by the following Equation 2:

T 0 = C 0 ×( V 1 − V 2 − V 3 )× I 0   [Equation 2]

Voltage changes at the terminal and the output terminal become the same as those illustrated in FIG. 3 .

Now, consider a case of abnormal operation in which the connection between the capacitor 7 and the terminal A is opened by an external factor. In such an open state, at the same time as the operation of the control circuit 8 , the potential at the terminal A is lowered by the constant current source 12 , and the inverted input terminal of the comparator 9 becomes V 3 of less. By this, the output of the comparator 9 is inverted in a state where there is little delay time. Even in the case where the terminal A to which the capacitor 7 is connected, is short-circuited to an improper wiring line such as by being connected to a ground potential by an external factor, when the control circuit 8 is operated, since the voltage of the terminal A is V 3 or less, the output of the comparator 9 is inverted in a state where there is little delay time, and safety is increased. This is shown in FIG. 5 .

On the other hand, there is a case where the terminal A to which the capacitor is connected, is connected to an abnormal voltage such as a potential higher than (V 1 −V 2 ) by an external factor. In the prior art, in this case, the output terminal voltage is not inverted permanently. In the embodiment of the present invention, this is improved. That is, when the terminal A is connected to a potential V 4 higher than (V 1 −V 2 ), the output voltage is inverted in a state where there is little delay time, and safety is increased.

As specific example, a case where the capacitor 7 is short-circuited to the potential V 1 of the power source will be described.

In this state, when the control circuit 8 starts to operate, since the potential of the terminal A becomes higher than V 4 and higher than (V 1 −V 2 ), the output of the comparator 13 provided in the present invention is inverted. In the state described thus far, there is little delay time and the output voltage of the comparator is inverted. The voltage changes in this example are shown in FIG. 6 .

Another embodiment is shown in FIG. 7 . Although this circuit operates in the same way as the circuit of FIG. 1, connection of capacitance 7 and constant current source 12 is different from FIG. 1 .

At an initial state, a switch 1 is turned ON (closed), and a switch 2 is turned OFF (opened). A capacitor 7 has a potential V 2 of a reference voltage in advance.

In order to start the operation of this delay circuit, a signal is given to an input terminal 11 . When the signal enters the input terminal 11 , a control circuit 8 turns OFF the switch 1 and turns ON the switch 2 . A constant current source 12 is connected to a terminal A, and the capacitor 7 also connected to the terminal A is discharged. When the potential at the terminal A reaches a value obtained by subtracting a potential V 3 of a reference voltage 5 from a potential V 1 of a power source voltage, the output of a comparator 13 is inverted. The voltage changes at this time are shown in FIG. 8 .

When the terminal A to which the capacitor is connected, is connected to a potential lower than V 4 by an external factor or is connected to a potential higher than (V 1 −V 3 ), the output of the comparator 9 or the comparator 13 is inverted in a state where there is little delay time.

In the example of FIG. 1, although the potential of the terminal A is set at the potential of (V 1 −V 2 ) in advance, this potential may be any potential of V 1 to the ground.

Before the voltage of the input terminal is changed, even if the potential of the capacitor is V 1 or the ground potential, the present invention can be realized. This can be also explained by the circuit shown in FIG. 1 . At an initial state, both the switches 1 and 2 are turned OFF. The capacitor 7 has been made to have the ground potential in advance. At this time, all of the switches 1 and 2 , and the comparators 9 and 13 are turned OFF. In order to start the operation of this delay circuit, a signal is given to the input terminal 11 . When the signal enters the input terminal 11 , the control circuit 8 turns ON the switch 1 so that the capacitor 7 is first charged up to a potential of (V 1 −V 2 ). Thereafter, the switch 1 is turned OFF, the switch 2 is turned ON, and the comparators 9 and 13 are put in an operable state. The constant current source 12 is connected to the terminal A, and the capacitor 7 also connected to the terminal A is discharged. When the potential at the terminal A reaches the potential V 3 of the reference voltage 5 , the output of the comparator 9 is inverted. The potential changes of the terminal A voltage and the output terminal at this time are shown in FIG. 9 .

It does not matter if the potential of the capacitor at the initial stage is not VSS. That is as long as the comparator is turned OFF at the initial state, the potential of the capacitor 4 may have any state.

Although the foregoing embodiments have been described, the present invention can be carried out even if input terminals of the comparators or the output logic is assembled in any manner.

The embodiments described thus far can be constructed with a semiconductor integrated circuit. At that time, a capacitance is difficult to be assembled in the integrated circuit, and is connected to the outside. Thus, the present invention displays effectiveness.

According to the present invention, as described above, only a simple circuit is added, such an operation is made that an output potential is changed even at an abnormal time when a capacitance becomes an open state or is short-circuited to a power source voltage potential or a ground potential, so that there are effects that the reliability of the entire apparatus is increased and the safety is improved.