Method for conserving memory storage during an interpolation operation

The commonly owned, patent application entitled: “Processor with Instruction Set for Audio Effects,” U.S. patent application Ser. No. 08/886,920, filed Jul. 2, 1997, now U.S. Pat. No. 5,930,158, issued Jul. 27, 1999, is herein incorporated by reference.

A portion of the disclosure of this patent document contains a computer program listing which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

This invention relates generally to a method for conserving memory space during program execution and more specifically to a method for conserving memory storage within an audio signal processor during an interpolation operation.

Interpolation programs and subroutines are known in the art for providing a gradual transition between two distinct data values, for instance, from a low setting to a high setting. It can be understood that if the difference between the two data values is too great, an instantaneous conversion of the low setting to the high setting results in signal distortion. The interpolation process allows the transition to be made gradually, and by so doing minimizes the signal distortion which may otherwise result from the transition.

Audio signal processors often require interpolation operations to vary the characteristics of audio information. Interpolation may be required between two widely varying values to generate special effects, or to ensure high quality audio performance. If the difference between the two levels is large and changed instantaneously (a process which is referred to as “slamming”), undesirable sound effects such as “pops” or “clicks” can result. Interpolation allows the levels to be changed from one value to the other gradually, thereby reducing or eliminating the occurrence of signal distortion and the unwanted audio effects.

A downside of implementing an interpolation process is that it typically requires additional memory space to store the interpolation commands and additional data needed to perform the interpolation process. Audio processors, as most other signal processors, have limited memory resources. It is therefore desirable to reduce the memory space needed during implementation of interpolation operations while reducing the occurrences of the aforementioned “slamming” effects.

The present invention provides a method for conserving memory storage during the execution of a interpolation operation while simultaneously reducing the occurrence of signal distortion. The method is accomplished in one embodiment using a pool of interpolation commands. When a interpolation operation is requested, it is performed using one of the pooled interpolation commands. If none of the pooled interpolation commands are available, for instance when all are simultaneously active, the interpolation command having the smallest difference between its interpolated value and final value is selected, and its interpolated value converted to its final value. By identifying and converting the data value which is closest to its final value, the aforementioned slamming effects are reduced. The selected interpolation command is then reassigned to interpolate the requested data. The reuse of the pooled interpolation commands saves memory space since an existing command or routine is used to carry out the requested interpolation. The need to allocate memory space to another interpolation command or routine is averted.

The invention will be better understood when considered in light of the following drawings and detailed description.

FIG. 1 illustrates a method for reducing memory storage during the execution of an interpolation operation in accordance with the present invention.

FIG. 2 illustrates an example of a computer system used to perform the method of the present invention.

FIG. 3 illustrates a simplified system block diagram of a typical computer system used to perform the method of the present invention.

An instruction which allows coefficient values to be modified in a controlled fashion is the INTERP instruction, the description and operation of which has been set forth in the above-referenced co-pending patent application entitled: “Processor with Instruction Set for Audio Effects.” The INTERP instruction accomplishes this by calculating a scaled linear interpolation between an two values A and Y, at a specific rate X, using the arithmetic operation shown in equation 1:

A−X(A−Y)→R  (1)

Accordingly, an initial value A is transformed to a final value Y at a scaling rate of X. R represents the interpolated value of A after one interpolation iteration. If R is substituted for A and equation (1) repeated, R becomes a further interpolated value of A, approaching the final value Y. The scaling value X controls the incremental change during each interpolation step. The process may require one or more iterations to complete the interpolation, depending up the scaling value X selected and the difference between the initial and final values A and Y, respectively. In its preferred embodiment, the INTERP instruction requires four memory registers for execution: one register for the INTERP instruction and one register each for storage of the initial, final, and scaling values A, Y, and X, respectively.

FIG. 1 illustrates a method for reducing memory storage during the execution of the interpolation operation. The method is applicable to the aforementioned INTERP instruction as well as other commands, routines, and processes which perform an interpolation operation from an initial value to a final value.

The method begins upon processor startup, at which time N INTERP instructions are pooled and stored into memory (step 120 ). The size of the pool is determined by such factors as the expected number of simultaneously occurring interpolation operations and the amount of memory allocated to interpolation operations. Other factors may include (but are not limited to) knowledge about previous interpolation loads and the processor's total available memory space. In the audio signal processor described in the co-pending patent application, “Processor with Instruction Set for Audio Effects,” N is between 3 and 8 instructions and each instruction is stored within an instruction memory register. In an alternative embodiment, the number of instructions allocated to the pool is dynamic and changes over time in response to light or heavy periods of simultaneously requested interpolation operations.

In the preferred embodiment, step 120 is executed using the following C source code, although other programming languages and/or instructions executing similar operations could be used to perform the same step.

Subsequently at step 130 , the program requests an interpolation operation from an initial value A to a final value Y. Interpolation requests may occur any time after processor start up, for instance, immediately following start up or after a number of intervening programming steps (not shown). Step 130 is executed using the following C source code in the preferred embodiment, although other programming languages and/or instructions executing similar operations could be used to perform the same step.

After the request is made, an interpolation value X is selected for the interpolation operation (step 140 ). In the preferred embodiment, the interpolation value remains constant for all interpolation iterations, although in an alternative embodiment, the interpolation rate may vary over one or more iterations.

This selection of the interpolation value (step 140 ) may also include providing either a single interpolation value to all pooled instructions or separate values to separate instructions. When a single value is used, additional memory registers can be conserved since only one (instead of N) memory register(s) is needed to supply N pooled instructions. If separate values of X are used, additional processing flexibility is achieved. The interpolation value may be held constant or made variable over the entire pool or within instruction subgroups of the pool.

Next at step 150 , an inquiry is made as to whether any of the INTERP instructions have performed a previous operation from the initial value A, i.e., if a previous interpolation has begun from initial value A. This could be the case, for instance, if A has been interpolated to different final value Z. In the preferred embodiment, the immediately preceding operation is queried, although in an alternative embodiment more distant operations may be queried as well. Step 150 is executed using the following C source code in the preferred embodiment, although other programming languages and/or instructions executing similar opeartions could be used to perform the same step.

/* if GPR already being ramped, use this one */

for( pPtr=pHead; pPtr; pPtr=pPtr->pChain ) (

If the answer to step 150 is yes, the final value Z of the previously used INTERP instruction is converted to Y (step 152 ). Upon the conversion of Z to Y (and selection of a interpolation value X), the INTERP instruction is reused to perform the requested interpolation operation (step 154 ). Once the operation is completed, the program counter returns to step 130 to await another interpolation request. The reuse of the INTERP instruction saves at least one memory register since a new INTERP instruction (and accordingly a new memory register) would otherwise be necessary to perform the new interpolation operation. In the preferred embodiment, steps 152 and 154 are executed using the following C source code, although other programming languages and/or instructions executing similar operations could be used to perform the same step.

if( pPtr->inUse && pPtr->gpr==gprAddress ) (

OS_WRITEGPR( ulChipHandle, pPtr->addrGPRy, ulDest );

pPtr->ulDest=ulDest;

OS_RELEASEMUTEX(fx 8210 Mutex);

return FXERROR_NO_ERROR;

)

)

If the answer to step 150 is no, the method inquires if there are any free INTERP instructions within the pool, i.e., are there any INTERP instructions which are not concurrently interpolating any values (step 160 ). If there are, a free INTERP instruction is assigned the initial, final, and interpolation values A, Y, and X respectively, and that instruction begins the interpolation operation (step 165 ). Once the operation is completed, the program counter returns to step 130 to await another interpolation request. As explained above, this operation saves at least one memory register since an existing INTERP instruction is used to carry out the requested interpolation. In the preferred embodiment, steps 160 and 165 are executed using the following C source code sections, respectively, although other programming languages and/or instructions executing similar operations could be used to perform the same step.

If the answer to step 160 is no, a search is performed to select the INTERP instruction having an interpolated value which is closest to its final value. (step 170 ). The interpolated value of the selected INTERP instruction is converted to its final value (step 180 ). The selected INTERP instruction is then reassigned to perform the requested interpolation from the initial value A towards a final value Y at the selected rate X (step 190 ). Once the operation is completed, the program counter returns to step 130 to await another interpolation request.

The reuse of an existing INTERP instruction saves at least one memory register. Moreover, since the difference between the interpolated and final values is, by definition, the smallest of all of the pooled INTERP instructions, it is very unlikely that a conversion therebetween will result in the “slamming” effects described above. As the number of pooled INTERP instructions increases, the conversion becomes even more transparent, further attenuating the possibility of any “slamming” effects. In the preferred embodiment, steps 170 , 180 and 190 are executed using the following C source code sections, respectively, although other programming languages and/or instructions executing similar operations could be used to perform the same step.

In the above described manner, the interpolation process of the present invention uses one less memory register and possibly two less registers if a constant scaling coefficient is used. By pooling and reusing the interpolation commands, 25-50% fewer memory registers are needed, freeing memory storage for other processor operations. Alternatively, a processor employing the described process may be fabricated using a smaller memory array, resulting in a lower cost, higher yield processor.

The described method may be implemented in a multitude of different forms (i.e., software, hardware, or a combination of both) and in a variety of systems to interpolate any type of digital data from an initial value to a final value. In one embodiment, the described method can be implemented as a software program to interpolate audio information in an audio signal processor. In an alternative embodiment, the method may be realized as a software program to interpolate any type of digital data in a computer system.

FIG. 2 illustrates an example of a computer system 210 implementing the described method for conserving memory space during the execution of an interpolation operation. Computer system 210 includes a monitor 214 , screen 212 , cabinet 218 , and keyboard 234 . A mouse (not shown) may also be included for providing additional input/output commands. Cabinet 218 houses a CD-ROM drive 216 or a hard drive (not shown) which may be utilized to store and retrieve digital data and software programs incorporating the present method, and the like. Although CD-ROM 216 is shown as the removable media, other removable tangible media including floppy disks, tape, and flash memory may be utilized. Cabinet 218 also houses familiar computer components (not shown) such as a processor, memory, and the like.

FIG. 3 illustrates a simplified system block diagram of a typical computer system 210 used to execute a software program incorporating the described method. As shown in FIG. 2, computer system 210 includes monitor 214 . Computer system 210 further includes subsystems such as I/O controller 224 , system memory 226 , central processor 228 , speaker 230 , removable disk 232 , keyboard 234 , fixed disk 236 , and network interface 238 . Other computer systems suitable for use with the described method may include additional or fewer subsystems. For example, another computer system could include more than one processor 228 (i.e., a multi-processor system) for processing the digital data responsive to the aforementioned interpolation method. Arrows such as 240 represent the system bus architecture of computer system 210 . However, these arrows 240 are illustrative of any interconnection scheme serving to link the subsystems. For example, a local bus could be utilized to connect the central processor 228 to the system memory 226 . Computer system 210 shown in FIG. 3 is but an example of a computer system suitable for use with the present invention. Other configurations of subsystems suitable for use with the present invention will be readily apparent to one of ordinary skill in the art.

While the above is a complete description of one possible embodiment of the invention, various alternatives, modification and equivalents may be used. For instance, a person skilled in the art will appreciate that the foregoing description is not limited to the use of the aforementioned INTERP instruction. The objectives of the invention can also be accomplished by implementing a sub-routine which is designed to perform an interpolation operation. The interpolation sub-routine may be stored and reused in accordance with the manner described herein to conserve memory space. The present invention is equally applicable thereto by making appropriate modifications to the embodiment described above. Nor is the invention limited to the processing of audio information. Those of ordinary skill in the art will appreciate that the invention is equally applicable to any form of data. Therefore, the above description should be viewed as only one embodiment of the present invention, the boundaries of which is appropriately defined by the metes and bounds of the following claims.