Digital communication system and method

The invention pertains to apparatus and methods for communicating signals between processors in multi-processor systems. More particularly, the invention pertains to such systems wherein the processors communicate with one another via a communications medium as in a local area network.

Communications circuitry for use in multi-processor systems dedicated to monitoring or supervising regions is known. One example is disclosed in Tice et al U.S. Pat. No. 4,916,432 entitled Smoke and Fire Detection System Communication. Another is disclosed in Tice U.S. Pat. No. 5,525,962 entitled Communication System and Method. Both of the noted patents are assigned to the assignee hereof and are hereby incorporated herein by reference.

While known systems are useful and have been effective, it would be desirable to be able to more completely separate data from clock signals during the communication process. Further, it would be desirable to be able to provide a substantially collision free communication environment. Such an environment would be useful in supervision or alarm systems as well as in general purpose local area networks.

A communications apparatus utilizes multi-polarity, representations for clock and data pulses. Clock pulses are transmitted from a source in a first polarity, in a communications medium as voltage pulses. The source transmits clock pulses with a low output impedance. In-between clock pulses, the source switches to a high output impedance.

At least some of the data pulses are transmitted in a second polarity, on the medium, as voltage pulses. Most of the data pulses are bracketed by pairs of clock pulses.

In one aspect data pulses, for example representing a logical “one”, can be transmitted as substantially constant width pulses with logical “zero” being represented by absence of a pulse. Alternately, data can be represented as variable width voltage pulses. A logical “one” can be transmitted with a first width and a logical “zero” transmitted with another width.

In one aspect, where the source corresponds to a common control element, energy can be supplied to a plurality of spaced part units coupled to the medium, at least, when the clock pulses are being generated by the control element. In this embodiment, data can be generated by the control element, with the second polarity or by another of the units coupled to the medium.

In yet another aspect, the control element can provide framing signals for messages along with the clock pulses to synchronize communications on the line.

Further, since the clock signals and the data signals are transmitted with different polarities relative to the medium signal-to-noise characteristics are improved. For example, if the first polarity is opposite the second polarity, the respective detection thresholds can be spaced further apart from one another, i.e., +2.5 volts and −2.5 volts, respectively. Finally, the polarity of a particular pulse also identifies the type of information, clock or data, represented by the pulse.

Other advantages include:

The clocking waveform and the device data waveform will never occur at the same time. This makes it possible to implement a lockout design in the detection circuit that will tend to prevent a false clock or data detection from “ringing” on the line during the driving of the clock and data voltage waveforms.

A device wired backwards will not short out the communication wiring. The system can determine which devices are wired backwards without interference with the devices that are wired correctly. (The system may be able to communicate to such devices without having to correct the wiring under certain conditions).

The ability to differentiate from a low impedance (causing a low voltage on the line) and data.

In order to minimize “ringing and other distortions” on the wiring during communications, an adjustable waveform shape can be driven from the power source for clocking. The “slew rate” or transition rate of the voltage from one level to another can be adjusted to compensate for various wiring configuration. This will tend to minimize distortion of the waveform during communications. This waveform adjustment will be a function of:

propagation times for the signals on the wiring due to lengths and characteristic impedances of the wires,

errors occurring in the communications which is monitored by every device on the loop, and

waveform analysis at a central point, most likely the power source for clocking.

In yet another aspect, bytes of data can be transmitted with single intervening clock signals. Alternately, transmission can be implemented with only a single synchronizing signal followed by a string of data such as one or more bytes.

Collision free communications can be accomplished by having the devices monitor the communication line voltages while they are transmitting. Any mismatch in voltage causes a transmitting device to drop off the line and wait for the next access period to start transmitting again.

Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings.

FIG. 1 is a block diagram of a system in accordance with the present invention;

FIG. 1A is a block diagram of communication line interface circuitry;

FIG. 2 is a block diagram of an electrical unit usable with the system of FIG. 1;

FIG. 3 is a set of timing diagrams illustrating a communications protocol usable with the system of FIG. 1;

FIG. 4 is a more detailed diagram of a communication signal of FIG. 3;

FIG. 5 is a diagram illustrating an alternate form of a communications signal; and

FIG. 6 is a diagram illustrating yet another form of a communications signal.

While this invention is susceptible of embodiment in many different forms, there are shown in the drawing and will be described herein in detail specific embodiments thereof with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the invention to the specific embodiments illustrated.

FIG. 1 illustrates a system 10 which can be used for monitoring a plurality of conditions in one or more regions to be supervised. The system 10 includes a common control unit 12 which could be implemented as one or more interconnected programmed processors and associated, prestored instructions.

The unit 12 includes an interface 12 a for coupling, for example, to a communications medium 14 , illustrated in FIG. 1 for exemplary purposes only as an optical or electrical cable.

Coupled to medium 14 is a plurality of ambient condition detectors 18 and a plurality of control or function units 20 . It will be understood that the relative arrangement of the members of the pluralities 18 and 20 relative to the medium 14 is not a limitation of the present invention. The unit 12 can communicate with members of the pluralities 18 or 20 , or these members can communicate among themselves using a protocol to be discussed subsequently.

The members of the plurality 18 can include intrusion sensors, position sensors, gas sensors, fire sensors such as smoke sensors, thermal sensors or the like, and gas sensors, all without limitation. The members of the plurality 20 can include solenoid actuated control or function implementing units, display devices, printers or the like.

Also coupled to the control unit 12 via a medium 24 , illustrated for example as a pair of electrical cables, is a plurality 26 of alarm indicating output devices. These could include audible or visible output devices without limitation, speech output devices and the like. The devices 26 are intended to broadcast a message, which might indicate alarm conditions, in one or more predetermined regions.

FIG. 1A illustrates additional details of interface 12 a. The interface includes frame/clock drive circuitry 12 b which is coupled to controllable switches 12 c - 1 , - 2 . Switches 12 c - 1 , - 2 provide a short circuit path, when closed, around relatively high impedance elements R 1 and R 2 . Data drive circuitry 12 d, data receive circuitry 12 e and clock receive circuitry 12 f are all coupled across communication link 14 .

Interface 12 a receives control signals from control element 12 g which could be implemented with a programmed processor, associated preprogrammed instructions and interface circuits. It will also be understood that element 12 g could receive via link 14 , or any other selected input additional instructions, programs or data which could be stored therein for later execution or analysis, respectively.

In over-all operation, interface 12 a via driver 12 b provides framing and clock signals of a first polarity at a time when switches 12 c - 1 , - 2 are in a short circuit or closed state thereby presenting a low output impedance to the link 14 . The clock receive circuitry 12 f detects signal levels associated with clock pulses. It will be understood that the frame and clock signals impressed on the link 14 are voltage signals of a predetermined amplitude, for example 24 volts and 5 volts, respectively.

Interface 12 a will switch to a high impedance output state, switches 12 c - 1 , - 2 effectively being open circuited, at a time when drive circuitry 12 b is effectively outputting a zero volt signal. During this time interval data from units in pluralities 18 or 20 can be coupled to medium or link 14 with a second or different polarity, which could be opposite of the first polarity and received in data receive circuitry 12 e. Alternately, during these time intervals interface 12 a can transmit data via data drive circuits 12 d to the members of the pluralities 18 or 20 .

Data receive circuitry 12 e includes one or more latches which retain data from the link 14 until reset. If a single latch is used, when the drive circuitry 12 b sends the next clock pulse, that data latch can be reset. Resetting takes place when clock receiver circuitry 12 f detects the next clock pulse. The final data value is retained in the storage element in receiver 12 e and is reset at the start of the next frame. Where a plurality of data latches is provided, they could be reset simultaneously using a frame end signal.

FIG. 2 illustrates an exemplary electrical unit 30 usable with the system 10 . The electrical unit 30 could, without limitation, correspond to a member of the plurality of detectors 18 . In this instance, the unit 30 would incorporate an appropriate sensor 32 a, illustrated in phantom. Alternately, the unit 30 could correspond to a member of the plurality of function modules 20 . In this instance, the unit 30 would include output function implementing circuitry 32 b illustrated in phantom.

The unit 30 would also include control circuitry 34 . The circuitry 34 could be implemented using one or more programmed processors in combination with other hardwired logic circuits.

The unit 30 also includes a power supply 36 which, is illustrated in FIG. 2, could receive electrical energy from the communications medium 14 . That energy could in turn be made available to the components of the unit 30 . Alternately, the unit 30 could contain a power supply energized via a battery or another source without limitation.

Unit 30 also includes an interface circuitry indicated generally at 38 . The interface circuitry 38 facilitates bidirectional communication with communication signals on the medium 14 . For purposes of communicating with the common control unit 12 , any other member of the plurality 18 or the plurality 20 detection circuits 38 a, 38 b and 38 c are also provided.

In accordance with the communications protocol provided on the medium 14 , clock detection circuitry 38 a detects those signals which have a first polarity relative to the communications medium 14 . Threshold detection circuitry 38 b detects those electrical signals which exhibit a second or opposite polarity relative to the medium 14 . Circuitry 38 c detects message framing signals.

Those signals detected by threshold circuitry 38 a, clock pulses in accordance with the communications protocol system 10 , can be presented on a line 40 a to the control element 34 . Additionally, those signals detected by circuitry 38 b, in accordance with the protocol of the system 10 , can be presented as data pulses on a line 40 b. Control element 34 is also able to communicate via a line 40 c and interface circuitry 38 with either the common control unit 12 or members of the plurality 18 or 20 without limitation.

Control circuitry 34 can also include data input/output comparison circuitry 34 a. Circuitry 34 a can be implemented in whole or in part using hardwired or programmed circuitry.

It will be understood that one use of the protocol herein is being discussed with respect to the system 10 . However, the purpose or function of the system 10 is not a limitation of the present invention. The present protocol could be used with any distributed unit communication system without departing from the spirit and scope of the present invention.

FIG. 3 is a set of timing diagrams which further illustrates the communication protocol. A voltage signal 50 can be impressed upon the communications medium 14 by either control unit 12 or, if desired, one of the members of the pluralities 18 or 20 .

The waveform 50 provides a message framing signal bounded by transitions 50 a, indicating a message start and 50 b indicating a message termination. Between message intervals, waveform 50 , relative to the medium 14 , exhibits a relatively high DC voltage level.

During inter-message intervals, waveform 50 c could be coupled to the medium 14 via a power supply in unit 12 with a low output impedance. If desired, electrical energy can be supplied from the control unit 12 to the members of the pluralities 18 and 20 during these time intervals.

Interface circuitry 38 c, for example in exemplary unit 30 , is able to detect the start of a message indicated by framing signal 52 . During a message frame, the voltage on medium 14 exhibits a relatively low value between message start transition 50 a and message end transition 50 b.

During the frame time interval, indicated by waveform 52 , line 40 d, the output power supply in the control unit 12 or any other unit which is providing framing signals must be capable of switching between high and low impedance states. As illustrated in waveform 50 , the unit which is supplying synchronization signals which include the framing transitions 50 a, 50 b also provides a plurality of spaced apart voltage clock pulses indicated generally at 54 . Clock pulses are transmitted on the medium 14 by output circuitry 12 a with a low output impedance as discussed above.

During the time interval that each of the clock pulses is present on the medium 14 , energy is also being supplied to those units, such as a unit 30 which have a power supply, such as power supply 36 coupled to the medium 14 . The clock pulses 54 are all coupled to the medium with a first or positive polarity.

Between clock pulses, the synchronizing device assumes a high output impedance state. Other units, such as the common control unit 12 or members of the pluralities 18 or 20 can transmit voltage-type data pulses 56 on the medium 14 to be received by other members of the pluralities 18 and 20 as well as the control unit 12 . During data intervals, those devices coupled to the medium 14 which are not transmitting data assume a high impedance state and can receive those data pulses. The data pulses 56 are transmitted on the medium 14 with a polarity which is different, or opposite, to the polarity of the clock pulses 54 .

Impressing clock pulses on the medium 14 with a different polarity than that of the data pulses results in maximizing the receiving units'ability to separate clock and data pulses reliably. Since in the present protocol, clock signals and data signals are presented with different polarities, separation of the clock and the data can be carried out readily.

The detected polarity will determine which signals represent clock pulses and which signals represent data pulses. Additionally, the clock signals and the data signals, in accordance with the present protocol, will always occur at different time intervals. This contributes to an increased signal to noise ratio of the present system in that false clock signals or data signals resulting from ringing on the medium 14 can be rejected if the polarity of the noise signal does not correspond to the polarity of an expected clock or data signal.

The detected clock signals, present on the line 40 a, and the displaced data signals, present on the line 40 b, can then be coupled to control element 34 for processing at the unit 30 . Alternately, the control unit 34 can generate a string of data pulses on the line 40 c which can be transmitted via the medium 14 in-between clock pulses 54 .

FIG. 4 is a graph which illustrates further details of the signal 50 of FIG. 3 . As illustrated in FIG. 4, the signal 50 exhibits a frame start/frame end threshold 60 , detectable in framing threshold detection circuitry 38 c. Signal 50 also exhibits a clock threshold 62 which can be used to detect the presence of the plurality of clock signals 54 via circuitry 38 a.

A third threshold 64 functions to distinguish between a first polarity exhibited by the framing signals and the clock signals and a second, preferably opposite, polarity exhibited by a plurality of data signals 56 . In one embodiment, where binary values are being transmitted via the medium 14 , the presence of opposite polarity voltage pulses 56 could, for example, be indicative of the presence of logical 1 . Logical zeros could be represented by an absence of the opposite polarity signals 56 as indicated at 56 - 1 , FIG. 4 .

Alternately, logical “one” signals can be transmitted as pulses 56 of a predetermined width. Logical “zero” can be transmitted, as indicated in phantom at 56 - 2 , with a different width but of the same polarity as the pulses 56 .

In addition, a stabilizing time interval T can be provided after frame start transition 50 a and before a message starts such as before a data bit, such as 56 - 1 , is transmitted. The stabilizing interval T can have a duration of less than 5 Msec, preferably in a range of 2-3 Msec.

Collision free communications can be enhanced by having the members of the pluralities 18 and 20 monitor the medium 14 when each respective device is carrying out a transmit operation. Detected voltage mismatches between the respective unit's intended communications sequence and that which is detected on the medium can cause the respective device to cease transmission and wait for the next framing interval to re-initiate transmission.

Circuitry 34 a can compare a sequence of data output signals on line 40 c to respective signals actually present on the medium 14 as detected by threshold circuitry 38 b. Where a given data output pulse sequence differs from a pulse sequence present on the medium 14 , that difference indicates to the respective electrical 30 that at least one other unit is attempting to communicate at the same time via medium 14 .

Since a transmitting electrical unit transmits a voltage pulse, such as the pulses 56 with a low impedance output, the presence of one or more of those pulses on the medium 14 will override any respective output signals from other electrical units corresponding to, for example, a logical zero, 56 - 1 which are output via the respective electrical unit with a high impedance output state. Thus, the electrical unit which detects the mismatch can terminate communication temporarily until it detects a subsequent frame start signal and perhaps an associated command which will authorize further transmission on the medium 14 .

The above described voltage drive protocol minimizes noise or losses due to leakage in the transmission medium 14 . This would include leakage in conductive cables, wires or other sources of shunt impedance which might be present or cross the lines and not related to data transmission. By way of example, if the high level output impedance of the interface 12 a corresponds to something on the order of 2000 ohms, since a transmitting electrical unit transmits at a very low output impedance state, even a shunt on the order of 100 ohms will not interfere with communications of data on the medium 14 .

Thus, using the above-described protocol members of the plurality 18 can communicate information to members of the plurality 20 during message frames generated for example by common control unit 12 . Alternately, and without limitation, the framing signals and clock pulses could be generated by any other electrical unit coupled to the medium 14 .

It will be understood that neither the contents of the messages being transmitted nor the detailed circuitry of the members of the pluralities 18 or 20 are limitations of the present invention. It will also be understood that, if desired, the control unit 12 could, but need not, be the primary source of framing and clock signals in the system 10 . In such an instance, the members of the pluralities 18 and 20 could communicate among themselves without directly communicating with the common control unit 12 but still operate within a synchronizing scheme established by that common control unit.

FIG. 5 illustrates an alternate communication protocol exemplified by waveform 70 . Waveform 70 includes a frame interval 70 a bounded by a preframe voltage level 70 b and a postframe voltage level 70 c. During the preframe and postframe intervals, signals 70 b, 70 c provide energy to the pluralities of the devices such as devices 18 and 20 .

Message frame 70 a is defined by a frame start transition 72 a and a frame ending transition 72 b. Subsequent to frame start transition 72 a, a stabilization time T′ is provided. During this time interval between frame start transition 72 a and any subsequent message or messages, any residual currents on the communication link 14 have an opportunity to dissipate or decrease to a level that will not interfere with communication of subsequent messages.

In the protocol of FIG. 5, a plurality of bytes 74 a, 74 b and 74 c are serially transmitted between an end of the stabilization interval T′ and frame end transition 72 b. For synchronization purposes, interbyte clock pulses 76 a and 76 b are transmitted on the medium with a polarity opposite the polarity of the data pulses corresponding to a logical “one”. Data signals corresponding to a logical “zero”, as illustrated in FIG. 5, are transmitted at a level 3 amplitude.

During the stabilization time interval T′ as well as during the clock pulses 76 a, 76 b, the source switches to a relatively low output impedance. The source then switches to a high impedance mode between clock signals thereby enabling communicating devices, such as members of the pluralities 18 and 20 to impress data signal voltage-type pulses on the link 14 with a polarity opposite that of the polarity of the clock signals.

FIG. 6 illustrates via a waveform 80 an alternate communications protocol. Waveform 80 includes a message frame interval 80 a which is bounded by a preframe level 80 b and a postframe level 80 c. During the intervals where the levels 80 b, 80 c are present, power can be supplied via medium 14 to the members of the pluralities 18 and 20 .

Frame 80 a is bounded by frame start transition 82 a and a frame end transition 82 b. Subsequent to frame start transition 82 a, a stabilization time T″ is provided, corresponding to the stabilization time interval T′ discussed previously.

Unlike the protocol of FIG. 5, the protocol of FIG. 6 does not incorporate clock signals as previously discussed in FIGS. 4 and 5. Instead, at the end of stabilization interval T″, a data start signal S can be detected followed by an initial byte of information, a sequence of binary one and binary zero representations. Subsequently, an interbyte interval B is provided. Interval B is followed by another start signal S and a second byte of information represented by binary one and binary zero representations. After yet another interbyte interval B and another start signal S, a third byte of information can be transmitted in the same frame. The third byte is terminated by the frame end transition 82 b.

Those of skill in the art will understand that the frame start transition 82 a and the frame end transition 82 b can be used as an alternate to having the clock signals 76 a, 76 b of the waveform 70 of FIG. 5 . In this instance, frame start transition 82 a could also enable a local clock of an appropriate frequency for clocking data signals.

From the foregoing, it will be observed that numerous variations and modifications may be effected without departing from the spirit and scope of the invention. It is to be understood that no limitation with respect to the specific apparatus illustrated herein is intended or should be inferred. It is, of course, intended to cover by the appended claims all such modifications as fall within the scope of the claims.