Receiving latch with hysteresis

This invention is related to circuits, and particularly to CMOS circuits for use in computers where has been a need for a receiver and a latch which is fulfilled by our hysteresis latch circuit.

In the past circuits for use in computers there has been a need for a receiver and a latch for setting a hysteresis for a circuit.

Our invention provides a circuit which eliminates elements of prior art circuits and provides a hysteresis latch.

These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.

FIG. 1 shows our preferred embodiment of a hysteresis latch in the environment where it can be used.

Before considering our preferred embodiments in detail, it will be understood the the receiving latch with hysteresis circuit we developed is useful in receiving data on cross chip boundaries in a chip to chip interface. FIG. 1 which illustrates our preferred embodiment also illustrates a typical latch which can be seen to differ from our hysteresis latch circuit which is implemented in CMOS. The abbreviation here PFET is used to refer to a p channel field effect transistor device. NFET is used to refer to an n channel field effect transistor device. In todays technology PFETS are normally non-conducting between the source electrode and drain electrode when the gate-to-source potential is relatively negative, an opposite condition from that obtained from an NFET device's relative biasing.

Turning now to our invention in greater detail, it will be seen from FIG. 1 which illustrates our preferred embodiment that our hysteresis latch is a new circuit which combines the function of a traditional receiver and latch, essentially eliminating elements of the latch while providing the receiver function as a hysteresis latch combination. In our preferred embodiment our hysteresis latch provides output to an L 2 latch at the interface from our hysteresis latch. Also, In the example shown, the hysteresis latch can be coupled to receive a scannable input from a test input having an A clock for loading test vectors into the latch. This is but one example where our latch can be used.

In the illustrated embodiment a data path beginning with data input D allows the passage of information from the input pad D to the L 1 node where it is available as output.

In order to illustrate in more detail, FIG. 1 illustrates typical circuits which could employ our hysteresis latch in an L 1 , L 2 latch arrangement for clocking data to an output of L 2 at the L 2 pad of the B clock circuit generally illustrated at 12 . Other than the fact that the L 1 out node of our preferred hysteresis latch 11 is common to the circuits along the data path, B clock circuit 12 does not use our hysteresis latch. Neither does the A clock circuit 13 . However, the B clock circuit 12 does illustrate how a typical latch circuit is normally configured in the art and this typical latch will use an eliminated PFET 128 and an eliminated NFET 129 which are not employed in the hysteresis latch section 40 of the receiving hysteresis latch circuit 11 which includes a feed section 20 , a clock section 30 and the hysteresis latch 40 section.

The hysteresis latch circuit 11 has a receiver data input D providing data along the data path from input D to the output node L 1 . An active high level data line clock voltage is indicated by a positive-going clock signal voltage, while an active low level data line clock level is indicated with a negative going clock signal. As the receiver enable pin E is settable to a high or low voltage level, it is respectively turning the hysteresis latch section ON or OFF while providing the initial input to the dataline. Clocking is supplied for the hysteresis latch circuit by a clock, in this illustration it is supplied by the C clock. A C clock high level turns the hysteresis latch section pass gate 114 ON, enabling the hysteresis path. The receiver hysteresis latch section consists of a dataline input to pass gate 114 , (C) clock couplings to the pgate and ngate of PFET 114 ′ and NFET 114 ″ transistors of the pass gate 114 , whose drains are coupled to ground and whose sources pass the data line information to the drain of a latch PFET 117 and the source of an latch NFET 118 at a node of the dataline to latch and gate the dataline information out of the latch from the gates of PFET 117 and NFET 118 respectively to the output node L 1 of the receiving latch with hysteresis when used for cross chip boundary interface connections. A low level zero on the data input pad D turns the data input PFET 115 ON, raising the data input node DN output of the feed section 20 to a high level (and passing through the pass gate 114 ) and turns ON inverter 116 of the hysteresis section of the latch which turns ON latch PFET 117 and turns OFF latch NFET 118 . As voltage on the input pad D begins to rise, input gate PFET 115 turns OFF which turns OFF input gate NFET 119 (when receiver section NFET 120 is on) forming a path of contention through pass gate 114 with the latch PFET 117 . As the threshold voltage on the data input D pad's node DN falls to a low level through pass gate 114 and inverter 116 this turns OFF latch PFET 117 while turning ON latch NFET 118 . When Clock goes low turning OFF the pass gate 114 data is latched at node L 1 .

On the other hand in this illustration, when C clock is high turning ON pass gate 114 and data at pad D is in a high state this turns OFF data input gate threshold PFET 115 and ON NFET 119 bringing node DN low through pass gate 114 and through inverter 116 having a PFET 116 ′ and NFET 116 ″ connected as shown with the data line connected to their gates respectively and the PFET 116 ′ drain connected to the output node L 1 and the NFET source connected to the output node L 1 turning latch PFET 117 OFF and latch NFET 118 ON. As data on data input pad D begins to fall, turning data input gate threshold PFET 115 ON, this creates a contention path through pass gate 114 with NFET 118 . At the receiver down level threshold PFET 115 turns ON completely and NFET 119 turns OFF bringing node DN high through pass gate 114 and through inverter 116 turning PFET 117 ON and NFET 118 OFF. Then when the (C) clock goes low data is latched in node L 1 .

While we have described our preferred embodiments of our invention, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first disclosed.