Method for etching low K dielectric layers

The present invention relates to a process for etching dielectric layers on a substrate.

Dielectric material, such as silicon dioxide, silicon nitride, or TEOS deposited glass, is used in integrated circuits to electrically isolate active devices or features formed on a semiconductor substrate. For example, a layer of dielectric material can be used to electrically isolate electrically conductive interconnect lines that electrically connect active devices on the substrate. It is often necessary to etch through these dielectric layers to form holes or “vias” into which conducting material is deposited to make vertical interconnection or “contact plugs.” To etch the dielectric layer, a mask layer of an etch-resistant material is deposited on the dielectric layer and patterned using conventional photolithographic methods to conform to a desired pattern of holes. In conventional etching processes, the dielectric layer is typically etched in a process chamber using a plasma of etchant gases. For example, a silicon dioxide layer is etched by a plasma of fluorine-containing gas that reacts with silicon in the dielectric layer to form volatile SiF x species. Suitable fluorine-containing gases include, for example, CHF 3 , CH 3 F, CF 4 , and CH 2 F 2 . In addition, the etchant gas contains passivating gases that combine with other vaporized gaseous species to form passivating deposits on the freshly etched features to provide anisotropic etching of the features.

The demand for faster integrated circuits in recent years has produced higher circuit densities and operating frequencies or clock speeds, resulting in the need for dielectric materials having a low dielectric constant (low K); i.e., in current semiconductor fabrication terminology, a low K material is a material that has a dielectric constant of less than about 3.2 which is the dielectric constant of silicon oxide, and more preferably from about 2.5 to 3.2. In high density integrated circuits, the metal interconnect lines are positioned closer together and carry voltages at higher frequencies. The relatively high dielectric constants of conventional dielectric materials allow polarization of the dielectric layer and crosstalk between the interconnect lines. Thus materials having low K are necessary to reduce capacitive coupling between interconnect lines in order to use the highest possible operating frequencies. New low K dielectric materials typically comprise organic polymers such as benzocyclobutene, parylene, polytetrafluoroethylene, polyether, or polyimide. In addition, low K dielectric materials often include small amounts of other materials, such as elemental silicon or silicon-containing compounds, for example Si, SiO 2 , or Si 3 N 4 to provide increased thermal stability and adhesion to a variety of metals and oxides.

As with the silicon oxide materials, the low K dielectric materials are also etched using a plasma of a fluorine-containing gas, especially low K dielectric materials which contain silicon, such as benzocyclobutene, because the fluorine plasma readily reacts with the silicon-containing dielectric. However, it is difficult for the fluorine-containing gas compositions to provide both a high etch rate and a high etching selectivity ratio. By etching selectivity ratio it is meant the ratio of the rate of etching of the low K dielectric layer to the rate of etching of the overlying mask layer (which is typically silicon dioxide), or an underlying silicon-containing layer, such as silicon, polysilicon layer, or titanium silicide. Tailoring the gas composition to provide a high etch-rate often results in a low etching selectivity ratio, and vice versa. Modern integrated circuits typically require etching selectivity ratios of greater than 5:1 with respect to the mask layer, and 15:1 or greater with respect to adjacent and underlying silicon-containing layers such as polysilicon, WSi x , and TiSi x . The low selectivity ratio of conventional etching techniques, using fluorine-containing gases, make it especially difficult to anisotropically etch features having high aspect ratios, such as vias, in low K dielectric layers. Furthermore, fluorine-containing gases erode the process chamber, for example, highly reactive atomic fluorine species react with aluminum in process chambers to form volatile aluminum fluoride species, such as AIF x . Thus it is desirable to have an etching process for etching low dielectric materials that is absent fluorine and that provides high etch rates and a high etching selectivity ratio.

Another problem with conventional processes for etching low K dielectric material is that the etching processes fail to maintain the critical dimensions of etched features, which are the predefined dimensions of the etched features used to determine their electrical properties in the design of integrated circuits. In modern integrated circuits, the line widths of interconnect lines and diameters of contact plugs are becoming increasingly smaller to levels below 0.25 microns, to accommodate higher circuit densities. Because the electrical resistance of these features is proportional to the cross-sectional area of the etched features, it is important to maintain consistent and uniform dimensions without variations across an etched feature or between different etched features. Tapering cross-sectional profiles, that vary as a function of the spacing between the features or other variations in the profile of the features, are not acceptable. The critical dimensions are typically measured as a ratio or difference between the width W r of the mask or resist features and the width W e of the resultant etched features. The closer the two widths, the more predictable and reliable are the electrical properties of the etched features.

Another problem with conventional etching processes arises from excessive deposition of the passivating or other etchant deposits on the etched features or holes in the dielectric layer. These passivating deposits must be removed prior to filling the etched holes with electrically conductive material. While the precise composition of the passivating deposits depends upon the vaporized species in the process gas, the material being etched, and the mask or resist layer applied on the substrate, the passivating deposits typically consist of polymeric material. Because of their chemical composition, the passivating deposits are often difficult to remove without further etching or damaging the low K dielectric material. Thus it is desirable to have an etching process for etching a low K dielectric material that removes the passivating deposits while etching the substrate.

Yet another problem arises because it is difficult to form interconnect lines and vias in a low K dielectric layer by conventional processes, such as for example, a dual damascene method. A dual damascene process is a multilevel interconnect fabrication process in which a dielectric layer is etched to form first voids for fabricating vias that connect different levels of interconnecting lines, and second voids to fabricate interconnect lines. After the first voids are etched, the voids are filled with a sacrificial material, such as a photoresist comprising an organic polymer, which is resistant to the etchant gas. Then, the dielectric layer is etched a second time to form second voids for the interconnect lines which overlie the first voids. Thereafter, the sacrificial material is removed from the first voids, by dipping the substrate in an etchant solution. The first and second voids for the vias and lines are filled with metal in a single metallization step. However, when a low K dielectric material is used for the dielectric layer, it is difficult to use conventional dual damascene techniques because the same etchant solution that removes the sacrificial material will also often remove the low K dielectric material because both materials are organic polymers.

Accordingly, there is a need for an etching process for anisotropically etching low K dielectric material that provides a high etching rate and etching selectivity ratio relative to the overlying mask layer or underlying silicon-containing layer. It is desirable for the etching process to leave little or no passivating deposits on the substrate after etching is completed. It is also desirable that the etching plasma be absent fluorine-containing gas which erodes the process chamber. There is a further need for a process for forming low K dielectrics layers by a conventional dual damascene process.

This invention provides a method for etching a dielectric layer on a substrate, such as a silicon-containing organic dielectric layer, to provide a high etching selectivity to an overlying mask. The method comprises the steps of (i) placing a substrate having a dielectric layer covered by a mask of silicon oxide or silicon nitride into a process zone, (ii) providing in the process zone, an energized process gas comprising oxygen to etch the dielectric layer on the substrate substantially without etching the patterned mask layer of silicon oxide or silicon nitride. Preferably, the process gas introduced into the process zone is substantially absent a fluorine-containing gas. More preferably, the process gas further comprises a non-reactive gas, such as nitrogen, argon, xenon, neon, krypton, or helium, in a volumetric flow ratio of oxygen to non-reactive gas sufficiently high to etch the dielectric layer at an etch rate at least about 500 nm/minute and an etching selectivity of the dielectric layer to the mask of at least about 15:1. Most preferably, the is directed to etching a silicon-containing organic dielectric layer having a dielectric constant of less than about 3.0. Suitable organic dielectric layers are composed of a polymer comprising one or more of benzocyclobutene, parylene, polytetrafluoroethylene, polyether, or polyimide.

In another aspect, the present invention is directed to a method suitable for forming interconnect plugs in a dielectric layer on a substrate. In this method, a substrate having a dielectric layer and an overlying first mask is placed in a process zone. Using the etching process of the present invention, first voids are formed in the dielectric layer. The first voids are then filled with a sacrificial material that is etched at the same or lower rate than the material of the dielectric layer. The dielectric layer is etched a second time to form second voids for the interconnect lines, which overlie the first voids formed for the vias. Thereafter, the sacrificial material is removed from the first voids by dipping the substrate in a stripper solution. Then the first and second voids are filled with metal in a single metallization step to form interconnect plugs and interconnecting lines.

These and other aspects, features and advantages of this invention will become better understood by the following drawings, description, and appended claims which illustrate the examples of this invention:

FIG. 1 is a schematic sectional view of a process chamber suitable for practicing the etching process of the present invention;

FIG. 2 is a schematic of a partial molecule of benzocyclobutene;

FIG. 3 a is a schematic in vertical cross-section of a patterned photoresist layer and hard mask layer over a low K dielectric layer covering electrically conductive interconnect lines on a substrate;

FIG. 3 b is a schematic in vertical cross-section of the substrate of FIG. 3 a after etching of the low K dielectric layer showing a substantially anisotropically etched first void for forming a via;

FIG. 3 c is a schematic in vertical cross-section of the substrate of FIG. 3 b showing a patterned photoresist layer for forming a second void over the first void, and showing the first void filled with a sacrificial material;

FIG. 3 d is a schematic in vertical cross-section of the substrate of FIG. 3 c after etching of the low K dielectric layer showing a substantially anisotropically etched second void for forming an interconnect line;

FIG. 3 e is a schematic in vertical cross-section of the substrate of FIG. 3 d after removing remnant sacrificial material;

FIG. 3 f is a schematic in vertical cross-section of the substrate of FIG. 3 e after filling first and second voids with metal to form vias and interconnect lines;

FIG. 4 is a graph showing the change in the etch rate and etch rate uniformity of the low K dielectric layer across a substrate when etching vias and interconnect lines as a function of helium backside cooling, RF power, magnetic field strength, and the volumetric flow ratio of O 2 to N 2 ;

FIG. 5 a is a graph showing the etch rate of the low K dielectric layer as a function of the volumetric flow rate of O 2 ;

FIG. 5 b is a graph showing the sidewall angle of features etched in the low K dielectric layer as a function of the volumetric flow rate of O 2 ; and

FIG. 5 c is a graph showing the etch rate and etch rate uniformity of the low K dielectric layer across the substrate when etching a 0.25 μm trench as a function of helium backside cooling, RF power, magnetic field strength, and the volumetric flow ratio of O 2 to N 2 .

The etching process of the present invention is useful for anisotropically etching a low K dielectric layer 10 on a substrate 15 with a high etch rate and a high etching selectivity ratio. The substrate 15 can be made of any material including glass, ceramic, metal, polymer, or semiconductor material, such as silicon or gallium arsenide. Preferably, the low K dielectric layer 10 comprises an organic polymer material having a low dielectric constant, such as benzocyclobutene, parylene, polytetrafluoroethylene, polyether, polyimide, or mixtures thereof. More preferably, the low K dielectric layer 10 comprises an organic polymer material having a low dielectric constant, and including small amounts of other materials to provide increased thermal stability and/or adhesion to a variety of metals and oxides. For example, a silicon-containing organic polymer material having a low dielectric constant, such as benzocyclobutene. By silicon-containing it is meant that the organic polymer material contains elemental silicon or silicon compounds, such as Si, SiO 2 , or Si 3 N 4 .

Low K dielectric layers 10 comprising an organic polymer material are generally fabricated from high viscosity fluids consisting essentially of an organic polymer-precursor suspended in a solvent base. For example, CYCLOTENE® manufactured by Dow Chemical Company comprises the organic polymer benzocyclobutene, which has a dielectric constant of about 2.4 and is suspended in a solvent. The fluid polymer-precursor is applied on a substrate 15 using a conventional spin coating apparatus to form a low K dielectric layer 10 comprising an organic polymer. The thickness of the low K dielectric layer 10 is adjusted by varying the volume of polymer dispensed on the substrate 15 , the speed at which the substrate 15 is spun, or the spinning time. The polymer layer on the substrate 15 is then cured in a vacuum oven and a low pressure and/or high temperature to evaporate the solvent carrier and cross-link the polymer.

An overlying layer of etch resistant material is deposited over the low K dielectric layer 10 . Typically, the etch resistant layer comprises a hard mask layer 20 of silicon oxide, silicon nitride, silicon oxy-nitride, sputtered silicon, amorphous silicon, or amorphous carbon. The hard mask layer 20 is deposited directly over the low K dielectric layer 10 by any conventional means including plasma enhanced vapor deposition, chemical vapor deposition, and physical vapor deposition. In a preferred embodiment, the hard mask layer 20 comprises a layer of silicon dioxide deposited by CVD to a thickness of about 0.1-0.3 μm.

The hard mask layer 20 is patterned and etched to define the features to be etched in the low K dielectric layer 10 using conventional photolithographic processes. In conventional photolithographic processes, a photoresist, such as RISTON®, manufactured by duPont de Nemours Chemical Company, is applied on the hard mask layer 20 , and the features to be etched, such as holes or voids for form vias, are defined by exposing the photoresist layer 25 to a pattern of light through a reticle corresponding to the desired configuration of features. The light exposed photoresist layer 25 is treated using a developer and the unexposed photoresist removed to uncover portions of the hard mask layer 20 . Thereafter the hard mask layer 20 is etched using conventional etching processes, such as a plasma or energized process gas comprising a fluorine-containing gas, to expose portions of underlying low K dielectric layer 10 .

In the present process, the low K dielectric layer 10 on the substrate 15 is etched in a process chamber 30 , such as for example, a DIELECTRIC ETCH MxP+ CENTURA chamber, commercially available from Applied Materials Inc., Santa Clara, Calif., as shown in FIG. 1 . The particular embodiment of the process chamber 30 shown herein, suitable for processing of semiconductor substrates 15 , is provided only to illustrate the invention, and should not be used to limit the scope of the invention. Other process chambers capable of energizing a process gas, for example an IPS chamber, also available from Applied Materials Inc., can also be used.

To perform the process, the process chamber 30 is evacuated to a pressure of less than about 1 mTorr, and a substrate 15 is transferred to a process zone 35 of the process chamber 30 from a load lock transfer chamber (not shown), that is also at vacuum. Preferably, the process zone 35 comprises a volume of at least about 5,000 cm 3 , and more preferably from about 10,000 to about 50,000 cm 3 . The substrate 15 is placed on a support 40 and held in place during the etching process using a mechanical or electrostatic chuck 50 having a receiving surface with grooves 55 in which a coolant gas, such as helium, is held to control the temperature of the substrate 15 .

Process gas is introduced into the process chamber 30 through a gas distributor 60 peripherally disposed about the substrate 15 , and the process chamber 30 is maintained at a pressure ranging from about 1 to about 1000 mTorr, and more typically from 10 to 300 mTorr. An electric field is coupled to the process gas in the process zone 35 to energize the process gas (i) inductively by applying an RF current to an inductor coil 65 encircling the process chamber 30 , (ii) capacitively by applying an RF current to a cathode electrode 63 in the support 40 and sidewalls 45 of the process chamber 30 being electrically grounded to serve as an anode electrode, or (iii) both inductively and capacitively. In reactive ion etching (RIE) processes, the process gas is typically energized by capacitively coupling an RF voltage at a power level of from about 100 to about 2000 Watts to the cathode electrode 63 , and by electrically grounding the anode electrode. Alternatively, an RF current at a power level of from about 750 Watts to about 2000 Watts can be applied to an inductor coil 65 to inductively couple energy into the process chamber 30 to energize the process gas in the process zone 35 . The frequency of the RF current applied to the process electrodes or inductor coil 65 is typically from about 50 KHZ to about 60 MHZ, and more typically about 13.56 MHZ.

The plasma or energized process gas is enhanced using electron cyclotron resonance or magnetically enhanced reactors, in which a magnetic field generator, such as a permanent magnet 70 or electromagnetic coils, is used to apply a magnetic field to the plasma in the process zone 35 to increase the density and uniformity of the energized process gas. Preferably, the a magnetic field comprises a rotating magnetic field with the axis of the field rotating parallel to the plane of the substrate 15 , as described in U.S. Pat. No. 4,842,683, issued Jun. 27, 1989, which is incorporated herein by reference. The magnetic field in the process chamber 30 should be sufficiently strong to increase the density of the ions formed in the energized process gas, and sufficiently uniform to reduce charge-up damage to features such as CMOS gates. Generally, the magnetic field as measured on a surface of the substrate 15 is less than about 500 Gauss, and more typically from about 10 to about 100 Gauss.

Spent process gas and etchant byproducts are exhausted from the process chamber 30 through an exhaust system 75 capable of achieving a minimum pressure of about 10 −3 mTorr in the process chamber 30 . A throttle valve 80 is provided in the exhaust for controlling the pressure in the process chamber 30 . Also, an optical endpoint measurement technique is typically used to determine completion of the etching process for a specific layer by measuring the change in light emission intensity of a particular wavelength corresponding to a detectable gaseous species. A sudden decrease or increase in the amount of the detectable species, such as for example, CO or CN, that results from chemical reaction of the process gas with the silicon dioxide or polysilicon layer indicates completion of etching of the dielectric layer and start of etching of the underlayer.

The etching process of the present invention uses a process gas that provides high etch rate and a high etching selectivity ratio of low K dielectric layer 10 comprising an organic polymer material. The process comprises the steps of placing a substrate 15 having a low K dielectric layer 10 with a patterned resist layer thereon into a process zone 35 , introducing a process gas comprising oxygen into the process zone 35 , and energizing the process gas in the process zone 35 to etch the polymer layer. Although the precise mechanism of the etching is unknown, it is believed the etching occurs primarily by the reaction of the oxygen gas with the hydrocarbon components of the organic polymer of the low K dielectric layer 10 to form gaseous carbon compounds, such as CO, CO 2 , and other carbon-containing gases, that are exhausted from the process chamber 30 .

The flow rate of the oxygen gas is dependent on the size of the process zone 35 and should be sufficiently high to react with substantially all the etchant residue on the substrate 15 to form gaseous byproducts. However, excessively high flow rates can isotropically etch the low K dielectric layer, which is undesirable. For a process zone 35 having a volume of about 10,000 cm 3 , a suitable flow rate of oxygen gas is about 5-100 sccm, and more preferably about 10-40 sccm. For different sized process chambers 30 , equivalent flow rates of oxygen that maintain substantially the same ratio of oxygen flow in sccm to process chamber 30 volume in cm 3 should be used.

Preferably, the process gas further comprises an inert gas that is activated by the energized process gas to sputter and remove dissociated material loosely adhered to the surface of the low K dielectric layer 10 , thereby enhancing the dielectric etch rate. The inert gas can comprise argon, xenon, neon, krypton, or helium, of which helium is preferred. Because excessive amounts of inert gases can dilute the relative concentration of oxygen gas reducing the overall etch rate, the volumetric flow rate of inert gases to oxygen gas is tailored to provide optimum etch rates and etching selectivity ratios for a specific polymer. The content of the inert gas in the process gas is typically from about 5 to about 40 sccm.

For optimal etching, the volumetric flow ratio of oxygen to inert gas is selected to provide both a high etch rate and a high etching selectivity to the overlying hard mask layer 20 of SiO 2 or Si 3 N 4 so as not to etch away the hard mask layer 20 before etching through the low K dielectric layer. Preferably, the volumetric flow ratio of oxygen to inert gas is selected to provide an etching layer selectivity ratio of etching the low K dielectric material relative to the hard mask layer 20 (and also relative to the underlayer) of at least about 15:1, while simultaneously etching the low K dielectric layer 10 at a high etch rate of at least about 0.5 μm/min, and more preferably from 0.7 to 1.5 μm/min. Preferably, the volumetric flow ratio of oxygen to the other gas is from about 1:0 to about 0:1, for example from about 2:1 to about 1:2, and more preferably from 2:1 to 1:0, and most preferably about 1:1. For example, when the substrate 15 comprises an underlayer below the low K dielectric layer 10 , such as a poly or monocrystalline silicon, metallic silicide, silicon oxide, or silicon nitride layer, the volumetric flow ratio of oxygen to an inert gas can be tailored to increase etching selectivity ratios for specific combinations of materials, such as for example, the etching of benzocyclobutene to a silicon substrate 15 . In particular, the volumetric flow ratio of the process gas is selected so that the etching selectivity ratio of dielectric to silicon substrate 15 is at least about 5:1, and more preferably at least about 15:1. The volumetric flow ratio of oxygen to an inert gas can also be adjusted so that the etch rate of the low K dielectric layer 10 is at least 10, while sidewalls 90 of the etched features have smooth surfaces that form angles of at least about 85° with the surface of the low K dielectric layer 10 on the substrate 15 . Although preferred volumetric flow ratios are recited herein, it should be understood that the volumetric flow ratios can be tailored for different combinations of materials, and feature geometry, such as feature aspect ratios, to achieve specific etching selectivity ratios or etch rates without deviation of the present invention.

In another embodiment of this invention, it has been found that the addition of passivating gases in combination with oxygen and an inert gas provides passivating films on the sidewalls 90 of freshly etched features thereby promoting anisotropic etching. It is believed, that the added passivating gases react with dissociated carbon atoms to form polymers that deposit on the sidewalls 90 of the freshly etched features as passivating films that improve vertical anisotropic etching. Suitable gases include N 2 , H 2 , NH 3 , CO, or mixtures thereof, of which N 2 is preferred. Preferably, the volumetric flow ratio of oxygen, inert gas, and passivating gas is from about 1:5:5 to about 1:0:0, for example from about 2:1:1 to about 1:4:4, and more preferably from about 1:1:1 to about 1:0:5, and most preferably from about 1:0:1 to about 1:0:5.

A further advantage of the process gas is that the oxygen-containing gas removes or strips any photoresist, etchant byproducts, and excessive passivating deposits remaining on the substrate 15 while simultaneously etching the low K dielectric layer 10 , especially at low etching temperatures. Thus, when the etching of the low K dielectric layer 10 is completed, a post-process of stripping photoresist can proceed immediately without interrupting the manufacturing process. However, in contrast to conventional resist stripping processes that require the substrate 15 to be heated to temperatures of from about 200 to about 400° C. in order to burn off the resist, the process of the present invention removes the low K dielectric layer by etching at low temperatures. FIG. 2 shows a schematic of a partial molecule of benzocyclobutene, showing the SI—O linkages and the hydrocarbon groups. It has been discovered that the reaction between the oxygen-containing gas and hydrocarbon groups of the organic polymer of the low K dielectric layer 10 is exothermic, and the etching rate of the low K dielectric is actually improved by lowering the temperature of the substrate 15 . Preferably, the substrate 15 is cooled using helium as described above to a temperature of less than about 40° C. More preferably, the substrate 15 is cooled to a temperature of at least about −30° C.

In yet another aspect, the present invention is to a method for forming multiple levels of interconnecting lines 95 , and vias 100 in low K dielectric layers 10 by a dual damascene process. In this method, illustrated in FIGS. 3 a to 3 d , a low K dielectric layer 10 having a thickness of from about 0.5 to about 5 μm, is deposited over interconnecting lines 95 of conducting material on an underlying layer 105 on the substrate 15 . A patterned hard mask layer 20 of silicon oxide or nitride is formed over the low K dielectric layer 10 . Thereafter, the process of the present invention is used to etch first voids 110 in the low K dielectric layer 10 for fabricating vias 100 that connect the different levels of interconnecting lines 95 to one another.

The first voids 110 etched in the dielectric layer are filled with a sacrificial material 115 that is resistant to the patterning processes used to pattern and etch through the hard mask layer 20 , and that is etched at the same or lower rate than the rate of etching of the organic polymer low K dielectric layer 10 by the present process. A second layer of hard mask 20 is formed over the surfaces of the filled voids and the low K dielectric layer 10 , and the hard mask layer 20 is patterned to provide a layer of another set of resist features on the substrate 15 .

The low K dielectric layer 10 is etched for a second time by the present etching process to form second voids 120 in the low K dielectric layer 10 , the second voids 120 sized and distributed to form second interconnect lines, which overlie the first voids 110 formed for the interconnecting vias 100 . Thereafter, the sacrificial material 1 15 is removed from the first voids 110 by a wet etching process that removes any remaining sacrificial material 115 substantially without etching or damaging the surrounding low K dielectric layer 10 . The first and second voids 120 are filled with metal in a single metallization step to form interconnect plugs and overlying interconnecting lines 95 , as shown in FIG. 3 d.

One problem of performing the dual damascene process for etching low K dielectric polymer layer, is that the sacrificial material 115 in the first voids 110 should not be removed by any of the subsequent processes that are used to form the second voids 120 . At the same time, the sacrificial material 115 must be capable of being readily removed by a process that does not damage or etch the surrounding low K dielectric layer 10 . Preferably, the sacrificial material 115 is a photoresist that consists essentially of an organic polymer that is etched at approximately the same or lower rate as the low K dielectric layer 10 . More preferably, the photoresist used as the sacrificial material 115 is not removed by the etching process used to etch the second voids 120 for forming the second interconnecting lines 95 . This can be accomplished by using a photoresist that is opposite to the photoresist type used to pattern the hard mask layer 20 . For example, when a positive-resist such as RISTON® is used to pattern the hard mask layer 20 , a negative resist is used for the sacrificial material 115 . Another method is to select a photoresist that is sensitive to different frequencies of light, so that photoresist used as a sacrificial material 115 is not altered by exposure to the light used to pattern the hard mask layer 20 . A third way is to use a reticle that exposes or masks the sacrificial material 115 in the first voids 110 as it simultaneously defines the second voids 120 in a photoresist layer 25 on the hard mask layer 20 . A suitable photoresist, which is not exposed by the same frequency of light as RISTON®.

The present invention has been discovered to provide a method for removing a suitable sacrificial material 115 from a silicon-containing low K dielectric layer 10 , such as benzocyclobutene, substantially without damaging or etching the surrounding low K dielectric layer 10 . In the method, after the second voids 120 have been formed in the hard mask layer 20 , the substrate 15 is immersed in a bath of a stripping solution, which removes the sacrificial material without reacting with the low K dielectric material. A suitable stripping solution comprises EKC®, commercially available from Shippley Corporation of Newton, Mass. The substrate is immersed in the bath from about 5 seconds to 1 hour. In addition, methods that employ additional energy imparted to the bath, such as ultrasonic baths or elevated temperatures can also be used. Following the wet etching step, the etching solution that remains on the substrate 15 surface is neutralized and removed by a suitable rinsing apparatus. Suitable rinsing apparatus include a cascade overflow rinsing tank, a quick down rinser, or a spin rinse/dryer.

The following examples illustrate the process of the present invention for etching low K dielectric layers 10 comprising organic polymers, especially silicon-containing low K dielectric layers, on semiconductor substrates 15 . However, the apparatus and method can be used in other applications as would be apparent to those skilled in the art, and the scope of the present invention should not be limited to the illustrative examples provided herein.

In these examples, the substrates 15 were silicon wafers of 200 mm (8 inch) diameter, coated successively with a benzocyclobutene layer having a thickness of about 2 μm, and a silicon oxide hard mask layer 20 having a thickness of about 0.3 μm. In addition there was a layer of photoresist, typically about 1 μm thick, on the hard mask layer 20 . The substrate 15 was placed on the support 40 of a DIELECTRIC ETCH MxP+ CENTURA chamber. Process gas comprising O 2 and N 2 in the particular volumetric flow rates and volumetric flow ratios described below were introduced into the process chamber 30 and the process chamber 30 was maintained at a pressure of about 30 mTorr. Thereafter, the process gas was energized in the process zone 35 by applying a RF voltage to the process electrodes, and the energized process gas was enhanced by applying a rotating magnetic field within the process zone 35 . The particular power level applied to the process electrodes and the strength of the magnetic field are described for each example. The substrate 15 was cooled to temperatures sufficiently low to provide a high etching rate of the low K dielectric layer 10 . Typically, the substrate 15 was cooled to a temperature of 2° C. using a flow of helium on the backside of the substrate 15 maintained at a pressure of from about 2 to about 20 Torr.

Scanning electron microscope (SEM) photos or micrographs of the etched wafers were used to measure (i) the material removed from the low K dielectric layer 10 , (ii) the material removed from the overlying SiO 2 hard mask layer 20 , and (iii) the sidewall profile angle. The mean etch rate was calculated by measuring the depth of the features etched in the substrate 15 in at least 15 different places. The etching selectivity ratio was calculated from the ratio of the etch rate of the low K dielectric layer 10 to the etch rate of the hard mask layer 20 . The etch rate uniformity was calculated using the formula:

Uniformity=(maximum etch rate−minimum etch rate)/(2 mean etch rate)