Device and method for coding and decoding data

The present invention concerns in general terms the coding and decoding of digital data, and relates particularly to the use of a single circuit for coding and decoding data, for example in a device for sending and receiving data.

The invention also relates to the transfer of data between a memory and a data coding or decoding circuit.

In the majority of cases of transmission of data between a sending device and a receiving device, it is necessary to code the data before the sender transmits them, and correlatively to decode them after the receiver has received them. The purpose of the coding is for example to minimise transmission errors due to noise corrupting the transmitted data, or to encrypt the transmitted data.

The coding and decoding operations can be performed by a single circuit, which is programmed either in coding mode or in decoding mode. A data coding and decoding device then uses a coding circuit and a decoding circuit which are programmed once and for all.

However, in the case of applications functioning in half-duplex mode, it is clear that the coding circuit and the decoding circuit never operate simultaneously. Since these circuits are relative expensive, a device which has two of these circuits is expensive.

The type of coding envisaged here consists of increasing the total number of data to be transmitted, by adding coding data to the data initially to be transmitted, or useful data.

A coding circuit processes the useful data in blocks in order to code them, one block including for example a few tens of octets. The coding circuit requires as an input blocks of data to be coded separated from each other by padding blocks. The coding circuit replaces the padding blocks with blocks of coding data. The coding circuit produces successive frames each having a block of useful data formed by a certain number of words of useful data, and a block of coding data formed by a certain number of words of coding data.

On reception, the coding data must be separated from the useful data. The coding data are used for decoding the useful data, for example by correcting any transmission errors, or by decrypting the useful data. The latter can then be stored to memory, for example.

The decoding circuit therefore produces successive blocks of useful data.

In addition, more and more devices use a direct access circuit for transferring data between two internal circuits. A direct access circuit allows more rapid transfers than a processor and does not monopolise the processor.

In order to use a direct access circuit as effectively as possible, that is to say to effect rapid data transfers, it is necessary to effect a continuous transfer of a data “stream”. However, as stated above, the coding circuit requires, as an input, blocks of data to be coded separated from each other by padding blocks.

There is therefore incompatibility between transferring the data in continuous streams and supplying useful data in blocks, with interruption between the blocks.

This is because the transmission of successive small blocks of data by means of a direct access circuit eliminates the advantage of the latter, since it would then be necessary to reprogram the direct access circuit for each block transmitted.

In order to transfer data between a memory and a coding circuit as envisaged here, it is therefore not realistic to effect successive transfers of blocks containing the number of words of useful data for each of the frames to be formed.

In order to effect a continuous transfer of a large number of words of useful data between the memory and the coding circuit, it can be envisaged including non-significant words after each block of useful data, prior to transfer. At the time of coding, these non-significant words will be replaced by the coding words. However, this results in storing the non-significant words with the useful data words, and consequently a large amount of memory space is necessary.

Likewise, after decoding, in order to effect a continuous transfer of a large number of data words to the memory, it can be envisaged transmitting the coding words with the useful data words. There again, this results in using a large amount of memory space, by the storage of coding words which then no longer have any function.

Both for coding and decoding, the memory is poorly used, since it contains non-signficant words or coding words, in addition to useful data.

Thus the transfer of data between a memory and a coding or decoding circuit by means of a direct access circuit results in using either the direct access circuit or the memory in a non-optimum fashion.

The present invention aims to remedy the drawbacks of the prior art by providing a device and a method for coding and decoding data which makes it possible to code and decode data in half-duplex mode in a more economical fashion, whilst being just as effective, than in the prior art.

For this purpose, the invention proposes a method of coding and decoding data, the data to be coded and the decoded data being stored in a memory, characterised in that the coding and decoding are performed by a single data coding and decoding means,

and in that it includes the steps of:

initialising the coding and decoding means in coding mode, and controlling the passage of data to be coded from the memory to the coding and decoding means, and

initialising the coding and decoding means in decoding mode, and controlling the input of coded data into the coding and decoding means, and the passage of decoded data from the coding and decoding means to the memory.

Correlatively, the invention concerns a data coding and decoding device, having a memory for storing the data to be coded and the decoded data,

characterised in that it has a single data coding and decoding means and a control means adapted to, selectively:

initialise the coding and decoding means in coding mode, and control the passage of data to be coded from the memory to the coding and decoding means, and

initialise the coding and decoding means in decoding mode, and control the input of coded data into the coding and decoding means, and the passage of decoded data from the coding and decoding means to the memory means.

The invention also concerns a data coding and decoding device, adapted to cooperate with a memory for storing the date to be coded and the decoded data,

characterised in that it has a single data coding and decoding means and a control means adapted to, selectively:

initialise the coding and decoding means in coding mode, and control the passage of data to be coded from the memory to the coding and decoding means, and

initialise the coding and decoding means in decoding mode, and control the input of coded data into the coding and decoding means, and the passage of decoded data from the coding and decoding means to the memory means.

The method and device according to the invention allow a coding and a decoding of data in half-duplex mode which is performed economically since a single coding and decoding component is required.

According to a preferred characteristic of the invention, the method also includes the step of controlling a transfer of data to a data transmission means after the coding of the data. This is because the data coding applies particularly to the transmission of data, for example by radio transmission.

According to another preferred characteristic of the invention, the method includes the step of controlling a transfer of data between a data reception means connected at the input to the coding and decoding means, and the coding and decoding means. This is because the decoding of data applies particularly to the reception of data which have for example been sent by radio transmission.

The control means is advantageously connected at the input and output of the coding and decoding means, so that the data to be coded and the decoded data pass through the control means. Controlling the data transfer is thus performed reliably and economically.

According to other preferred characteristics, the device includes a data transmission means connected at the output of the coding and decoding means, and the control means is adapted to control the transfer of data between the coding and decoding means and the transmission means.

The device includes a data reception means, and the control means is adapted to control the transfer of data between the data reception means and the coding and decoding means. The device according to the invention is thus particularly used in a data sending and receiving context.

The present invention also concerns a data processing device, a communication device, such as computer, printer or facsimile apparatus, including the preceding coding and decoding device.

The present invention also concerns a storage medium, such as a floppy disk or a CD-ROM.

The advantages of these devices and storage medium are similar to those previously described.

The aim of the invention is also to make the use of a coding circuit or decoding circuit compatible with a direct access circuit, and to allow a rapid transfer of data between a memory and a coding or decoding circuit, whilst allowing optimum use of the memory.

To this end, the invention proposes a device for the coding of data extracted from a main memory, the data being in the form of useful data words, having:

a means of direct access to the main memory in order to extract the data to be coded,

a means of coding the extracted data, by the formation of groups of words each having a first predetermined number of useful data words and a second predetermined number of additional words, the additional words being determined by the coding means,

characterised in that it has:

a first buffer memory means connected between the direct access means and the coding means, the said buffer memory means receiving the extracted data, and

a means of controlling the transfer of data between the first buffer memory means and the coding means, adapted to control successively a transfer of the first predetermined number of useful data words and an interruption of the transfer of the data words for a period of interruption corresponding to the period which would be necessary for transferring the second predetermined number of additional words.

The invention also proposes a data coding device, adapted to cooperate with:

a main memory containing the data to be coded, the data being in the form of useful data words,

a means of direct access to the main memory for extracting the data to be coded,

and having:

a means of coding the extracted data, by the formation of groups of words each having a first predetermined number of useful data words and a second predetermined number of additional words, the additional words being determined by the coding means,

characterised in that it has:

a first buffer memory means connected between the direct access means and the coding means, the said buffer memory means receiving the extracted data, and

a means of controlling the transfer of data between the first buffer memory means and the coding means, adapted to control successively a transfer of the first predetermined number of useful data words and an interruption of the transfer of the data words for a period of interruption corresponding to the period which would be necessary for transferring the second predetermined number of additional words.

Correlatively, the invention proposes a method of coding data extracted from a main memory, the data being in the form of useful data words, including the step of:

coding the extracted data, by a coding means forming groups of words each including a first predetermined number of useful data words and a second predetermined number of additional words, the additional words being determined by the coding,

characterised in that it includes the steps of:

storing the extracted data in a first buffer memory means, prior to coding, and

controlling a transfer of the first predetermined number of useful data words between the first buffer memory means and the coding means, and successively an interruption of the transfer of the data words for a period of interruption corresponding the period which would be necessary for transferring the second predetermined number of additional words.

The coding device and method according to the invention allow a rapid transfer of data between the main memory and the coding circuit, by means of the direct access circuit, whilst storing only the useful data in the main memory.

Thus the main memory and the direct access circuit are both used in an optimum fashion, by virtue of the use of a buffer memory between the direct access means and the coding means, and by virtue of the appropriate control of the data transfers between the buffer memory and the coding means.

According to a preferred characteristic, the control means is adapted to control the transfer of data between the main memory and the first buffer memory means, via the direct access means.

The transfer of data between the main memory and the buffer memory is a rapid transfer of a large number of useful data, whilst the transfer of data between the buffer memory and the coding means is a transfer of successive blocks of data words each containing a smaller number of useful data words.

According to another preferred characterstic, a data transmission means is connected at the output from the coding means, and the control means is adapted to control the transfer of data between the coding means and the transmission means. In fact, the coding of data is applied particularly to the transmission of data, for example, by radio transmission.

The invention also concerns a device for the decoding of data coded in the form of groups of words each having a first predetermined number of useful data words and a second predetermined number of additional words, having:

a means of decoding the coded data, in order to supply the first predetermined number of useful data words in each of the groups of words,

a main memory for storing the useful data words supplied by the decoding means,

a means of direct access to the main memory in order to enter the useful data words therein,

characterised in that it has:

a second buffer memory means connected between the decoding means and the direct access means, and

a means of controlling the transfer of data between the decoding means and the second buffer memory means, adapted to control successively a transfer of the first predetermined number of useful data words and an interruption of the transfer of the data words for a period of interruption corresponding to the period which would be necessary for transferring the second predetermined number of additional words.

The invention also concerns a device for the decoding of data coded in the form of groups of words each having a first predetermined number of useful data words and a second predetermined number of additional words, having:

a means of decoding the coded data, in order to supply the first predetermined number of useful data words in each of the groups of words,

and adapted to cooperate with:

a main memory for storing the useful data words supplied by the decoding means,

a means of direct access to the main memory in order to enter the useful data words therein,

characterised in that it has:

a second buffer memory means connected between the decoding means and the direct access means, and

a means of controlling the transfer of data between the decoding means and the second buffer memory means, adapted to control successively a transfer of the first predetermined number of useful data words and an interruption of the transfer of the data words for a period of interruption corresponding to the period which would be necessary for transferring the second predetermined number of additional words.

Correlatively, the invention concerns a method of decoding data coded in the form of groups of words each having a first predetermined number of useful data words and a second predetermined number of additional words, including the steps of:

decoding the coded data, by a decoding means supplying the first predetermined number of useful data words in each of the groups of words,

storing the useful data words supplied by the decoding means,

characterised in that it includes the steps of:

storing the decoded data in a second buffer memory means, and

controlling a transfer of the first predetermined number of useful data words between the decoding means and the second buffer memory means, and successively an interruption of the transfer of the data words during a period of interruption corresponding to the period which would be necessary for transferring the second predetermined number of additional words.

The advantages offered by the invention for transferring data between the decoding means and the main memory are similar to those set out above.

According to preferred characteristics:

the control means is adapted to control the transfer of data between the second buffer memory means and the main memory, via the direct access circuit,

a data reception means is connected at the input of the decoding means, and the control means is adapted to control the transfer of data between the data reception means and the decoding means.

The present invention also concerns a data processing device, a communication device, such as computer, printer or facsimile apparatus, including the preceding device for the coding of data extracted from a main memory or the corresponding decoding device.

The present invention also concerns a storage medium, such as a floppy disk or a CD-ROM.

The advantages of these devices and storage medium are similar to those previously described.

The characteristics and advantages of the present invention will emerge more clearly from a reading of several embodiments illustrated by the accompanying drawings, in which:

FIG. 1 is a block diagram of a first embodiment of a sending and receiving device according to the invention,

FIG. 2 depicts a block diagram for the management of the data buses at the input and output of an error correction circuit included in the device of FIG. 1,

FIG. 3 depicts control signals and state signals used in the device of FIG. 1,

FIG. 4 depicts the operating algorithm of the sending and receiving device according to the invention,

FIG. 5 depicts a data transfer algorithm for the reception of data, included in the algorithm of FIG. 4,

FIG. 6 depicts a data transfer algorithm for the sending of data, included in the algorithm of FIG. 4,

FIG. 7 is a block diagram of a second embodiment of a sending and receiving device according to the invention,

FIG. 8 depicts an error correction code word formed in the device of FIG. 7,

FIGS. 9 a to 9 c depict sequences of octets passing through the device of FIG. 7,

FIG. 10 depicts the control signals and state signals used in the device of FIG. 7,

FIGS. 11 to 13 depict data transfer algorithms for the sending of data, and

FIGS. 14 to 16 depict data transfer algorithms for the reception of data.

In the first embodiment chosen and depicted in FIG. 1, a data coding and decoding device is a data sending and receiving device having a main memory 1 in which data are stored. The data sending and receiving device is connected, via the memory 1 to a data processing device 10 , known per se. The device 10 can be a computer, or a processing terminal, connected by a data bus to the memory 1 .

The device 10 can be used conventionally to configure operating parameters for the different circuits of the data sending and receiving device, for example for initialising the circuit 4 , which will be detailed subsequently.

The data sending and receiving device can also be integrated into a data processing device 100 or into a communication device 100 , such as a computer, a printer, or a facsimile apparatus. The memory 1 is then connected to a data processing circuit internal to the data processing device or communication device.

The main memory 1 is connected by a bidirectional bus B 1 to a logic controller 3 which controls the data transfers internal to the sending and receiving device. The logic controller 3 can be a programmable circuit, for example of the FPGA (Field Programmable Gate Array) type, or a circuit of the ASIC (Application Specific Integrated Circuit) type. The logic controller 3 is described in detail hereinafter.

A direct access circuit 2 , referred to as a DMA (Direct Access Memory) circuit, affords bidirectional access, direct to the main memory 1 . The circuit 2 here uses two channels in a monodirectional fashion, which form a sending channel and a receiving channel. This circuit has the advantage of affording very rapid access to the main memory 1 .

The logic controller 3 is connected to a data coding and decoding circuit, here an error correction circuit 4 , by means of a monodirectional bus B 3 . The error correction circuit 4 is an FEC (Forward Error Correction) circuit which codes the data to be sent and decodes the data received. The error correction circuit 4 is therefore alternately a coder and a decoder, as detailed hereinafter. The coding and decoding are performed according to an algorithm of the VITERBI type, suitable when the errors are not grouped together, or according to an algorithm of the REED-SOLOMON type, suitable in the case of errors in packets. The latter type of error correction will be considered more particularly hereinafter.

The error correction circuit 4 is connected by a monodirectional bus B 4 to a sending circuit 5 which sends the data over a transmission channel.

A receiving circuit 6 receives data via the transmission channel and is connected by a monodirectional bus B 2 to the logic controller 3 . The data received are coded and must be decoded by the error correction circuit 4 .

The sending and receiving of data operate in half-duplex mode. First of all, in the sending direction, data to be sent are transmitted between the memory 1 and the error correction circuit 4 , via the logic controller 3 . The data are in the form of a sequence of octets forming a useful message. All the N octets received, where N is an integer equal to 25 by way of example, the circuit 4 inserts K redundant octets, which K is an integer equal to 6 by way of example. N useful octets OC 1 , to OC N and K redundant octets OR 1 to OR K form an error correction code word MC. The K redundant octets OR 1 , to OR K are determined by the error correction circuit 4 , according to a REED-SOLOMON algorithm, in order to correct K/2 possible errors in the error correction code word.

The error correction circuit 4 supplies the error correction code words to the sending circuit 5 , which sends them over the transmission channel.

Moreover, in the receiving direction, the receiving circuit 6 receives, from the transmission channel, data coded in the form of a code word MC and transmits them to the logic controller 3 , which transmits them to the error correction circuit 4 .

The error correction circuit 4 decodes the data received by performing, overall, decoding operations which are the reverse of the coding operations performed on sending. The error correction circuit 4 receives error correction code words MC including N useful octets OC 1 to OC N and K redundant octets OR 1 to OR K . The circuit 4 uses the K redundant octets to detect and correct any errors in the words received. The decoding results in decoded words MD containing the N useful message octets, if necessary corrected by virtue of the redundant octets, and K redundant octets OR 1 to OR K which no longer have any role.

The circuit 4 transfers the decoded words to the logic controller 3 via the bus B 4 for the purpose of storing the useful message octets OC 1 to OC N in the main memory 1 .

FIG. 2 shows the management of the data buses of the data sending and receiving device.

In general terms, the error correction circuit 4 receives data via the bus B 3 . After processing of the data, coding or decoding, the circuit 4 supplies the processed data over the bus B 4 .

Control of the data flows makes it possible on the one hand to selectively connect the bus B 1 or the bus B 2 to the bus B 3 and on the other hand to selectively connect the bus B 4 to the sending circuit or to the bus B 1 : to do this, the logic controller 3 controls “switches” at the input and output of the error correction circuit 4 .

In the preferred embodiment, the switching and control functions are combined in the logic controller 3 .

Thus the bus B 1 , is connected to a storage flip-flop 31 , itself connected to a first input EN 1 of a multiplexer 32 whose output S 1 is connected to the bus B 3 . The bus B 2 is connected to a second input EN 2 of the multiplexer 32 . The bus 34 is connected to the bus B 1 via a three-state bus control unit 33 .

A logic control signal COM 1 controls the operation of the flip-flop 31 , to switch the data present on the bus B 1 to the multiplexer 32 , when the signal COM 1 is at the low state. A logic control signal COM 2 selectively connects the first input EN 1 of the multiplexer 32 to its output S 1 when the signal COM 2 is at the low state, or the second input EN 2 to the output S 1 , when the signal COM 2 is at the high state. A logic control signal COM 3 controls the passage of the data present on the bus B 4 to the bus B 1 , when the signal COM 3 is at the high state, and prevents its passage otherwise.

As a variant, the switching and control functions can be implemented in distinct circuits.

FIG. 3 depicts a block diagram of the logic signals exchanged between the logic controller 3 and the direct access circuit 2 , the error correction circuit 4 , the sending circuit 5 , the receiving circuit 6 and the data processing circuit 10 . Some of these signals control the data transfers between the main memory 1 and the sending circuit 5 and receiving circuit 6 , as well as the operation of the circuits involved in the sending and receiving of data. Other ones of these signals represent operating states of the different circuits, relating to the transfer of data.

The logic controller 3 supplies the following logic signals to the error correction circuit 4 :

a clock signal CLK, of frequency equal to 20 MHz,

a signal IN for instructing the error correction circuit 4 to take into account the octet which is supplied to it at its input (bus B 3 ), when the signal IN is at the low state simultaneously with a rising edge of the clock signal CLK,

a signal OUT for instructing the error correction circuit 4 to supply an octet at its output (bus B 4 ), when the signal OUT is at the low state simultaneously with a rising edge of the clock signal CLK,

a signal HR for indicating to the error correction circuit 4 that the octet which is supplied to it as an input (bus B 3 ) is a redundant octet or a padding octet, when the signal HR is at the high state.

The error correction circuit 4 supplies the following logic signals to the logic controller 3 :

a signal AIN for indicating to the logic controller 3 that the circuit 4 is not full, and that it can receive an octet, when the signal AIN is at the low state,

a signal AOUT for indicating to the logic controller 3 that the circuit 4 is ready to transmit an octet, when the signal AOUT is at the low state.

The logic controller 3 supplies the following logic signals to the direct access circuit 2 :

a signal DC E for asking a direct access channel for a sending of data, between the main memory 1 and the logic controller 3 , when the signal DC E goes to the high state,

a signal DC R for asking a direct access channel for a reception of data, between the logic controller 3 and the main memory 1 , when the signal DC R goes to the high state.

The direct access circuit 2 supplies the following logic signals to the logic controller 3 :

a signal ACQ E in response to the signal DC E , in order to acknowledge the request for a direct access channel for sending. When the signal ACQ E goes to the low state, this means that the direct access circuit 2 is performing the transfer of data between the main memory 1 and the logic controller 3 ,

a signal ACQ R in response to the signal DC R in order to acknowledge the request for a direct access channel for receiving. When the signal ACQ R goes to the low state, this means that the direct access circuit 2 is performing the transfer of data between the logic controller 3 and the main memory 1 .

The sending circuit 5 supplies a signal DEM E to the logic controller 3 . The signal DEM E is an authorisation to send data when it goes to the high state.

The receiving circuit 6 supplies a signal DEM R to the logic controller 3 . The signal DEM R indicates that a data reception is detected by the circuit 6 when it goes to the high state.

The data processing circuit 10 supplies a signal DO E to the logic controller 3 . The signal DO E indicates that the data present in the memory 1 are ready to be sent, when it goes to the high state.

FIG. 4 shows the operating algorithm for the device of FIG. 1 . This algorithm can be, totally or partially, memorised in any storage medium SM 1 capable of cooperating with the logic controller 3 . This storage medium is integrated or can be detachably mountable on the data coding and decoding device. For example, the storage medium is a floppy disk, or a CR-ROM. The algorithm includes steps E 1 to E 7 , which are run through cyclically.

At the following step E 2 , the logic controller 3 initialises the error correction circuit 4 in decoding mode, according to a procedure which depends on the type of error correction circuit used. This procedure consists for example of transmitting control signals and/or configuration octets to the circuit 4 , in order to program it in decoding mode. This initialisation makes it possible notably to fix the values of the parameters N and K.

Step E 2 is followed by step E 3 , which is a test for verifying whether a data reception is detected by the circuit 6 , by verifying whether the signal DEM R is at the high state. When the response is positive, the logic controller 3 generates, at step E 4 , the appropriate signals for the device to process the data received and to store them in the memory 1 . Step E 4 is detailed with reference to FIG. 5 and is followed by step E 3 .

When no reception is detected at step E 3 , step E 5 is a test for verifying whether the data are to be sent and whether the sending circuit 5 is ready for sending, which corresponds to the two signals DO E and DEM E at the high state. If the response is negative, step E 5 is followed by step E 3 .

If there are data to send, step E 5 is followed by step E 6 in which the logic controller 3 initialises the error correction circuit 4 in sending mode, or coding mode, according to a procedure which depends on the type of error correction circuit used. This procedure consists for example of transmitting control signals and/or configuration octets to the circuit 4 , in order to program it in coding mode.

Step E 6 is followed by step E 7 , in which the logic controller 3 generates the appropriate signals for data to be sent to be transmitted from the memory 1 to the sending circuit 5 , via the logic controller 3 and error correction circuit 4 . Step E 7 is detailed hereinafter with reference to FIG. 6 .

Step E 7 is followed by step E 2 , in which the circuit 4 is reinitialised in decoding mode.

It will be noted that, according to this embodiment, the coding and decoding circuit 4 is in decoding mode by default, and that it goes to coding mode when there are data to be sent. This functioning gives priority to decoding and is suited to cases where it is not known when a remote device is sending its data.

For different applications, it is possible to initialise the device in coding mode by default, in order to give priority to coding.

According to FIG. 5, step E 4 of receiving data includes substeps E 40 to E 51 which are run through cyclically.

Step E 40 is an initialisation in which the logic controller initialises a counter CPT 1 at zero, and transmits the following signals to the error correction circuit 4 :

the signal IN at the high state in order to instruct not to take into account data supplied at the input of the error correction circuit 4 ,

the signal HR at the low state in order to indicate that octets supplied at the input of the error correction circuit are not redundant or padding octets,

the signal OUT at the high state in order to instruct the error correction circuit 4 not to supply an octet at its output.

The logic controller transmits the signal DC R at the low state to the direct access circuit 2 , in order not to request a channel in receiving mode from the direct access circuit 2 .

The logic controller 3 puts the control signal COM 2 at the high state in order to instruct the multiplexer 32 to connect the buses B 2 and B 3 . Thus the data supplied by the receiving circuit 6 , via the bus B 2 , are transmitted to the error correction circuit 4 via the bus B 3 . The logic controller 3 puts the control signal COM 3 at the low state so that the data present on the bus B 4 do not pass over the bus B 1 .

Step E 40 is followed by steps E 41 and E 47 . Steps E 41 to E 46 on the one hand, and steps E 47 to E 50 on the other hand, form two branches which are run through simultaneously and independently of each other. Passage from one step to the following is effected in accordance with clock frequencies which can be different for the two branches.

Steps E 41 to E 46 make it possible to transfer data received by the receiving circuit 6 to the error correction circuit 4 , via the logic controller 3 .

Step E 41 is a test on the value of the signal AIN, in order to determine whether the error correction circuit 4 is ready to receive data (signal AIN at the low state). As long as the response is negative, step E 41 is repeated.

When the response to step E 41 is positive, step E 41 is followed by step E 42 , in which the logic controller 3 supplies the signal IN at the low state to the error correction circuit 4 , so that an octet supplied to the error correction circuit 4 is taken into account by this circuit. The counter CPT 1 is incremented by one unit.

Step E 42 is followed by step E 43 , which is a test on the value of the counter CPT 1 . As long as the counter CPT 1 has not reached the value N, corresponding to the number of useful octets of an error correction code word MC, steps E 41 and E 42 are repeated.

When the counter CPT 1 reaches the value N, this means that N octets have been transmitted to the error correction circuit 4 ; step E 43 is then followed by step E 44 , analogous to step E 41 . Step E 44 is a test on the value of the signal AIN, in order to determine whether the error correction circuit 4 is ready to receive data (signal AIN at the low state). As long as the response is negative, step E 44 is repeated.

When the response to step E 44 is positive, step E 44 is followed by step E 45 , in which the logic controller 3 supplies the signal IN at the low state to the error correction circuit 4 , so that an octet supplied to the error correction circuit 4 is taken into account by this circuit. The counter CPT 1 is incremented by one unit. The logic controller 3 supplies the signal HR at the high state to the error correction circuit 4 , in order to indicate to it that the octets which are supplied to it are redundant octets.

Step E 45 is followed by step E 46 , which is a test on the value of the counter CPT 1 . As long as the counter CPT 1 has not reached the value N+K, corresponding to the total number of octets of an error correction code word MC, steps E 44 and E 45 are repeated.

When the counter CPT 1 reaches the value N+K, this means that steps E 44 and E 45 have been repeated for all the redundant octets of an error correction code word. Step E 46 is then followed by step E 51 , which is analogous to step E 3 , and which is a test for verifying whether the reception of data has ended, that is to say whether the signal DEM R is at the low state. As long as the response is negative, steps E 40 to E 46 are repeated.

When the reception of data is ended, step E 51 is followed by step E 3 previously described.

Steps E 47 to E 50 make it possible to transfer data received and decoded by the error correction circuit 4 to the memory 1 , via the logic controller 3 .

Step E 47 is a test on the value of the signal AOUT. As long as the signal AOUT is not at the low state, step E 47 is repeated.

When the error correction circuit 4 supplies the signal AOUT at the low state to the logic controller 3 , this means the data are ready at the output of the error correction circuit 4 .

In this case, step E 47 is followed by step E 48 , at which the logic controller 3 supplies the signal OUT at the low state to the error correction circuit 4 , in order to instruct it to supply an octet on the bus B 4 . The logic controller 3 also supplies the signal DC R at the high state in order to request a channel to the main memory 1 .

The following step E 49 is a test on the value of the signal ACQ R . As long as the signal ACQ R is at the high state, step E 49 is repeated.

When the signal ACQ R goes to the low state, this means that a channel to the main memory 1 is available for the transfer of data. Step E 49 is followed by step E 50 , in which the logic controller 3 puts the control signal COM 3 at the high state in order to connect the bus B 4 to the bus B 1 , so that the octets leaving the error correction circuit 4 are sent over the bus B 1 to the memory 1 .

The logic controller 3 supplies the signal OUT at the high state to the error correction circuit 4 , in order to instruct the error correction circuit 4 not to supply an octet on the bus B 3 .

The logic controller 3 supplies the signal DC R at the low state to the direct access circuit 2 in order to deactivate its request for a channel.

Step E 50 is followed by step E 51 previously described. Steps E 40 to E 50 are repeated as long as the reception of data is not ended, that is to say as long as the response to step E 51 is negative.

Step E 7 of sending data is detailed with reference to FIG. 6, and includes substeps E 70 to E 83 which are run through cyclically.

Step E 70 is an initialisation in which the logic controller 3 initialises a counter CPT 2 at zero, and transmits the following signals to the error correction circuit 4 :

the signal IN at the high state in order to give instructions not to take into account data supplied at the input of the error correction circuit,

the signal OUT at the high state in order to instruct the error correction circuit 4 not to supply an octet at its output,

the signal HR at the low state in order to indicate that octets supplied to the error correction circuit 4 are not redundant octets.

The logic controller 3 transmits the signal DC E at the low state to the direct access circuit 2 , in order not to request a sending channel between the main memory 1 and the logic controller 3 .

The control signal COM 1 is put at the high state in order not to switch the data onto the bus B 1 , and the signal COM 2 is put at the low state in order to connect the buses B 1 and B 3 .

Step E 70 is followed by steps E 71 and E 81 . Steps E 71 to E 80 on the one hand, and steps E 81 to E 83 on the other hand, form two branches which are run through simultaneously and independently of each other. In these two branches, passing from one step to the following is effected at each switching of a clock, which can be different from one branch to the other.

Steps E 71 to E 80 make it possible to transmit N useful octets and K padding octets between the memory 1 and the error correction circuit 4 , so that the circuit 4 can form an error correction code word.

At step E 71 , the logic controller 3 transmits the signal DC E at the high state in order to request a sending channel to the direct access circuit.

The following step E 72 is a test of the value of the signal AIN. As long as the signal AIN is at the high state, step E 72 is repeated. When the signal AIN goes to the low state, this means that the error correction circuit 4 can receive octets.

The following step E 73 is a test for verifying whether the signal ACQ E is at the low state. As long as the signal ACQ E is at the high state, step E 73 is repeated.

When the signal ACQ E goes to the low state, step E 73 is followed by step E 74 , in which the signal COM 1 is put at the low state in order to switch the data onto the bus B 1 , and the logic controller 3 transmits the signal DC E at the low state to the direct access circuit in order to release the channel.

Step E 74 is followed by step E 75 , which is a test on the value of the counter CPT 2 .

As long as the counter CPT 2 has not reached the value N, step E 75 is followed by step E 76 , in which:

the logic controller 3 increments the counter CPT 2 by one unit,

the logic controller 3 transmits the signals IN and HR at the low state to the error correction circuit 4 , so that an octet supplied to the error correction circuit 4 is taken into account by it, and to indicate to it that this octet is not a redundant octet.

When the counter CPT 2 has reached the value N at step E 75 , this means that step E 76 has been run through for N useful octets OC 1 to OC N and that consequently N octets have been transmitted between the memory 1 and the logic controller 3 . Step E 75 is then followed by step E 77 , in which:

the logic controller 3 increments the counter CPT 2 by one unit,

the logic controller 3 transmits the signals IN and HR at the low state and high state respectively, to the error correction circuit 4 , so that an octet supplied to the error correction circuit 4 is taken into account by it, and to indicate to it that this octet is a padding octet.

Step E 77 is followed by step E 80 , which is a test on the value of the counter CPT 2 . If the counter CPT 2 has not reached the value N+K, step E 80 is followed by step E 71 .

When the counter CPT 2 reaches the value N+K, this means that step E 77 has been run through for K padding octets Or 1 to Or K and that consequently N+K octets have been transmitted between the memory 1 and the logic controller 3 . Step E 80 is then followed by step E 83 , which is a test for the end of the transmission, that is to say it tests whether the signal DO E is at the low state.

If the transmission is not ended, step E 83 is followed by step E 71 . If the transmission is ended, step E 83 is followed by step E 2 previously described.

Steps E 81 and E 82 make it possible to transfer an octet between the error correction circuit 4 and the sending circuit 5 .

Step E 81 is a test on the value of the signal AOUT. As long as the signal AOUT is at the high state, step E 81 is repeated.

When the signal AOUT goes to the low state, this means that the error correction circuit 4 has formed at least one code word MC which is ready to be sent. Step E 81 is then followed by step E 82 , in which the logic controller 3 supplies the signal OUT at the low state to the error correction circuit 4 , in order to instruct it to supply an octet to the sending circuit, via the output bus B 4 . Step E 82 is followed by step E 83 previously described.

In the second embodiment chosen and depicted in FIG. 7, a data sending and receiving device has a main memory 11 in which data are stored. The data sending and receiving device is connected, via the memory 11 , to a data processing device 20 , known per se. The device 20 can be a computer, or a processing terminal, connected to the memory 11 by a data bus.

The data sending and receiving device can also be integrated into a data processing device 200 or into a communication device 200 , such as a computer, a printer or a facsimile apparatus. The memory 11 is then connected to a data processing circuit internal to the data processing device, or communication device.

The main memory 11 is connected to a circuit 12 for direct access to the main memory 11 , referred to as a DMA (Direct Access Memory) circuit, which allows bidirectional access direct to the main memory 11 . The circuit 12 here uses two channels in a monodirectional fashion, which form a sending channel and a receiving channel. This circuit has the advantage of allowing very rapid access to the main memory 11 .

First of all in the sending direction the direct access circuit 12 is connected to a buffer memory 13 of the FIFO type (First In, First Out), itself connected to a data coding circuit, here an error correction circuit 14 . The error correction circuit 14 is an FEC (Forward Error Correction) circuit which codes the data to be sent, according to an algorithm of the VITERBI type, appropriate when the errors are not grouped, or according to an algorithm of the REED-SOLOMON type, appropriate in the case of errors in packets. This last type of error correction will be more particularly considered and detailed hereinafter.

The error correction circuit 14 is connected to a sending circuit 15 , which sends the data over a transmission channel.

The error correction circuit 14 receives data in the form of a sequence of words, for example octets, forming a useful message, and receives padding data in the form of padding words, here octets.

The error correction circuit 14 thus receives N octets of useful data followed by K padding octets, where N is an integer equal to 26 by way of example and K is an integer equal to 6 by way of example. When all the N octets have been received, the circuit 14 replaces the K padding octets with K redundant octets. The N useful octets OC 1 to OC N and the K redundant octets OR 1 to OR k form an error correction code word MC as depicted in FIG. 8 . The K redundant octets OR 1 , to OR K are determined by the error correction circuit 14 , according to a Reed-Solomon algorithm, for correcting K/2 possible errors in the error correction code word.

In addition, in the receiving direction, a receiving circuit 18 receives data from the transmission channel. The receiving circuit 18 is connected to a data decoding circuit, here an error correction circuit 17 . The error correction circuit 17 is connected to a buffer memory 16 of the FIFO type, similar to the buffer memory 13 . The buffer memory 16 is connected to the direct access circuit 12 , itself connected to the main memory 11 .

The error correction circuit 17 overall performs decoding operations which are the reverse of the coding operations of the circuit 14 . The error correction circuit 17 receives error correction code words MC having N useful octets OC 1 to OC N and K redundant octets OR 1 , to OR K . The circuit 17 uses the K redundant octets for detecting and correcting any errors in the words received. The decoding results in decoding words containing the N useful message octets, if necessary corrected by means of the redundant octets, and K redundant octets OR 1 to OR K which no longer have any role.

The circuit 17 transfers the decoded words to the buffer memory 16 , for the purpose of storing the useful message octets OC 1 to OC N in the main memory 11 .

An automatic control device 19 is connected to the direct access circuit 12 , to the buffer memories 13 and 16 and to the error correction circuits 14 and 17 , as will be detailed later.

The coding and decoding operations performed by the error correction circuits 14 and 17 are illustrated by FIGS. 9 a to 9 c .

FIG. 9 a depicts schematically a sequence of useful octets entering or leaving the main memory 11 . FIG. 9 b depicts the sequence of octets entering the error correction circuit 14 . This sequence includes an alternation of N useful octets OC 1 to OC N and K padding octets Or 1 to Or K . FIG. 9 c depicts the sequence of octets leaving the error correction circuit 14 or entering or leaving the error correction circuit 17 . This sequence includes an alternation of N useful octets OC 1 to OC N and K redundant octets OR 1 , to OR K . The K redundant octets are determined on sending, by the error correction circuit 14 , which inserts them in place of the padding octets.

According to other embodiments, the coding circuit is a data encripting circuit. The coding circuit then inserts a key formed by a certain number of octets following each of the coded useful data blocks. The corresponding decoding circuit uses the key for decoding the block of coded useful data. Other types of coding/decoding can be used in the scope of the invention.

FIG. 10 shows a block diagram of the logic signals exchanged between the automatic control device 19 and the direct access circuit 12 , the buffer memories 13 and 16 and the error correction circuits 14 and 17 . Some of these signals control the data transfers between the main memory 11 and the sending 15 and receiving 18 circuits, as well as the operation of the circuits involved in the sending and receiving of data. Other ones of these signals represent operating states of the different circuits, relating to the transfer of data. Some of these signals are identical to signals used in the first embodiment.

The automatic control device 19 receives signals DEM E and DEM R from the circuits 15 and 18 respectively. The signal DEM E is an authorisation to send data when it goes to the high state. The signal DEM R indicates that a reception of data is detected by the circuit 18 when it goes to the high state.

The automatic control device 19 transmits signals DC E and DC R to the direct access circuit 12 . The signal DC E is a request for a direct access channel for sending data, between the main memory 11 and the buffer memory 13 , when it goes to the high state. The signal DC R is a request for a direct access channel for receiving data, between the memory 16 and the main memory 11 , when it goes to the high state.

The direct access circuit 12 transmits signals ACQ E and ACQ R to the automatic control device 19 in response to the signals DC E and DC R respectively. The signal ACQ E is an acknowledgement of a request for a direct access channel for sending. When the signal ACQ E goes to the low state, this means that the direct access circuit 12 executes the transfer of data between the main memory 11 and the buffer memory 13 . The signal ACQ R is an acknowledgement of a request for a direct access channel for receiving. When the signal ACQ R goes to the low state, this means that the direct access circuit 12 performs the transfer of data between the memory 16 and the main memory 11 .

The automatic control device 19 transmits signals SIM E and SIM R respectively to the buffer memories 13 and 16 . The signal SIM E indicates that an octet is presented at the input of the buffer memory 13 when it goes to the high state. The signal SIM R indicates that an octet is presented at the input of the memory 16 when it goes to the high state.

The buffer memory 13 and the buffer memory 16 transmit respectively signals IR E and IR R to the automatic control device 19 . The signal IR E indicates that the buffer memory 13 is ready to receive data. The signal IR R indicates that the buffer memory 16 is ready to receive data.

The automatic control device 19 transmits signals SOM E and SOM R respectively to the buffer memories 13 and 16 . The signal SOM E is an instruction to transmit an octet from the buffer memory 13 to the error correction circuit 14 , when it goes to the high state. The signal SOM R is an instruction to transmit an octet from the memory 6 to the memory 11 , via the direct access circuit 12 , when it goes to the high state.

The automatic control device 19 transmits signals SOF E and SOF R respectively to the error correction circuits 14 and 17 . The signal SOF E is an instruction to transmit an octet from the error correction circuit 14 to the sending circuit 15 . The signal SOF R is an instruction to transmit an octet from the error correction circuit 17 to the buffer memory 16 .

The buffer memory 13 transmits a signal OR E to the automatic control device 19 . The signal OR E indicates that the buffer 13 contains data to be sent when it is at the high state.

The buffer memory 16 transmits a signal OR R to the automatic control device 19 . The signal OR R indicates that the memory 16 contains data being received when it is at the high state.

The automatic control device 9 transmits signals SIF E and SIF R respectively to the error correction circuits 14 and 17 . The signal SIF E indicates that an octet is presented at the input of the error correction circuit 14 , when it is at the high state. The signal SIF R indicates that an octet is presented at the input of the error correction circuit 17 , when it is at the high state.

The automatic control device 19 transmits signals ST E and ST R respectively to the error correction circuits 14 and 17 . The signal ST E indicates the start of a block of useful data presented at the error correction circuit 14 when it goes to the high state. The signal ST R indicates the start of a block of useful data presented at the error correction circuit 17 when it goes to the high state.

The error correction circuits 14 and 17 transmit respectively signals OUT E and OUT R to the automatic control device 19 . The signal OUT E indicates that the error correction circuit 14 has useful octets present at an output, or that these useful octets are in the course of transmission to the sending circuit 15 , when it is at the high state. When the signal OUT E is at the low state, it indicates either that redundant octets are in the course of transmission to the sending circuit 15 , or that no octet is in the course of transmission between the circuit 14 and the circuit 15 .

Similarly, the signal OUT R indicates that the error correction circuit 17 has useful octets present at its output, and that useful octets are in the course of transmission to the memory 16 when it is at the high state. When the signal OUT E is at the low state, it indicates either that redundant octets are present at the output of the circuit 17 , or that no octet is in the course of transmission between the circuit 17 and the circuit 16 .

The sending and receiving of data are independent of each other and can function equally well in full duplex or half-duplex.

The operating of the device of FIG. 7 will now be described by algorithmes which can be, totally or partially, memorised in any storage medium SM 2 capable of cooperating with the control device 19 .

This storage medium is integrated or can be detachably mountable on the data sending and receiving device. For example, the storage medium is a floppy disk, or a CD-ROM.

The sending of data will be dealt with first of all, described with reference to FIGS. 10, 11 , 12 and 13 . The sending of data entails data transfers between the main memory 11 , the direct access circuit 12 , the buffer memory 13 , the error correction circuit 14 and the sending circuit 15 . These transfers are controlled by the automatic controller 19 and are described in the form of algorithms.

The data transfers necessary for the sending of data and described with reference to FIGS. 11, 12 and 13 can be effected simultaneously, whilst being asychronous.

FIG. 11 depicts an algorithm for the transfer of data between the main memory 11 and the buffer memory 13 , via the direct access circuit 12 . This algorithm includes steps E 101 to E 105 and is implemented by the automatic control device. Steps E 01 to E 105 are run through cyclically, and the automatic control device 19 goes from one step to the following at each switching of an internal clock.

Step E 101 is the initiation of the data transfer, at which the signal DC E requesting a direct access channel is at the low state, that is to say the automatic control device 19 is not requesting a direct access channel to the direct access circuit 12 . The signal SIM E is also at the low state, which means that no octet is presented at the input of the buffer memory 13 by the direct access circuit 12 .

The following step E 102 is a logic test on the values of the signals DEM E and IR E in order to verify that they are both at the high state. The signal DEM E at the high state indicates that the circuit 15 is enabling a sending of data, and the signal IR E at the high state indicates that the buffer memory 13 is not full and can receive data. As long as these signals are not both at the high state, step E 102 is reiterated.

When the signals DEM E and IR E both go to the high state, the automatic control device 19 transmits the signal DC E at the high state to the direct access circuit 12 , at step E 103 , in order to request a direct access channel.

The following step E 104 is a test of the logic value of the signal ACQ E in order to determine whether the direct access circuit 12 is in the process of effecting the requested transfer. As long as the signal ACQ E is at the high state, step E 104 is looped back on itself; when the signal ACQ E goes to the low state, this means that the direct access circuit 12 effects the transfer of data between the main memory 11 and the buffer memory 13 . In the latter case, step E 104 is followed by step E 105 .

At step E 105 , the automatic control device cancels its request for a direct access channel by transmitting the signal DC E at the low state to the direct access circuit 12 . The automatic control device 19 transmits the signal SIM E at the high state to the buffer memory 3 in order to indicate to it that the data are being presented to it at its input. Consquently the data transmitted by the direct access circuit are stored in the buffer memory 13 .

FIG. 12 depicts an algorithm for the transfer of data between the buffer memory 13 and the error correction circuit 14 . This algorithm includes steps E 110 to E 116 , which are run through cyclically. The automatic control device 19 goes from one step to the next at each switching of an internal clock, which can be different from that used for the algorithm in FIG. 11 .

The algorithm for the transfer of data between the buffer memory 13 and the error correction circuit 14 successively controls a transfer of the first predetermined number N of useful data words, and an interruption of the transfer of the data words for a period of interruption corresponding to the period which will be necessary for transferring the second predetermined number K of additional words.

The purpose of the initialisation step E 110 is:

to set to zero a counter CPT E which counts the octets transmitted between the buffer memory 13 and the error correction circuit 14 ,

to transmit the signal SOM E at the low state to the buffer memory 13 in order to signify an absence of an instruction to transmit an octet from the buffer memory 13 to the circuit 14 ,

to transmit the signals SIF E and ST E at the low state to the correction circuit 14 , in order to signify that no octet is presented at the input of the circuit 14 .

The following step E 111 is a logic test of the signals DEM E and OR E . When these signals are both at the high state, this means that a sending request has been transmitted to the automatic control device 19 , and that the buffer memory 13 contains data to be transmitted. As long as these two conditions are not verified, step E 111 is reiterated.

When these two conditions are verified, step E 111 is then followed by step E 112 , during which the counter CPT E is incremented by one unit, and the automatic control device 19 transmits the signal SOM E at the high state to the buffer memory 13 in order to indicate to it an instruction to transmit an octet from the buffer memory 13 to the circuit 14 , and transmits the signals SIF E and ST E at the high state to the error correction circuit 14 , in order to signify that an octet is presented at the input of the circuit 14 , and that this octet constitutes the start of a useful data block.

At the following step E 113 , the counter CPT E is incremented by one unit and the automatic control device 19 transmits the signal SOM E at the high state to the buffer memory 13 in order to indicate to it an instruction to transmit an octet from the buffer memory 13 to the circuit 14 , and transmits the signal SIF E at the high state and the signal ST E at the low state to the error correction circuit 14 , in order to indicate that an octet is presented at the input of the circuit 14 , and that this octet does not constitute the start of a useful data block.

The following step E 114 is a test for verifying whether the counter CPT E of octets transmitted to the error correction circuit 14 has reached the predetermined value N, corresponding to the number of useful octets present in an error correction code word. As long as the value N is not reached, step E 113 is repeated.

Steps E 112 and E 113 allow the transfer of useful octets OC 1 to OC N between the memory 13 and the error correction circuit 14 .

When N useful octets have been transmitted to the error correction circuit 14 , step E 114 is followed by step E 115 , at which the counter CPT E is incremented by one unit, and the automatic control device 19 transmits the signal SOM E at the low state to the buffer memory 13 in order to indicate to it an absence of an instruction to transmit an octet from the buffer memory 13 to the circuit 14 , and transmits the signal SIF E at the high state and the signal ST E at the low state to the error correction circuit 14 , in order to indicate that an octet is presented at the input of the circuit 14 , and that this octet does not constitute the start of a useful data block.

The octets transmitted to the circuit 14 during step E 115 are not useful octets, and their value has no importance. These octets are padding octets Or 1 , to Or K , which will be replaced subsequently by the redundant octets OR 1 , to OR K determined by the error correction circuit 14 .

The following step E 116 is a test for verifying the value of the counter CPT E . As long as the counter CPT E has not reached the value N+K, step E 115 is repeated.

When the counter CPT E has reached the value N+K, a sufficient number of octets have been transmitted to enable the error correction circuit 14 to form an error correction code word MC. Step E 116 is then followed by step E 110 . Steps E 110 to E 116 are repeated as long as there remain any octets in the buffer memory 13 to be transmitted to the error correction circuit 14 (signal OR E at the high state).

FIG. 13 depicts an algorithm for the transfer of data between the error correction circuit 14 and the sending circuit 15 . This algorithm includes steps E 120 to E 123 , which are run through cyclically by the automatic control device. The automatic control device 19 goes from one step to the following at each switching of an internal clock, which can be different from those used for the algorithms of FIGS. 11 and 12.

Step E 120 is an initialisation at which the control circuit 19 sets the signal SOF E to the low state, in order to indicate to the error correction circuit 14 not to transmit data to the sending circuit 15 .

The following step E 121 is a test for verifying the value of the signals DEM E and OUT E . As long as the signals DEM E and OUT E are not both at the high state, step E 121 is repeated.

When the signals DEM E and OUT E are both at the high state, this means that a request to send data has been transmitted to the control circuit 19 , and that the error correction circuit 14 contains data to be transmitted. Step E 121 is then followed by step E 122 , at which the automatic control device 19 transmits the signal SOF E at the high state to the error correction circuit 4 in order to indicate to it to transmit an octet to the sending circuit 15 .

The following step E 123 is a test for verifying the value of the signals DEM E and OUT E . As long as the signals DEM E and OUT E are not both at the low state, step E 122 is repeated in order to transmit an octet to the sending circuit 15 .

When the signals DEM E and OUT E are both at the low state, this means that there is no longer any request to send data which is transmitted to the control circuit 19 , and that the error correction circuit 14 does not contain any data to be transmitted. Step E 123 is then followed by the initialisation step E 120 .

The reception of data will now be dealt with, described with reference to FIGS. 10, 14 , 15 and 16 . The reception of data entails data transfers between the reception circuit 18 , the error correction circuit 17 , the memory 16 , the direct access circuit 12 and the main memory 11 . These transfers are controlled by the automatic control device 19 and are described in the form of algorithms.

The data transfers described with reference to FIGS. 14, 15 and 16 can be performed simultaneously, whilst being asynchronous.

FIG. 14 depicts the algorithm for the transfer of data between the data reception circuit 18 and the error correction circuit 17 . This data transfer entails exchanges of logic signals between the automatic control device 19 and the error correction circuit 17 . The algorithm includes steps E 130 to E 135 , which are run through cyclically by the automatic control device. The algorithm goes from one step to the following at each switching of an internal clock.

to set to zero a counter CPT R , which counts the octets which enter the error correction circuit 17 ,

to transmit the signal SIF R at the low state to the error correction circuit 17 , in order to indicate that no octet is presented at the input of the error correction circuit 17 ,

to transmit the signal ST R at the low state to the error correction circuit 17 , in order to indicate that the first octet of a block is not being transmitted to the error correction circuit 17 .

The following step E 131 is a test for verifying the value of the signal DEM R . As long as the signal DEM R remains at the low state, no reception of data is detected and step E 131 is then repeated.

When the signal DEM R goes to the high state, a reception of data is detected, and step E 131 is followed by step E 132 .

At step E 132 , the counter CPT R is incremented by one unit, and the automatic control device 19 transmits the signals SIF R and ST R at the high state to the error correction circuit 17 , in order to indicate to it that the reception circuit is transmitting an octet to it, and that this octet is the start of a useful data block.

At the following step E 133 , the counter CPT R is incremented by one unit, and the automatic control device 19 transmits the signals SIF R and ST R at the high and low states respectively, to the error correction circuit 17 , in order to indicate to it that the reception circuit is transmitting an octet to it, and that this octet is not the start of a useful data block.

Step E 133 is followed by step E 134 , which is a test for verifying whether the counter CPT R has reached the value N+K. As long as this value is not reached, step E 133 is repeated, so as to transmit an error correction code word MC to the error correction circuit 17 .

When the counter CPT R reaches the value N+K, step E 134 is followed by step E 135 , at which the value of the signal DEM R is tested. If the signal DEM R is at the high state, this means that there are still data being received by the reception circuit 18 , and step E 135 is followed by step E 132 in order to process another error correction code word.

If the signal DEM R is at the low state, this means that there are no more data being received by the reception circuit 18 , and step E 135 is followed by step E 130 .

FIG. 15 depicts an algorithm for the transfer of data between the error correction circuit 17 and the buffer memory 16 . This algorithm includes steps E 140 to E 145 , which are run through cyclically. The algorithm goes from one step to the following at each switching of the internal clock, which can be different from that used for the algorithm of FIG. 14 .

The algorithm for the transfer of data between the error correction circuit 17 and the buffer memory 16 controls successively a transfer of the first predetermined number N of useful data words, and an interruption of the transfer of the data words for a period of interruption corresponding to the period which would be necessary for transferring the second predetermined number K of additional words.

to set to zero a counter CP 2 R , which counts the octets transmitted from the error correction circuit 17 to the buffer memory 16 ,

to transmit the signal SIM R at the low state to the buffer memory 16 , in order to indicate to it that no octet is being supplied to it as an input,

to transmit the signal SOF R at the low state to the error correction circuit 17 in order to indicate to it not to transmit any octet to the buffer memory 16 .

The following step E 141 is a test of the value of the signals OUT R , DEM R and IR R .

As long as the signals OUT R , DEM R and IR R are not all three at the high state, step E 141 is repeated.

When these three signals are at the high state, this means respectively that:

useful octets are present at the output of the error correction circuit 17 to the buffer memory 16 ,

a data reception is detected,

the buffer memory 16 is not full and can consequently receive data.

When these three conditions are verified, step E 141 is followed by step E 142 , at which the counter CP 2 R is incremented by one unit, the automatic control device 19 transmits the signal SIM R at the high state to the buffer memory 16 , in order to indicate to it that an octet is being presented to it as an input, and the automatic control device 19 transmits the signal SOF R at the high state to the error correction circuit 17 in order to control the transmission of an octet between the error correction circuit 17 and the buffer memory 16 .

The following step E 143 is a test for verifying whether the counter CP 2 R has reached the value N. As long as this is not the case, step E 142 is repeated.

When the counter CP 2 R has reached the value N, this means that the error correction circuit has transmitted the N useful octets OC 1 to OC N of an error correction code word MC to the buffer memory 16 . Step E 143 is then followed by step E 144 , at which the counter CP 2 R is incremented by one unit, the automatic control device 19 transmits the signal SIM R at the low state to the buffer memory 16 in order to instruct it not to receive an octet, and the automatic control device 19 transmits the signal SOF R at the high state to the error correction circuit 17 in order to control the transmission of an octet between the error correction circuit 17 and the buffer memory 16 .

At step E 144 , the redundant octets OR 1 , to OR K of the error correction code word MC which leave the circuit 17 are not stored in the buffer memory 16 .

The following step E 145 is a test on the value of the counter CP 2 R , in order to repeat step E 144 for the K redundant octets of the error correction code word. Thus, as long as the counter CP 2 R has not reached the value N+K, step E 144 is repeated, and when this value is reached step E 145 is followed by step E 140 .

FIG. 16 depicts an algorithm for the transfer of data between the buffer memory 16 and the main memory 11 , via the direct access circuit 12 . The algorithm includes steps E 150 to E 154 , which are run through cyclically by the automatic control device. The algorithm goes from one step to the following at each switching of an internal clock, which can be different from those used for the algorithms of FIGS. 14 and 15.

the signal DC R is transmitted at the low state to the direct access circuit 12 in order to indicate to it that there are no data to be transferred from the buffer memory 16 to the main memory 11 , and

the signal SOM R is transmitted at the low state to the buffer memory 16 in order to instruct it not to transmit an octet to the direct access circuit 12 .

The following step E 151 is a test on the value of the signals DEM R and OR R . As long as the signals DEM R and OR R are not both at the high state, step E 151 is repeated.

When the signals DEM R and OR R are both at the high state, this means that a data reception is detected and that the buffer memory 16 contains data to be transmitted to the main memory 11 . Step E 151 is then followed by step E 152 , at which the automatic control device 19 transmits the signal DC R at the high state to the direct access circuit in order to demand from it a direct access channel to the main memory 11 .

The following step E 153 is a test on the value of the signal ACQ R , in order to determine whether the direct access circuit is executing the transfer of data between the buffer memory 16 and the main memory 11 . As long as the response is negative, that is to say the signal ACQ R is at the high state, step E 153 is repeated.

When the signal ACQ R goes to the low state, step E 153 is followed by step E 154 , at which the signal SOM R is transmitted at the high state to the buffer memory 16 , in order to instruct it to transmit the octets to the direct access circuit 12 .

When the data have been transferred from the buffer memory 16 to the main memory 11 , step E 154 is followed by step E 150 .

Naturally the present invention is in no way limited to the embodiments described and depicted, but quite the contrary encompasses any variant within the capability of persons skilled in the art.