High speed parallel adder

1. Field of the Invention

The present invention relates to a parallel adder, and in particular, to a parallel adder that performs high speed operations.

2. Background of the Related Art

FIG. 1A is a block diagram illustrating a related art ripple carry type adder in which a carry generated by a lower full adder is inputted as an additional input signal of an upper full adder, which is adjacent the a lower full adder. As shown in FIG. 1A, in a first full adder FA 10 , input signals A 0 , B 0 and a carry input signal C in are added to output a sum signal S 0 . A carry signal C 0 is output from the first full adder FA 10 to be an input signal for a second full adder FA 11 . The second full adder FA 11 adds input signals A 1 , B 1 , and the carry input signal C 0 to output a sum signal S 1 . The carry signal C 1 is inputted to a third full adder FA 12 as an input signal. The above-described processes are performed as many times as the prescribed number of bits.

FIG. 1B is a block diagram illustrating a related art carry selection type adder. In an adder RCA 21 , on the assumption that there is a carry signal, an addition operation is performed. In an adder RCA 22 , on the assumption that there is not a carry signal, an addition operation is performed. As a result of the actual addition by an adder RCA 11 , the addition result of either the adder RCA 21 or the adder RCA 22 is selected and outputted through a multiplexor MUX. The addition result is selected based on whether the carry signal from the adder RCA 11 is present.

In other words, in the adder RCA 11 , four bit input signals (A 0 , B 0 ), (A 1 , B 1 ), (A 2 , B 2 ) and (A 3 , B 3 ) are added to output the carry input signal C in and four bit sum output signals S 0 through S 3 . Additionally, in the adder RCA 21 , on the assumption that there is a carry signal C in (C in =1), four bit input signals (A 4 , B 4 ), (A 5 , B 5 ), (A 6 , B 6 ), (A 7 , B 7 ) and a carry input signal (C in ) are added to output four bit sum output signals S 4 through S 7 . In the adder RCA 22 , on the assumption that there is not a carry signal C in (C in =0), four bit input signals (A 4 , B 4 ), (A 5 , B 5 ), (A 6 , B 6 ), (A 7 , B 7 ) and a carry input signal C in (C in =0) are added to output and four bit sum output signals S 4 through S 7 .

When the actual addition is performed by the adder RCA 11 , the carry output signal C out having the value “1” may be generated, or the carry output signal C out may not be generated, so that the value thereof may be “0”. When the array output signal C out is generated, the multiplexor MUX is controlled in accordance with the carry output signal (C out =1), and the sum output signal of the adder RCA 21 is selected and outputted. When the carry output signal C out is not generated, the multiplexor MUX is controlled in accordance with the carry output signal (C out =0), and the sum output signal from the adder RCA 22 is selected and outputted.

FIG. 2A is a circuit illustrating a related art full adder. In FIG. 2A, when input signals A and B are both high level (i.e., a logic value of “1”) and a carry signal C is high level or “1”, an OR-gate OR 1 outputs “1”, and an AND-gate AD 1 outputs “1”. In addition, a NOR-gate NOR 1 outputs “0” irrespective of the output from an AND-gate AD 2 . The output value “0” from the NOR-gate NOR 1 is inverted to “1” by an inversion buffer B 1 , and the carry signal is outputted as “1”.

FIG. 2B is a detailed circuit diagram illustrating a related art full adder. In FIG. 2B, when input signals A and B are both “1”, and a carry signal C is “1”, PMOS transistors PM 1 -PM 4 are turned off. Thus, “0” is outputted from a node N 1 . The outputted value “0” from the node N 1 is inverted to “1” by an inversion buffer B 2 , and a carry signal is outputted as “1”.

In addition, a PMOS transistor PM 9 is turned on in accordance with a value “0” outputted from the node N 1 . Since PMOS transistors PM 6 -PM 8 and PMOS transistors PM 10 -PM 12 are all turned off, “0” is outputted from common nodes N 2 and N 3 . The outputted value “0” from the node N 3 is inverted to “1” by the inversion buffer B 1 , and the sum is outputted as “1”.

FIG. 3A is a diagram illustrating an output timing of a related art ripple type adder. As shown in FIG. 3A, in a full adder FA 10 , input signals A 0 and B 0 and a carry input signal C in are added, and a delay time of τc is generated until a carry output signal C 0 is generated. In a full adder FA 11 , input signals A 1 and B 1 and a carry input signal (C in =C 0 ) are added, and a delay time of τc is generated until the carry output signal C 1 is generated. Accordingly, a total delay time of 2τc is generated before the carry output signal C 1 .

Since the delay time of τc is generated from each full adder, a total delay time of 8τc is generated by an 8 bit ripple carry type parallel adder. In other words, since an addition operation is performed in order by the upper full adder after a carry output signal is generated by the preceding lower full adder, a relatively large amount of delay time (a processing time) is required.

FIG. 3B is a diagram illustrating an output timing of a related art carry selection type adder. As shown in FIG. 3B, in the RCA 11 , four bits input signals (A 0 , B 0 ), (A 1 , B 1 ), (A 2 , B 2 ), (A 3 , B 3 ) and a carry input signal C in are added, and a delay time of 4τc is generated until the carry output signal C out is generated. However, since the remaining addition operations are performed by the adders RCA 21 and RCA 22 , a no additional delay time is required. A delay time of τc for a selection operation of the multiplexor MUX is added in accordance with a carry output signal C out from the adder RCA 11 . Thus, a total delay time of 5τc is generated.

The related art adders have various disadvantages. As described above, in the ripple carry type adder, since the addition operation is performed sequentially by the upper adder after a carry output signal is generated by the lower adder, the delay time is generated proportionally to the number of output bits. In the carry selection type parallel adder, since the upper adder is arranged in parallel, it is possible to slightly reduce the delay time. In other words, when a carry output is outputted from the lower adder, a predetermined result value is selected and outputted in accordance with the actual addition operation. However, the surface of the parallel adder is necessarily increased due to a laminated structure of the system.

An object of the present invention to provide a parallel adder that overcomes at least the problems and disadvantages in the related art.

Another object of the present invention to provide a parallel adder that generates a carry signal more rapidly.

A further object of the present invention is to provide a parallel adder having a reduced size/layout.

A further object of the present invention is to provide a parallel adder that selects a pass transistor after passing a carry signal through the NAND-gate/NOR-gate to reduce a layout surface when generating a sum output signal.

Still another object of the present invention is to provide a parallel adder for a digital signal processor (DSP).

To achieve the above objects, features and/or advantages in whole or in part, there is provided a parallel adder that includes a first full adder including a logic combination unit for NORing and NANDing input signals and for generating a control signal, a buffer for inverting an inverted carry input signal in accordance with the control of the logic combination unit, a carry output unit for generating a carry signal in accordance with the control of the logic combination unit and for outputting the output signal from the buffer as a carry signal, an output controller for logically combining the output signal from the logic combination unit and for generating a control signal, and a sum output unit controlled by the sum output controller for receiving the inverted carry signal and for generating a sum output signal, and a second full adder including a logic combination unit, a buffer, and a carry output unit for receiving inverted input signals from the inverters and a carry input signal from a first full adder and for generating an inverted carry output signal, a sum output controller having the same construction as the sum output controller, and a sum output unit for receiving the carry input signal and for generating a sum output signal in accordance with the control of the sum output controller, wherein the first and second full adder are formed in a multiple structure.

The present invention may be achieved in a whole or in parts by a parallel adder including a plurality of full adders, wherein each full adder includes a logic combination unit that performs logical operations between input signals to generate a first control signal, a carry output unit receiving a carry input signal to generate a carry output signal based on the first control signal and a sum output controller for logically combining the first control signal to generate a second control signal and generating a sum output signal based on the second control signal and the carry input signal.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.

The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:

FIG. 1A is a block diagram illustrating a related art ripple carry type adder;

FIG. 1B is a block diagram illustrating a related art carry selection type adder;

FIG. 2A is a circuit diagram illustrating a related art full adder;

FIG. 2B is a circuit diagram illustrating another related art full adder;

FIG. 3A is a diagram illustrating an output timing of a related art ripple type adder;

FIG. 3B is a diagram illustrating an output timing of a related art carry selection type adder;

FIG. 4 is a block diagram illustrating a preferred embodiment of a parallel adder according to the present invention;

FIG. 5 is a circuit diagram illustrating an (n+1)-th full adder of FIG. 4;

FIG. 6 is a circuit diagram illustrating an n-th full adder of FIG. 4;

FIGS. 7A-7D are diagrams illustrating signal waveforms of the full adder circuit of FIG. 5; and

FIGS. 8A-8D are diagrams illustrating signal waveforms of the full adder circuit of FIG. 6 .

A first preferred embodiment of a parallel adder according to the present invention will now be described. As shown in FIG. 4, a first full adder 41 is coupled for receiving a carry input signal /CIN, generating a carry output signal COUT from an inverter and a NAND-gate/NOR-gate and a sum output signal SUM by controlling a pass transistor after being passed through the NAND-gate/NOR-gate. A second full adder 42 is coupled for receiving a carry input signal CIN from the first adder 41 , generating a carry output signal /COUT through the inverter and the NAND-gate/NOR-gate, receiving input signals /INA and /INB from inverters I A1 , and I B1 , and generating a sum output signal SUM for controlling the pass transistor after being passed through the NANDgate/NOR-gate. Full adders 43 through 48 are coupled similarly to the above-described first and second full adders 41 and 42 .

FIG. 5 is a circuit diagram illustrating an (n+1)-th full adder (e.g., the first full adder 41 ) of FIG. 4 . As shown in FIG. 5, a logic combination unit 51 is coupled for NORing and NANDing input signals INA and INB and for generating a control output signal based on the NORing operation. A buffer 52 is coupled for inverting and outputting a carry input signal /CIN based on control by the logic combination unit 51 . A carry output unit 53 is coupled for generating a carry output signal COUT based on control by the logic combination unit 51 and the output signal from the buffer 52 . A sum output controller 54 is coupled for logically combining the output signal from the logic combination unit 51 and outputting a control output signal. A sum output unit 55 is coupled for receiving a carry input signal /CIN and for generating a sum output signal SUM in accordance with control by the sum output controller 54 .

FIG. 6 is a circuit diagram illustrating an n-th full adder of FIG. 4 according to the present invention. Different from the operation of FIG. 5, in the n-th full adder (e.g., the second full adder 42 ), input signals /INA and /INB are inputted through inverters I AN and I BN (e.g., the inverters I A1 and I B1 ), and a carry input signal CIN is inputted through the preceding full adder. In addition, the n-th full adder is similar to the (n+1)-th full adder except for a sum output unit 65 . In other words, the second full adder 42 is similar to the first full adder 41 except for the sum output unit 65 .

Operations and effects of the first preferred embodiment of the parallel adder according to the present invention will now be explained with reference to FIGS. 7A-8D. First, addition operations of the first full adder 41 will be explained with reference to FIG. 5 . For an example, “1” is inputted to external input terminals A 0 and B 0 , respectively, and is then inputted to the input terminals INA and INB of the first full adder 41 . Further, on the assumption that a carry signal is not externally supplied thereto, “1” is supplied to the carry input terminal /CIN of the first full adder 41 .

Since “0” is outputted from the NOR-gate NOR 11 and is inputted to the gates of the PMOS transistor PM 11 and the NMOS transistor NM 13 , the PMOS PM 11 is turned on and the NMOS transistor NM 13 is turned off. In addition, the PMOS transistor PM 12 and the NMOS transistor NM 11 , which work as an inverter based on the carry input signal /CIN, are turned off and turned on, respectively. “0” is outputted from the NAND-gate ND 11 in accordance with input signals INA and INB, and the NMOS transistor NM 12 . is turned off, and the PMOS transistor PM 13 is turned on. Thus, an electrode voltage Vcc is supplied to the carry output terminal COUT through the PMOS transistor PM 13 . In other words, “1” is outputted from the carry output terminal COUT.

Meanwhile, the carry input signal /CIN is directly outputted to the gate of the NMOS transistor NM 14 . The carry input signal /CIN is inverted to “0” by the inverter I 12 and supplied to the gate of the PMOS transistor PM 14 . Thus, the PMOS transistor PM 14 and the NMOS transistor NM 14 are both turned on to become an output ready state. “0” outputted from the NOR-gate NOR 11 is inverted to “1” by the inverter I 11 and supplied to one side of the NAND-gate ND 12 . The NAND-gate ND 11 output “0” is supplied to the other side of the NAND-gate ND 12 , which outputs “1”.

The PMOS transistor PM 15 is turned off in accordance with “1” outputted from the NAND-gate ND 12 , and the NMOS transistor NM 15 is turned on. The “1” supplied through the PMOS transistor PM 14 (a pass transistor) and the NMOS transistor NM 14 , is inverted to “0”by the inverter I 13 and supplied to the sum output terminal SUM.

As a result, under the above-described operations, a carry output signal COUT of “1” is generated by the first full adder 41 . The carry output signal COUT of “1” is supplied to the second full adder 42 as a carry input CIN. The second full adder 42 recognizes that there is a carry input signal. Further, the sum output SUM “0” is outputted from the first full adder 41 and is supplied to the sum output terminal SUM 0 .

Addition operations of the second full adder 42 are similar to the first full adder 41 and will be described with reference to FIG. 6 . First, “1” is respectively supplied to the external input terminals A 1 and B 1 , inverted to “0” by inverters I A1 and I B1 and supplied to the input terminals /INA and /INB of the second full adder 42 . A carry signal is externally supplied, and “1” is supplied to the carry input terminal CIN of the second full adder 42 continuing the example above, from the first full adder 41 .

Since “1” is outputted from the NOR-gate NOR 21 and supplied to the PMOS transistor PM 21 and the NMOS transistor NM 23 , the PMOS transistor PM 21 is turned off and the NMOS transistor NM 23 is turned on. In addition, the PMOS transistor PM 22 and the NMOS transistor NM 21 , which work as an inverter based on a carry input signal CIN, are turned off and turned on, respectively. In addition, “1” is outputted from the NAND-gate ND 21 in accordance with “0” respectively supplied to the input terminals /INA and /INB. Thus, the NMOS transistor NM 22 is turned on, and the PMOS transistor PM 23 is turned off.

Therefore, the terminal electrode Vcc is not supplied to the carry output terminal /COUT. Since the ground voltage Vss is supplied to the carry output terminal /COUT through the NMOS transistor NM 23 , “0” is outputted from the carry output terminal /COUT. Accordingly, the carry output terminal /COUT becomes active.

Meanwhile, the carry input CIN is directly supplied to the gate of the PMOS transistor PM 24 , which turns off. Further, the carry input CIN is inverted to “0” by the inverter 122 and the NMOS transistor NM 24 is turned off. The “1” outputted from the NOR-gate NOR 21 is inverted to “0” by the inverter 121 and supplied to one side of the NAND-gate ND 22 . The “1” outputted from the NAND-gate ND 21 is supplied to the other side of the NAND-gate ND 22 . Thus, “1” is outputted from the NAND-date ND 22 .

The “1” outputted from the NAND-gate ND 22 is directly supplied to the gate of the PMOS transistor PM 25 and to the gate of the NMOS transistor NM 25 . Thus, the PMOS transistor PM 25 and the NMOS transistor NM 25 are turned off and turned on, respectively. The carry input signal CIN is inverted to “0” by the inverter I 22 , and becomes a ready state by the NMOS transistor NM 25 . When the NMOS transistor NM 25 is turned on, because “0” is supplied to the input terminal of the inverter I 23 , “1” is outputted from the inverter I 23 and supplied to the sum output terminal SUM.

Under the above-described conditions, the carry output /COUT of “0” is generated by the full adder 42 and is supplied to the carry input /CIN of the third full adder 43 . Therefore, the third full adder 43 recognizes that there is a carry input signal, and the sum output signal SUM is outputted from the second full adder 42 and is supplied to the sum output terminal SUM 1 .

The first and second full adders 41 and 42 operate complementarily. Further, the full adders 43 , 45 , and 47 operate like the full adder 41 , and the full adders 44 , 46 , and 48 operate like the full adder 42 to generate sum output signals SUM 0 -SUM 7 and the carry output signal /COUT as shown in FIG. 4 .

FIGS. 7A-7D are exemplary waveforms illustrating a simulation result of a full adder circuit of FIG. 5 . When the input signals INA and /INA are supplied as shown in FIG. 7 A and the carry input signal /CIN is supplied as shown in FIG. 7B, the carry input signal COUT is generated as shown in FIG. 7 C. Further, the sum output /SUM is generated as shown in FIG. 7 D.

FIGS. 8A-8D are exemplary waveforms illustrating a simulation result of a full adder circuit of FIG. 6 . When the input signals /INA and /INB are inputted as shown in FIG. 8 A and the carry input signal CIN is supplied as shown in FIG. 8B, the carry output signal /COUT is generated as shown in FIG. 8 C. Further, the sum output signals SUM is generated as shown in FIG. 8 D.

As described above, the first preferred embodiment of the parallel adder according to the present invention has various advantages. The first preferred embodiment can increase processing speed by three times compared to the related art ripple type adder of eight bits by generating a carry output signal by using an inverter and a NAND-gate/NOR-gate and selecting a pass transistor through the NAND-gate/NOR-gate to generate a sum output signal, which decreases the layout surface to approximately a size of the related art ripple carry adder. Thus, the parallel adder is adaptable to a filter and a multiplexor of a digital signal processor.

The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.