Diced semiconductor wafer for mosaic solar cell fabrication

The present application is related to U.S. patent application Ser. No. 29/768,304 filed simultaneously herewith.

FIG. 1 is a top perspective view of a diced semiconductor wafer for a mosaic solar cell fabrication showing our new design;

FIG. 2 is a top plan view the semiconductor wafer of FIG. 1 and the unclaimed environment of the semiconductor wafer which has been scribed to produce the four mosaic solar cell elements shown in the preceding Figure. The broken line represents unclaimed environment structure only and forms no part of the claimed design.

FIG. 3 is a bottom plan view thereof:

FIG. 4 is a front elevation thereof;

FIG. 5 is a rear elevation view thereof; and

FIG. 6 is a left elevation view thereof; and,

FIG. 7 is a right elevation view thereof.