Manufacturing method of pillar-shaped semiconductor device

The present application is a Continuation application of PCT/JP2020/043750, filed Nov. 25, 2020, the entire contents of which are incorporated herein by reference.

The present invention relates to a manufacturing method of a pillar-shaped semiconductor device.

In recent years, three-dimensional transistors are used in LSI (Large Scale Integration). Among such three-dimensional transistors, an SGT (Surrounding Gate Transistor) which is a pillar-shaped semiconductor device is garnering attention as a semiconductor element that provides a highly-integrated semiconductor device. In addition, there is a need for higher integration and higher performance of semiconductor devices having an SGT.

With an ordinary planar MOS transistor, a channel extends in a horizontal direction along an upper surface of a semiconductor substrate. In contrast, a channel of an SGT extends in a vertical direction relative to the upper surface of the semiconductor substrate (for example, refer to Japanese Patent Laid-Open No. H2-188966 and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)). Therefore, an SGT enables further densification of a semiconductor device as compared to a planar MOS transistor.

FIGS. 5 A and 5 B show schematic structural diagrams of an N channel SGT. FIG. 5 A represents a sectional view and FIG. 5 B represents a plan view. N + layers 121 a and 121 b being semiconductor layers containing a high concentration of donor impurities of which one becomes a drain when the other becomes a source are formed at upper and lower positions inside a silicon semiconductor pillar 120 (hereinafter, a silicon semiconductor pillar will be referred to as a “Si pillar”) having a P or i (intrinsic) conductivity type. A portion of the Si pillar 120 between the N + layers 121 a and 121 b to become a source and a drain becomes a channel region 122 . A gate insulating layer 123 is formed so as to surround the channel region 122 . A gate conductor layer 124 is formed so as to surround the gate insulating layer 123 . The SGT is constituted of the N + layers 121 a and 121 b to become a source and a drain, the channel region 122 , the gate insulating layer 123 , and the gate conductor layer 124 . The N + layer 121 b and a source wiring metal layer S are connected via a contact hole C opened in an insulation layer 125 on the N + layer 121 b . Accordingly, an occupied area of the SGT in a plan view corresponds to an occupied area of a single source or drain N + layer of a planar MOS transistor. Therefore, a circuit chip having an SGT enables a further reduction in chip size as compared to a circuit chip having a planar MOS transistor.

In addition, there is a problem that has to be overcome when attempting to further reduce the chip size. As shown in FIG. 5 , the contact hole C which connects the source wiring metal layer S and the N + layer 121 b is formed on the Si pillar 120 in a plan view. When the reduction of the chip size advances, a distance between the Si pillar 120 and an adjacent Si pillar decreases. Accordingly, a distance to a contact hole adjacent to the contact hole C in a plan view decreases. Therefore, there is a need for miniaturization and densification of a contact hole formation step.

FIG. 6 shows a circuit diagram of an SRAM (Static Random Access Memory) cell using an SGT. The present SRAM cell circuit includes two inverter circuits. One of the inverter circuits is constituted of a P channel SGT Pc 1 as a load transistor and an N channel SGT Nc 1 as a drive transistor. The other inverter circuit is constituted of a P channel SGT Pc 2 as a load transistor and an N channel SGT Nc 2 as a drive transistor. A gate of the P channel SGT Pc 1 and a gate of the N channel SGT Nc 1 are connected to each other. A drain of the P channel SGT Pc 2 and a drain of the N channel SGT Nc 2 are connected to each other. A gate of the P channel SGT Pc 2 and a gate of the N channel SGT Nc 2 are connected to each other. A drain of the P channel SGT Pc 1 and a drain of the N channel SGT Nc 1 are connected to each other.

As shown in FIG. 6 , sources of the P channel SGTs Pc 1 and Pc 2 are connected to a supply terminal Vdd. Sources of the N channel SGTs Nc 1 and Nc 2 are connected to a ground terminal Vss. Select N channel SGTs SN 1 and SN 2 are arranged on both sides of the two inverter circuits. Gates of the select N channel SGTs SN 1 and SN 2 are connected to a word line terminal WLt. A source and a drain of the select N channel SGT SN 1 are connected to drains of the N channel SGT Nc 1 and the P channel SGT Pc 1 and to a bit line terminal BLt. A source and a drain of the select N channel SGT SN 2 are connected to drains of the N channel SGT Nc 2 and the P channel SGT Pc 2 and to an inverted bit line terminal BLRt. In this manner, a circuit having an SRAM cell is constituted of a total of six SGTs including two load P channel SGTs Pc 1 and Pc 2 , two drive N channel SGTs Nc 1 and Nc 2 , and two select N channel SGTs SN 1 and SN 2 (for example, refer to U.S. Patent Application Publication No. 2010/0219483). In the SRAM cell, the Si pillars of the two load P channel SGTs Pc 1 and Pc 2 are formed in closest proximity to each other. In this case, formation of a contact hole on upper P + layers of the load P channel SGTs Pc 1 and Pc 2 becomes an issue in realizing higher integration of the SRAM cell.

There is a need for higher performance and higher integration in circuits using an SGT.

A manufacturing method of a pillar-shaped semiconductor device according to the present invention includes the steps of:

forming a first impurity layer on a substrate; forming a first semiconductor layer on the first impurity layer; forming a second impurity layer on the first semiconductor layer; forming a first material layer on the second impurity layer; forming a first semiconductor pillar by using the first material layer as a mask to etch the second impurity layer, the first semiconductor layer, and an upper layer of the first impurity layer in this order from top to bottom; forming a gate insulating layer which surrounds the first semiconductor layer of the first semiconductor pillar and a gate conductor layer which surrounds the gate insulating layer; forming a first interlayer insulating layer above an upper surface of the gate conductor layer in an outer circumferential part of a top part of the first semiconductor pillar; forming a second material layer on the first interlayer insulating layer so as to surround side surfaces of the top part of the first semiconductor pillar and the first material layer; forming a second interlayer insulating layer in an outer circumferential part in contact with a side surface of the second material layer; forming a first depression which surrounds the top part of the first semiconductor pillar by using the second interlayer insulating layer as a mask to remove the first material layer and the second material layer; forming a third impurity layer so as to surround the second impurity layer in the top part of the first semiconductor pillar and inside the first depression; forming a first conductor layer made of a metal or an alloy on the third impurity layer; forming a third interlayer insulating layer on the first conductor layer; forming a first band-shaped contact hole which extends in a band shape on the third interlayer insulating layer on the first conductor layer; and forming a first wire conductor layer which connects to the first conductor layer via the first band-shaped contact hole, wherein the first conductor layer protrudes more toward a side of the first wire conductor layer than the first contact hole in a plan view.

The invention described above can further include the steps of:

forming a fourth impurity layer adjacent to the first impurity layer on the substrate; forming the first semiconductor layer on the first impurity layer and the fourth impurity layer; forming the second impurity layer and a fifth impurity layer on the first semiconductor layer; forming a third material layer on the fifth impurity layer; forming the first semiconductor pillar by using the first material layer as a mask to etch the first impurity layer, the first semiconductor layer, and the second impurity layer in this order from top to bottom and, at the same time, forming a second semiconductor pillar by using the third material layer as a mask to etch the fifth impurity layer, the first semiconductor layer, and the fourth impurity layer in this order from top to bottom; forming the gate insulating layer which surrounds the first semiconductor layer of the first semiconductor pillar and the second semiconductor pillar and a gate conductor layer which surrounds the gate insulating layer; forming the first interlayer insulating layer above the upper surface of the gate conductor layer in the outer circumferential part of the top part of the first semiconductor pillar; forming the second material layer on the first interlayer insulating layer so as to surround side surfaces of the top part of the first semiconductor pillar and the first material layer and, at the same time, forming a fourth material layer on the first interlayer insulating layer so as to surround side surfaces of a top part of the second semiconductor pillar and the third material layer; forming the second interlayer insulating layer in an outer circumferential part in contact with side surfaces of the second material layer and the fourth material layer; forming the first depression which surrounds the top part of the first semiconductor pillar and a second depression which surrounds the top part of the second semiconductor pillar by using the second interlayer insulating layer as a mask to remove the first material layer, the second material layer, the third material layer, and the fourth material layer; forming the third impurity layer inside the second depression and, at the same time, forming a sixth impurity layer so as to surround the fifth impurity layer in the top part of the second semiconductor pillar; forming a second conductor layer made of a metal or an alloy on the sixth impurity layer; forming the first band-shaped contact hole on the third interlayer insulating layer on the second conductor layer; and forming the first wire conductor layer which connects the first conductor layer and the second conductor layer via the first band-shaped contact hole, wherein the semiconductor pillar which differs from the first semiconductor pillar and the second semiconductor pillar is not formed in a formation region of the first wire conductor layer in a plan view.

The invention described above can further include the steps of:

forming a third interlayer insulating layer on the first conductor layer, the second conductor layer, and the second interlayer insulating layer;

forming the first band-shaped contact hole which overlaps with a partial region of the first conductor layer and a partial region of the second conductor layer in a plan view on the third interlayer insulating layer; and forming the third wire conductor layer by filling the first band-shaped contact hole, wherein partial regions of the first conductor layer and the second conductor layer protrude more outward than the first band-shaped contact hole in a plan view.

The invention described above can further include the steps of:

forming a first mask material layer which overlaps with partial regions of the first material layer and the third material layer and partial regions of the second material layer and the fourth material layer and which connects the partial regions and forms a cavity in a plan view after forming the second interlayer insulating layer; forming a third depression by using the first mask material layer as a mask to etch the first material layer, the third material layer, the second material layer, the fourth material layer, and the second interlayer insulating layer; forming the third impurity layer and the sixth impurity layer so as to be connected to each other in the third depression; and forming a third conductor layer on the third impurity layer and the sixth impurity layer being connected to each other and in the third depression.

In the invention described above, the third conductor layer may be used as the first wire conductor layer.

In the invention described above, the third impurity layer may be formed by epitaxial crystal growth.

The invention described above can further include the steps of:

forming the third impurity layer inside the first depression; forming the first conductor layer made of a metal or an alloy on the third impurity layer so that an upper surface of the first conductor layer becomes higher than an upper surface of the second interlayer insulating layer; and planarizing the first conductor layer so that an upper surface position of the first conductor layer equals an upper surface position of the second interlayer insulating layer.

The invention described above can further include the steps of:

forming a single crystal semiconductor thin film layer on a bottom part surface of the third depression; and consecutively forming a seventh impurity layer.

In the invention described above, a load SGT (Surrounding Gate Transistor) for an SRAM (Static Random Access Memory) cell circuit can be formed on the first semiconductor pillar and the second semiconductor pillar.

FIGS. 1 AA, 1 AB, and 1 AC are a plan view and a sectional structural diagram for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment;

FIGS. 1 BA, 1 BB and 1 BC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 CA, 1 CB and 1 CC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 DA, 1 DB and 1 DC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 EA, 1 EB and 1 EC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 FA, 1 FB and 1 FC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 GA, 1 GB and 1 GC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 HA, 1 HB and 1 HC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 IA, 1 IB and 1 IC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 JA, 1 JB and 1 JC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 KA, 1 KB and 1 KC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 LA, 1 LB and 1 LC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 MA, 1 MB and 1 MC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 NA, 1 NB and 1 NC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 10 A, 10 B and 10 C are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 PA, 1 PB and 1 PC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 QA, 1 QB and 1 QC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 RA, 1 RB and 1 RC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 SA, 1 SB and 1 SC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 1 TA, 1 TB and 1 TC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the first embodiment;

FIGS. 2 AA, 2 AB and 2 AC are a plan view and a sectional structural diagram for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a second embodiment of the present invention;

FIGS. 2 BA, 2 BB and 2 BC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the second embodiment of the present invention;

FIGS. 2 CA, 2 CB and 2 CC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the second embodiment of the present invention;

FIGS. 2 DA, 2 DB and 2 DC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the second embodiment of the present invention;

FIGS. 2 EA, 2 EB and 2 EC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the second embodiment of the present invention;

FIGS. 2 FA, 2 FB and 2 FC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the second embodiment of the present invention;

FIGS. 2 GA, 2 GB and 2 GC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the second embodiment of the present invention;

FIGS. 3 AA, 3 AB and 3 AC are a plan view and a sectional structural diagram for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a third embodiment of the present invention;

FIGS. 3 BA, 3 BB and 3 BC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the third embodiment of the present invention;

FIGS. 3 CA, 3 CB and 3 CC are a plan view and a sectional structural diagram for explaining the manufacturing method of a pillar-shaped semiconductor device having an SGT according to the third embodiment of the present invention;

FIGS. 4 A, 4 B and 4 C are a plan view and a sectional structural diagram for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a fourth embodiment of the present invention;

FIGS. 5 A and 5 B are schematic structural diagrams showing an SGT according to a conventional example; and

FIG. 6 is an SRAM cell circuit diagram using an SGT according to a conventional example.

Hereinafter, a manufacturing method of a pillar-shaped semiconductor device according to embodiments of the present invention will be described with reference to the drawings.

First Embodiment

Hereinafter, a manufacturing method of an SRAM cell circuit having an SGT according to a first embodiment of the present invention will be described with reference to FIGS. 1 AA to 1 TC . In each diagram, A represents a plan view, B represents a sectional structural diagram taken along an X-X′ line in A, and C represents a sectional structural diagram taken along a Y-Y′ line in A.

As shown in FIGS. 1 AA to 1 AC , an N layer 2 is formed on a P layer substrate 1 (an example of the “substrate” according to the scope of claims) by an epitaxial crystal growth method. An N + layer 3 a , a P + layer 4 a (an example of the “first impurity layer” according to the scope of claims), and a P + layer 4 b (an example of the “fourth impurity layer” according to the scope of claims) are respectively formed by an epitaxial crystal growth method on a surface layer of the N layer 2 . An i layer 6 (an example of the “first semiconductor layer” according to the scope of claims) is formed. An N + layer 3 b , a P + layer 4 c (an example of the “second impurity layer” according to the scope of claims), and a P + layer 4 d (an example of the “fifth impurity layer” according to the scope of claims) are formed by an epitaxial crystal growth method on the i layer 6 . A mask material layer 7 made up of, for example, a SiO 2 layer, an aluminum oxide (Al 2 O 3 , hereinafter referred to as AlO) layer, and a SiO 2 layer is formed. A silicon-germanium (SiGe) layer 8 is deposited. A mask material layer 9 made up of a SiO 2 layer and a SiN layer is deposited. Note that the i layer 6 may be formed of N-type or P-type Si containing a small amount of donor impurity atoms or acceptor impurity atoms. The N + layers 3 a and 3 b and the P + layers 4 a , 4 b , 4 c , and 4 d may be formed by other methods such as an ion implantation method. Furthermore, the mask material layers 7 and 9 may be formed of a single material layer or a plurality of material layers made of a SiO 2 layer, a SiN layer, an AlO layer, or other material layers. The P + layers 4 a and 4 b may be formed connected to each other in a plan view.

Next, using a band-shaped resist layer (not illustrated) formed by a lithographic method and extending in a Y direction in a plan view as a mask, the mask material layer 9 is etched by an RIE (Reactive Ion Etching) method. Using the resist layer as a mask, the mask material layer 9 is subjected to isotropic etching to form band-shaped mask material layers 9 a and 9 b . Accordingly, widths of the band-shaped mask material layers 9 a and 9 b are formed to be narrower than a minimum width of resist layers which can be formed by a lithographic method. Next, using the band-shaped mask material layers 9 a and 9 b as masks, band-shaped SiGe layers 8 a and 8 b are formed as shown in FIGS. 1 BA to 1 BC by etching the SiGe layer 8 by, for example, an RIE method.

Next, a SiN layer (not illustrated) is formed on the entire stack by an ALD (Atomic Layered Deposition) method so as to cover the mask material layer 7 , the band-shaped SiGe layers 8 a and 8 b , and the band-shaped mask material layers 9 a and 9 b . In this case, a cross section of the SiN layer is rounded in a top part thereof. The roundness is desirably formed above the band-shaped SiGe layers 8 a and 8 b . The entire stack is covered by a SiO 2 layer (not illustrated) by, for example, a flow CVD (Flow Chemical Vapor Deposition) method, and the SiO 2 layer and the SiN layer are polished by CMP (Chemical Mechanical Polishing) so that upper surface positions thereof equal upper surface positions of the band-shaped mask material layers 9 a and 9 b to form SiN layers 13 a , 13 b , and 13 c . Top parts of the SiN layers 13 a , 13 b , and 13 c are etched to form depressions. The depressions are formed so that positions of bottom parts of the depressions are at positions of lower parts of the band-shaped mask material layers 9 a and 9 b . The entire stack is coated by a SiN layer (not illustrated), and the entire SiN layer is polished so that an upper surface position of the SiN layer is equal to upper surface positions of the mask material layers 9 a and 9 b . The SiO 2 layer formed by flow CVD is removed. Accordingly, as shown in FIGS. 1 CA to 1 CC , band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb having same shapes as shapes of top parts of the SiN layers 13 a , 13 b , and 13 c in a plan view are formed on both sides of the band-shaped mask material layers 9 a and 9 b.

Next, as shown in FIGS. 1 DA to 1 DC , using the band-shaped mask material layers 9 a , 9 b , 12 aa , 12 ab , 12 ba , and 12 bb as masks, band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb are formed by etching the SiN layers 13 a , 13 b , and 13 c . In this case, widths of the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb are the same in a plan view.

Next, the band-shaped mask material layers 9 a and 9 b and the band-shaped SiGe layers 8 a and 8 b are removed. Accordingly, as shown in FIGS. 1 EA to 1 EC , the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb which respectively have, in top parts thereof, the band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb which extend in the Y direction in a plan view and which are arranged parallel to each other are formed on the mask material layer 7 .

Next, a SiO 2 (not illustrated) by a flow CVD method is formed so as to cover the entire stack. The SiO 2 is polished by a CMP method so that an upper surface position thereof equals upper surface positions of the band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb to form a SiO 2 layer 15 as shown in FIGS. 1 FA to 1 FC . A SiN layer 16 is formed on the SiO 2 layer 15 and the band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb . Band-shaped mask material layers 17 a and 17 b which extend in the X direction and which are arranged parallel to each other are formed on the SiN layer 16 using a same basic method as the method used to form the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb.

Next, as shown in FIGS. 1 GA to 1 GC , using the band-shaped mask material layers 17 a and 17 b as masks, the SiN layer 16 , the band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb , the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb , and the mask material layer 7 are subjected to RIE etching. The SiN layer 16 and the SiO 2 layer 15 which remain are removed. Accordingly, SiN pillars 20 a , 20 b , 20 c , 20 d , 20 e , 20 f , 20 g , and 20 h which have rectangular mask material layers 19 a , 19 b , 19 c , 19 d , 19 e , 19 f , 19 g , and 19 h in top parts thereof are formed in a plan view.

Next, as shown in FIGS. 1 HA to 1 HC , the rectangular mask material layers 19 b and 19 g and the SiN pillars 20 b and 20 g are removed.

Next, using the mask material layers 19 a , 19 c , 19 d , 19 e , 19 f , and 19 h and the SiN pillars 20 a , 20 c , 20 d , 20 e , 20 f , and 20 h as masks, the mask material layer 7 is etched to form mask material layers 7 a and 7 b (an example of the “first material layer” according to the scope of claims), mask material layers 7 c , 7 d , and 7 e (an example of the “third material layer” according to the scope of claims), and a mask material layer 7 f as shown in FIGS. 1 IA to 1 IC . In the etching, by performing isotropic etching by, for example, a CDE (Chemical Dry Etching) method, the mask material layers 7 a , 7 b , 7 c , 7 d , 7 e , and 7 f are given a circular shape in a plan view. The CDE etching is not required if the shapes of the mask material layers 7 a , 7 b , 7 c , 7 d , 7 e , and 7 f in a plan view are circular shapes prior to this step. The mask material layers 19 a , 19 c , 19 d , 19 e , 19 f , and 19 h and the SiN pillars 20 a , 20 c , 20 d , 20 e , 20 f , and 20 h are removed. As shown in FIGS. 1 IA to 1 IC , using the mask material layers 7 a , 7 b , 7 c , 7 d , 7 e , and 7 f as masks, the N + layer 3 a , the P + layers 4 c and 4 d , and the i layer 6 are etched to form Si pillars 6 a and 6 b (an example of the “first semiconductor pillar” according to the scope of claims), Si pillars 6 c , 6 d , and 6 e (an example of the “second semiconductor pillar” according to the scope of claims), and a Si pillar 6 f on the N + layer 3 a and the P + layers 4 a and 4 b . An N + layer 3 ba is formed in a top part of the Si pillar 6 a , a P + layer 4 ca is formed in a top part of the Si pillar 6 b , an N + layer 3 bb is formed in a top part of the Si pillar 6 c , an N + layer 3 Ba (not illustrated) is formed in a top part of the Si pillar 6 d , a P + layer 3 Ca (not illustrated) is formed in a top part of the Si pillar 6 e , and an N + layer 3 Bb (not illustrated) is formed in a top part of the Si pillar 6 f.

Next, as shown in FIGS. 1 JA to 1 JC , the N + layer 3 a , the P + layer 4 a , the N layer 2 , and the P layer substrate 1 which are connected to bottom parts of the Si pillars 6 a , 6 b , and 6 c are etched to form a Si pedestal 21 a made up of an upper part of the P layer substrate 1 , the N layer 2 a , the N + layers 3 aa and 3 ab , and the P + layer 4 aa. At the same time, the N + layer 3 a , the P + layer 4 b , the N layer 2 , and the P layer substrate 1 which are connected to bottom parts of the Si pillars 6 d , 6 e , and 6 f are etched to form a Si pedestal 21 b made up of an upper part of the P layer substrate 1 , the N layer 2 b , the N + layers 3 a B (not illustrated) and 3 b B (not illustrated), and the P + layer 4 bb . A SiO 2 layer 22 is formed in outer circumferential parts of the N + layers 3 aa , 3 ab , 3 a B, and 3 b B, the P + layers 4 aa and 4 bb , and the N layers 2 a and 2 b and on the P layer substrate 1 . A HfO 2 layer 23 (an example of the “gate insulating layer” according to the scope of claims) and a TiN layer (not illustrated) are formed by an ALD method so as to cover the entire stack. In this case, TiN layers are in contact with each other by side surfaces thereof between the Si pillars 6 b and 6 c and the Si pillars 6 d and 6 e . A TiN layer 24 a is formed on the HfO 2 layer 23 surrounding an outer circumference of the Si pillar 6 a , a TiN layer 24 b (an example of the “gate conductor layer” according to the scope of claims) is formed so as to surround the HfO 2 layer 23 in outer circumferences of the Si pillars 6 b and 6 c , a TiN layer 24 c (an example of the “gate conductor layer” according to the scope of claims) is formed so as to surround the HfO 2 layer 23 in outer circumferences of the Si pillars 6 d and 6 e , and a TiN layer 24 d is formed so as to surround the HfO 2 layer 23 in an outer circumference of the Si pillar 6 f . The entire stack is coated by a SiO 2 layer (not illustrated) and, subsequently, the entire stack is polished by a CMP method so that an upper surface position is equal to upper surface positions of the mask material layers 7 a , 7 b , 7 c , 7 d , 7 e , and 7 f . A planarized SiO 2 layer (not illustrated) is etched back by an RIE method to form a SiO 2 layer 25 . Using the mask material layers 7 a , 7 b , 7 c , 7 d , 7 e , and 7 f and the SiO 2 layer 25 as a mask, top parts of the HfO 2 layer 23 and the TiN layers 24 a , 24 b , 24 c , and 24 d are removed. The TiN layers 24 a , 24 b , 24 c , and 24 d are to become a gate conductor layer of the SGT. The gate conductor layer is a layer which contributes toward setting a threshold voltage of the SGT and may be formed of a gate conductor layer made of a single layer or made up of a plurality of layers. The gate conductor material layer is formed in contact with entire side surfaces between the Si pillars 6 b and 6 c and between the Si pillars 6 d and 6 e . Alternatively, for example, a tungsten (W) layer connected to the TiN layers 24 a , 24 b , 24 c , and 24 d may be formed and the layers including the W layer may be used as a gate conductor layer. The W layer may be another conductor material layer.

Next, as shown in FIGS. 1 KA to 1 KC , a SiN layer 27 (an example of the “first interlayer insulating layer” according to the scope of claims) is formed on the SiO 2 layer 25 in the outer circumferential parts of the Si pillars 6 a to 6 f . The entire stack is coated by a SiO 2 layer (not illustrated). By etching the SiO 2 layer by an RIE method, SiO 2 layers 28 a and 28 b (an example of the “second material layer” according to the scope of claims), SiO 2 layers 28 c , 28 d , and 28 e (an example of the “fourth material layer” according to the scope of claims), and a SiO 2 layer 28 f having fixed widths in a plan view are formed in the exposed top parts of the Si pillars 6 a to 6 f and the side surfaces of the mask material layers 7 a to 7 f . In this case, the SiO 2 layer 28 b and the SiO 2 layer 28 c are formed separated from each other. In a similar manner, the SiO 2 layer 28 d and the SiO 2 layer 28 e are formed separated from each other. Note that the SiN layer 27 need only be at least formed on the TiN layers 24 a , 24 b , 24 c , and 24 d which are gate conductor layers. Instead of forming the SiN layer 27 separately from the SiO 2 layer 25 , after forming the gate TiN layers 24 a to 24 d , a SiN layer may be deposited on the entire stack, the SiN layer may be polished by CMP so that an upper surface position thereof equals upper surface positions of the mask material layers 7 a to 7 f , and the SiN layer may be formed by an RIE method so that the upper surface position thereof is higher than upper end positions of the gate TiN layers 24 a to 24 d.

Next, the entire stack is coated by an aluminum oxide (AlO) layer (not illustrated). As shown in FIGS. 1 LA to 1 LC , the AlO layer is polished by a CMP method so that an upper surface position of the AlO layer equals upper surface positions of the mask material layers 7 a to 7 f to form an AlO layer 29 (an example of the “second interlayer insulating layer” according to the scope of claims). The SiO 2 layers 28 a , 28 b , 28 c , 28 d , 28 e , and 28 f which surround the top parts of the Si pillars 6 a to 6 f are removed to form depressions 30 a , 30 b , 30 c , 30 d , 30 e , and 30 f which surround the top parts of the Si pillars 6 a to 6 f . Since the SiO 2 layers 28 a , 28 b , 28 c , 28 d , 28 e , and 28 f are formed by self-alignment with respect to the Si pillars 6 a to 6 f , the depressions 30 a , 30 b , 30 c , 30 d , 30 e , and 30 f are formed by self-alignment with respect to the Si pillars 6 a to 6 f . Note that the AlO layer 29 may be formed of a single other material layer or a plurality of other material layers.

Next, as shown in FIGS. 1 MA to 1 MC , the mask material layers 7 a , 7 b , 7 c , 7 d , 7 e , and 7 f are removed to form depressions 30 A and 30 B (an example of the “first depression” according to the scope of claims), depressions 30 C, 30 D, and 30 E (an example of the “second depression” according to the scope of claims), and a depression 30 F on the outer circumference and the upper part of the top parts of the Si pillars 6 a to 6 f . Note that whichever of the SiO 2 layers 28 a , 28 b , 28 c , 28 d , 28 e , and 28 f and the mask material layers 7 a , 7 b , 7 c , 7 d , 7 e , and 7 f may be removed first.

Next, the entire stack is coated by a SiO 2 layer (not illustrated) by a CVD method. As shown in FIGS. 1 NA to 1 NC, an upper surface position of the SiO 2 layer is polished to the upper surface position of the AlO layer 29 to form SiO 2 layers 31 a , 31 b (not illustrated), 31 c , 31 d , 31 e (not illustrated), and 31 f so as to cover the top parts of the Si pillars 6 a to 6 f and inside the depressions 30 A, 30 B, 30 C, 30 D, 30 E, and 30 F. The SiO 2 layers 31 b and 31 e are removed by a lithographic method and a chemical etching method. A P + layer 32 b (an example of the “third impurity layer” according to the scope of claims) and a P + layer 32 e (an example of the “sixth impurity layer” according to the scope of claims) which contain acceptor impurities are formed by a selective epitaxial crystal growth method so as to cover the top parts of the Si pillars 6 b and 6 e and inside the depressions 30 B and 30 E. Note that, desirably, before forming the P + layers 32 b and 32 e , processing of thinly oxidizing the top parts of the Si pillars 6 b and 6 e and then removing the oxide films is performed so as to remove and clean damaged layers among the surface layers of the top parts of the Si pillars 6 b and 6 e . As the P + layers 32 b and 32 e , single-crystal P + layers 32 b and 32 e may be formed using a method other than a selective epitaxial crystal growth method such as a molecular beam crystal growth method. Alternatively, the P + layers 32 b and 32 e may be formed by applying a coat of a semiconductor layer containing acceptor impurities over its entire surface, polishing the semiconductor layer by a CMP method so that an upper surface thereof equals the upper surface position of the AlO layer 29 , and subjecting the upper surface to a CDE method or chemical etching.

Next, the entire stack is coated with a SiO 2 layer (not illustrated), and by polishing the SiO 2 layer by a CMP method so that an upper surface of the SiO 2 layer equals the upper surface position of the AlO layer 29 , the P + layers 32 b and 32 e are coated by a SiO 2 layer (not illustrated). The SiO 2 layers 31 a , 31 c , 31 d , and 31 f are removed by a lithographic method and a chemical etching method. As shown in FIGS. 10 A to 10 C , N + layers 32 a , 32 c , 32 d , and 32 f containing donor impurities are formed by a selective epitaxial crystal growth method so as to cover the top parts of the Si pillars 6 a , 6 c , 6 d , and 6 f and inside the depressions 30 A, 30 C, 30 D, and 30 F. The N + layers 32 a , 32 c , 32 d , and 32 f are desirably formed so that outer circumferences of the N + layers 32 a , 32 c , 32 d , and 32 f do not protrude more outward than outer circumferences of the depressions 30 A, 30 C, 30 D, and 30 F in a plan view. The SiO 2 layer on the P + layers 32 b and 32 e is removed.

Next, the entire stack is coated by a thin Ta layer (not illustrated) and a W layer (not illustrated). As shown in FIGS. 1 PA to 1 PC , the W layer is polished by a CMP method so that an upper surface position of the W layer equals the upper surface position of the AlO layer 29 to form W layers 33 a and 33 b (an example of the “first conductor layer” according to the scope of claims), W layers 33 c , 33 d , and 33 e (an example of the “second conductor layer” according to the scope of claims), and a W layer 33 f which have Ta layers on a side surface and in a bottom part thereof. In this case, the Ta layers between the N + layers 32 a , 32 c , 32 d , and 32 f and the P + layers 32 b and 32 e and the W layers 33 a , 33 b , 33 c , 33 d , 33 e , and 33 f are buffer layers for reducing contact resistance between the two layers. The buffer layer may be a single other material layer or a plurality of other material layers.

Next, as shown in FIGS. 1 QA to 1 QC , a contact hole C 1 is formed on the TiN layer 24 c , the N + layer 3 aa , and the P + layer 4 aa . At the same time, a contact hole C 2 is formed on the TiN layer 24 b , the N + layer 3 b B, and the P + layer 4 bb . The entire stack is coated by a thin buffer Ti layer (not illustrated) and a W layer (not illustrated). The W layer is etched back by RIE so that an upper surface position of the W layer becomes lower than upper surface positions of the contact holes C 1 and C 2 to form W layers 34 a (not illustrated) and 34 b inside the contact holes C 1 and C 2 . The entire stack is coated by a SiN layer (not illustrated). The SiN layer is polished by a CMP method so that an upper surface position of the SiN layer equals upper surface positions of the W layers 33 a , 33 b , 33 c , 33 d , and 33 f to form SiN layers 35 a (not illustrated) and 35 b on the W layer 34 a inside the contact hole C 1 and on the W layer 34 b inside the contact hole C 2 .

Next, the entire stack is coated by a SiO 2 layer (not illustrated). As shown in FIGS. 1 RA to 1 RC , after forming a SiO 2 layer 37 (an example of the “third interlayer insulating layer” according to the scope of claims) on the entire stack, a band-shaped contact hole C 3 (an example of the “first band-shaped contact hole” according to the scope of claims) which overlaps with at least a part of the W layers 33 b and 33 e on the Si pillars 6 b and 6 e and which extends in the Y direction in a plan view is formed using a lithographic method and an RIE method. Note that a bottom part of the band-shaped contact hole C 3 may reach the upper surface of the SiN layer 27 .

Next, as shown in FIGS. 1 SA to 1 SC , the band-shaped contact hole C 3 is filled and a supply wiring metal layer Vdd (an example of the “first wire conductor layer” according to the scope of claims) to which the W layers 33 b and 33 e are connected is formed. Note that the supply wiring metal layer Vdd is not limited to a metal layer and may be formed using a single layer or a plurality of layers of a material layer made of an alloy or a semiconductor containing a large amount of donor or acceptor impurities.

Next, as shown in FIGS. 1 TA to 1 TC , a SiO 2 layer 38 with a flat upper surface is formed so as to cover the entire stack. A ground wiring metal layer Vss 1 is formed via a contact hole C 4 formed on the W layer 33 c on the N + layer 32 c . At the same time, a ground wiring metal layer Vss 2 is formed via a contact hole C 5 formed on the W layer 33 d on the N + layer 32 d . A SiO 2 layer 39 with a flat upper surface is formed so as to cover the entire stack. A word wiring metal layer WL is formed via contact holes C 6 and C 7 formed on the TiN layers 24 a and 24 d . A SiO 2 layer 40 with a flat upper surface is formed so as to cover the entire stack. An inverted bit output wiring metal layer RBL and a bit output wiring metal layer BL are formed via contact holes C 8 and C 9 formed on the W layers 33 a and 33 f on the N + layers 32 a and 32 f . Accordingly, an SRAM cell circuit is formed on the P layer substrate 1 . In the present SRAM circuit, a load SGT is formed on the Si pillars 6 b and 6 e , a drive SGT is formed on the Si pillars 6 c and 6 d , and a select SGT is formed on the Si pillars 6 a and 6 f.

Note that in FIGS. 1 NA to 1 NC and 10 A to 10 C , the P + layers 32 b and 32 e and the N + layers 32 a , 32 c , 32 d , and 32 f are formed so that upper surfaces thereof are lower than the upper surface of the AlO layer 29 . In contrast, the upper surfaces of the P + layers 32 b and 32 e and the N + layers 32 a , 32 c , 32 d , and 32 f may be formed higher than the upper surface of the AlO layer 29 as long as the P + layers 32 b and 32 e and the N + layers 32 a , 32 c , 32 d , and 32 f do not come into contact with adjacent impurity layers. In addition, in FIGS. 1 PA to 1 PC , the W layer is polished by a CMP method so that an upper surface position of the W layer equals the upper surface position of the AlO layer 29 to form the W layers 33 a , 33 b , 33 c , 33 d , 33 e , and 33 f . In contrast, the upper surfaces of the W layers 33 a , 33 b , 33 c , 33 d , 33 e , and 33 f may be formed higher than the upper surface of the AlO layer 29 as long as the W layers 33 a , 33 b , 33 c , 33 d , 33 e , and 33 f do not come into contact with adjacent W layers.

In addition, the P layer substrate 1 is used as a substrate in the present embodiment. Alternatively, the N layer 2 on the P layer substrate 1 may also be considered a part of the substrate. In addition, other substrates such as a substrate made of an SOI (Silicon Oxide Insulator) may be used in place of the P layer substrate.

Positions of lower ends of the N + layers 32 a , 32 c , 32 d , and 32 f and the P + layers 32 b and 32 e in the vertical direction may be the same as, may be separated from, or may overlap with upper end positions of the gate TiN layers 24 a , 24 b , 24 c , and 24 d as long as normal SGT operations can be performed.

In addition, in the state shown in FIGS. 1 JA to 1 JC , the mask material layers 7 a , 7 b , 7 c , 7 d , 7 e , and 7 f may be absent. In this case, in FIGS. 1 KA to 1 KC or FIGS. 1 LA to 1 LC , due to a step of etching the top parts of the Si pillars 6 a to 6 f , a step of oxidizing the top parts of the Si pillars 6 a to 6 f and then removing the oxide film, or the like, the upper surface positions of the top parts of the Si pillars 6 a to 6 f can be made lower than the AlO layer 29 .

Note that the following conditions must be met in the formation of the band-shaped contact hole C 3 shown in FIGS. 1 RA to 1 RC .

(Condition 1)

There are no Si pillars (which correspond to 6 a , 6 c , 6 d , and 6 f in the present embodiment) other than load SGTs in a region of the band-shaped contact hole C 3 in a plan view.

(Condition 2)

The band-shaped contact hole C 3 may be formed connected to or separated from an adjacent other SRAM cell in the Y direction in a plan view. However, Si pillars (which correspond to Si pillars 6 b and 6 e in the present embodiment) which form load SGTs must be connected to each other in both the X direction and the Y direction in a plan view.

(Condition 3)

The band-shaped contact hole C 3 is formed in order to connect impurity regions (which correspond to P + layers 32 b and 32 e in the present embodiment) to become a source or a drain of an SGT connected to a top part of a Si pillar and a wiring conductive layer made of a metal, an alloy, or the like to each other.

The manufacturing method according to the first embodiment produces the following features.

(Feature 1)

In the present embodiment, the P + layers 32 b and 32 e are formed so as to cover P + layers 4 ca and 4 da in top parts of the Si pillars 6 b and 6 e and inside the depressions 30 B and 30 E formed by self-alignment with the Si pillars 6 b and 6 e . Accordingly, low-resistance P + layers 4 ca and 32 b and P + layers 4 da and 32 e are formed at high density. In addition, by increasing depths of the depressions 30 B and 30 E, resistance values can be readily lowered by eliminating contact with the N + layers 32 c and 32 d and the W layers 33 c and 33 d which are adjacent to the depressions 30 B and 30 E.

(Feature 2)

The W layers 33 b and 33 e on the P + layers 32 b and 32 e are formed inside the depressions 30 B and 30 E. Accordingly, the W layers 33 b and 33 e can be readily separated from similarly-formed N + layers 32 c and 32 d and the W layers 33 c and 33 d which are adjacent to the W layers 33 b and 33 e.

(Feature 3)

Since the W layers 33 b and 33 e are in contact with entire upper surfaces of the P + layers 32 b and 32 e , the supply wiring metal layer Vdd being a wire conductor layer may be separated from adjacent W layers 33 c and 33 d and may be connected to partial regions of the W layers 33 b and 33 e . This indicates that the contact hole C 3 for connecting the supply wiring metal layer Vdd being a wire conductor layer and the W layers 33 b and 33 e to each other can be formed separated from the W layers 33 c and 33 d . Accordingly, an SRAM cell circuit using a high-density SGT with a low source or drain resistance is formed. The two SGTs formed on the Si pillars 6 b and 6 c form a CMOS inverter circuit and, in a similar manner, the two SGTs formed on the Si pillars 6 d and 6 e form a CMOS inverter circuit. This indicates that the present embodiment can be applied to other logic circuits. Accordingly, the present embodiment can contribute toward forming a high-density, high-performance circuit using an SGT.

(Feature 4)

Conventionally, independent contact holes are respectively formed on the Si pillars 6 b and 6 e on which load SGTs are to be formed. A distance between the two contact holes is shortest as compared to distances between other contact holes of drive SGTs and select SGTs. In this case, when progress is made towards higher integration of SRAM cells, forming the two independent contact holes with one implementation of a lithographic method and an RIE etching method becomes difficult. Therefore, for example, a need arises to implement the lithographic method and the RIE etching method in two divided steps. In this case, in addition to a problem of increased cost that accompanies an increase in the number of steps, a decline in a scale of integration due to incorporating a margin in mask alignment between the two lithographic steps becomes an issue. In addition, a difficultly in production in order to form two independent and fine contact holes that are adjacent to each other becomes an issue. In contrast, in the present embodiment, the band-shaped contact hole C 3 is formed so as to overlap with the P + layers 32 b and 32 e and the W layers 33 b and 33 e on the two Si pillars 6 b and 6 e on which load SGTs are to be formed. Accordingly, the supply wiring metal layer Vdd and the P + layers 32 b and 32 e are connected via the band-shaped contact hole C 3 . In this manner, in the present embodiment, independent contact holes are not formed on the Si pillars 6 b and 6 e . Accordingly, cost reduction due to the contact hole being formed by one implementation of a lithographic method and an RIE etching method can be achieved and, at the same time, a decline in a scale of integration can be prevented due to an absence of an issue of a margin of mask alignment. Since the band-shaped contact hole C 3 can be formed wider as compared to a conventional method of forming two independent contact holes, there is an advantage that pattern accuracy can be improved. As a result, according to the present embodiment, an SRAM cell circuit using a high-integration and high-performance SGT is formed at low cost. In a similar manner, a logic circuit using a high-integration and high-performance SGT is formed.

Second Embodiment

Hereinafter, a manufacturing method of an SRAM cell circuit having an SGT according to a second embodiment of the present invention will be described with reference to FIGS. 2 AA to 2 CC . In each diagram, A represents a plan view, B represents a sectional structural diagram taken along an X-X′ line in A, and C represents a sectional structural diagram taken along a Y-Y′ line in A.

In the present embodiment, first, steps shown in FIGS. 1 AA to FIG. 1 QC described in the first embodiment are performed. The entire stack is coated by a resist layer (not illustrated). Using a lithographic method, a resist layer 42 (an example of the “first mask material layer” according to the scope of claims) which overlaps with the Si pillars 6 b and 6 e in a plan view and which has a band-shaped cavity is formed on a SiN layer 41 , the mask material layers 7 a to 7 f , and the SiO 2 layers 28 a to 28 f as shown in FIG. 2 A .

Next, as shown in FIGS. 2 BA to 2 BC , using the resist layer 42 as a mask, the SiN layer 41 , the mask material layers 7 b and 7 e , and the SiO 2 layers 28 b and 28 e are etched by an RIE method so that upper surface positions thereof are lower than upper surface positions of the top parts of the Si pillars 6 b and 6 e to form a depression 43 . Note that a bottom part of the depression 43 may reach the SiN layer 27 . As the resist layer 42 , other material layers made of a single layer or made up of a plurality of layers may be used as long as the material layers serve the purpose of an etching mask.

Next, the resist layer 42 is removed. As shown in FIGS. 2 CA to 2 CC , the mask material layers 7 b and 7 e and the SiO 2 layers 28 b and 28 e on the Si pillars 6 b and 6 e are removed to form a depression 43 A (an example of the “third depression” according to the scope of claims). The depression 43 A is made up of a rectangular part which extends in the Y direction and a removed portion of the SiO 2 layers 28 b and 28 e which surround the top parts of the Si pillars 6 b and 6 e.

Next, the entire stack is coated by a thin single-crystal Si layer (not illustrated) by an ALD method and a P + layer (not illustrated) containing acceptor impurities by an epitaxial crystal growth method. The P + layer and the thin Si layer are polished so that upper surface positions thereof equal an upper surface position of the SiN layer 41 to form a thin single crystal Si layer 45 b (an example of the “single crystal semiconductor thin film layer” according to the scope of claims) and a P + layer 46 as shown in FIGS. 2 DA to 2 DC .

Next, as shown in FIGS. 2 EA to 2 EC , upper parts of the thin Si layer 45 b and the P + layer 46 are etched to form a P + layer 46 b . A mask material layer 49 b which is in an upper part of the P + layer 46 b and of which an upper surface position is equal to the upper surface position of the SiN layer 41 is formed using a CVD method and a CMP method. The mask material layers 7 a , 7 c , 7 d , and 7 f and the SiO 2 layers 28 a , 28 c , 28 d , and 28 f in outer circumferential parts of the top parts and on the top parts of the Si pillars 6 a , 6 c , 6 d , and 6 f are removed to form depressions 43 A, 43 C, 43 D, and 43 E on the top parts of the Si pillars 6 a , 6 c , 6 d , and 6 f . Note that the P + layer 46 b is made of an impurity layer connected to the P + layer 32 b shown in FIGS. 1 NA to 1 NC in the first embodiment. Alternatively, the P + layer 46 b may be formed by a selective epitaxial crystal growth method as in the first embodiment. Alternatively, a single-crystal P + layer 46 b may be formed using other methods such as a molecular beam crystal growth method.

Next, as shown in FIGS. 2 FA to 2 FC , using a same method as the method used to form the P + layer 46 b , thin single crystal Si layers 45 a , 45 c , 45 d (not illustrated), and 45 e (not illustrated) and N + layers 46 a , 46 c , 46 d (not illustrated), and 46 e (not illustrated) which contains donor impurities are formed inside the depressions 43 A, 43 C, 43 D, and 43 E. Mask material layers 49 a , 49 c , 49 d , and 49 e of which upper surface positions are equal to the upper surface position of the SiN layer 41 are formed on the N + layers 46 a , 46 c , 46 d , and 46 e.

Next, the mask material layers 49 a , 49 b , 49 c , 49 d , and 49 e are removed. As shown in FIGS. 2 GA to 2 GC , W layers 50 a , 50 b (an example of the “third conductor layer” according to the scope of claims), 50 c , and 50 e are formed on the N + layers 46 a , 46 c , 46 d , and 46 e and the P + layer 46 b using a CVD method and a CMP method. A SiO 2 layer 52 is formed on the entire stack. The SiO 2 layer 52 on the W layer 50 b is removed and a band-shaped contact hole C 10 is formed using a lithographic method and an RIE etching method. A supply wiring metal layer VDD connected to the W layer 50 b via the band-shaped contact hole C 10 is formed. By performing the step shown in FIGS. 1 TA to 1 TC , an SRAM cell circuit is formed on the P layer substrate 1 . Note that the W layers 50 a , 50 b , 50 c , and 50 e may be formed of a conductor layer made of a single layer or a plurality of layers of another metal or an alloy.

Since the thin single crystal Si layers 45 a to 45 e are layers for forming the P + layer 46 b and the N + layers 46 a , 46 c , 46 d , and 46 f with good crystallinity, other single crystal semiconductor thin film layers may be used as long as a same purpose can be served.

Note that an impurity layer containing donor impurity atoms may be formed in top parts of the Si pillars 6 a , 6 c , 6 d , and 6 f and an impurity layer containing acceptor impurity atoms may be formed in the top parts of the Si pillars 6 b and 6 e under the thin single crystal Si layers 45 a to 45 e . The impurity layers may be formed by thermal diffusion of acceptor impurity atoms and donor impurity atoms from the P + layer 46 b and the N + layers 46 a , 46 c , and 46 e after the formation of the thin single crystal Si layers 45 a to 45 e . Alternatively, the impurity layers may be formed by forming the P + layer 46 b and the N + layers 46 a , 46 c , and 46 e by impregnating the top parts of the Si pillars 6 a to 6 f with acceptor impurity atoms and donor impurity atoms prior to the formation of the thin single crystal Si layers 45 a to 45 e.

The manufacturing method according to the second embodiment produces the following features.

(Feature 1)

In the first embodiment, the P + layers 32 b and 32 e are formed by a selective epitaxial crystal growth method in the depressions 30 B and 30 E in an outer circumferential part of top parts of the Si pillars 6 b and 6 e . The P + layers 32 b and 32 e in contact with the top parts of the Si pillars 6 b and 6 e are required to have good crystallinity. When the crystallinity is poor, problems such as the P + layers 32 b and 32 e causing an increase in diode resistance, an increase in leakage current, or a decline in junction breakdown voltage arise. In order to improve the crystallinity, areas of the depressions 32 B and 32 E of which crystals are to be grown are desirably widened in a plan view. However, since the areas of the depressions 32 B and 32 E decrease due to densification of the SRAM cell, it is difficult to form P + layers 32 b and 32 e with good crystallinity. In contrast, in the present embodiment, since the area of the depression 43 A to be formed by epitaxial crystal growth is larger than the depressions 32 B and 32 E according to the first embodiment, the P + layer 46 with good crystallinity can be formed. Accordingly, reductions in diode resistance and leakage current and an increase in breakdown voltage can be achieved. Furthermore, by forming the P + layer 46 by epitaxial crystal growth after forming the single crystal thin-film Si layer 45 , the P + layer 46 with even better crystallinity can be formed.

(Feature 2)

In the present embodiment, the P + layer 46 b and the N + layers 46 a , 46 c , 46 d , and 46 e include impurity regions which, by self-alignment, concentrically surround the top parts of the Si pillars 6 a to 6 f . Accordingly, a distance between the adjacent Si pillars 6 b and 6 c and a distance between the adjacent Si pillars 6 d and 6 e can be reduced. As a result, densification of the SRAM cell can be achieved. In a similar manner, the W layers 50 a to 50 e on the P + layer 46 b and the N + layers 46 a , 46 c , 46 d , and 46 e are formed inside the depressions 43 A to 43 E having been formed by self-alignment. Accordingly, the contact hole C 10 for connecting the top of the W layer 50 b and the supply wiring metal layer VDD with each other can be separated from the W layers 50 a , 50 c , 50 d , and 50 e on the adjacent Si pillars 6 a , 6 c , 6 d , and 6 f . As a result, densification of the SRAM cell can be achieved.

Third Embodiment

Hereinafter, a manufacturing method of an SRAM cell circuit having an SGT according to a third embodiment of the present invention will be described with reference to FIGS. 3 AA to 3 CC . In each diagram, A represents a plan view, B represents a sectional structural diagram taken along an X-X′ line in A, and C represents a sectional structural diagram taken along a Y-Y′ line in A.

As shown in FIGS. 3 AA to 3 AC , a Si pedestal 55 a made up of the N layer 2 A, the N + layers 3 Aa and 3 Ab, and the P + layer 4 Aa and a Si pedestal 55 b made up of the N layer 2 B, the N + layers 3 Ba (not illustrated) and 3 Bb (not illustrated), and the P + layer 4 Ba are formed on the P layer substrate 1 . Si pillars 6 A, 6 B, 6 C, 6 D, 6 E, and 6 F are formed on the Si pedestals 55 a and 55 b . A straight line connecting centers of the Si pillars 6 B and 6 E is along the Y direction. In a similar manner, a straight line connecting centers of the Si pillars 6 A and 6 D and a straight line connecting centers of the Si pillars 6 C and 6 F are also along the Y direction. A SiO 2 layer 22 a is formed in outer circumferential parts of bottom parts of the Si pillars 6 A to 6 F. A gate HfO 2 layer 23 a is formed by an ALD method so as to cover the entire stack. A gate TiN layer 24 A is formed so as to surround the HfO 2 layer 23 a which surrounds the Si pillar 6 A. At the same time, a gate TiN layer 24 B is formed so as to surround the HfO 2 layer 23 a which surrounds the Si pillars 6 B and 6 C. At the same time, a gate TiN layer 24 C is formed so as to surround the HfO 2 layer 23 a which surrounds the Si pillars 6 D and 6 E. At the same time, a gate TiN layer 24 D (not illustrated) is formed so as to surround the HfO 2 layer 23 a which surrounds the Si pillar 6 F. A SiO 2 layer 25 a is formed so as to surround the gate TiN layers 24 A, 24 B, 24 C, and 24 D.

As shown in FIGS. 3 AA to 3 AC , a W layer 26 a which connects to the TiN layer 24 C, the N + layer 3 Aa, and the P + layer 4 Aa via a contact hole Ca formed in the SiO 2 layer 25 a and of which an upper surface position is lower than upper surface positions of the TiN layers 24 A to 24 D is formed. At the same time, a W layer 26 b which connects to the TiN layer 24 B, the N + layer 3 Bb, and the P + layer 4 Ba via a contact hole Cb formed in the SiO 2 layer 25 a and of which an upper surface position is lower than the upper surface positions of the TiN layers 24 A to 24 D is formed. A SiN layer 27 a is formed in an outer circumferential part of top parts of the Si pillars 6 A to 6 F and on top of upper ends of the gate TiN layers 24 A to 24 D. N + layers 46 a , 46 c , 46 d (not illustrated), and 46 f (not illustrated) are formed in top parts of the Si pillars 6 A, 6 C, 6 D, and 6 F and P + layers 46 b and 46 e are formed in top parts of the Si pillars 6 B and 6 E. In addition, by the same steps as those shown in FIGS. 1 KA to 1 PC according to the first embodiment, N + layers 47 a , 47 c , 47 d (not illustrated), and 47 f (not illustrated) and P + layers 47 b and 47 e are formed by a selective epitaxial crystal growth method, and W layers 48 a , 48 b , 48 c , 48 d (not illustrated), 48 e and 48 f (not illustrated) are formed on the N + layers 47 a , 47 c , 47 d , and 47 f and the P + layers 47 b and 47 e . A SiO 2 layer 49 is formed in outer circumferential parts of the N + layers 47 a , 47 c , 47 d , and 47 f , the P + layers 47 b and 47 e , and the W layers 48 a , 48 b , 48 c , 48 d , 48 e , and 48 f.

Next, as shown in FIGS. 3 BA to 3 BC , a SiO 2 layer 50 is formed on the W layers 48 a , 48 b , 48 c , 48 d , 48 e , and 48 f and the SiO 2 layer 49 . A band-shaped contact hole Cc of which a bottom part position is equal to upper surface positions of the P + layers 47 b and 47 e , which overlaps with the W layers 48 b and 48 e in a plan view, and which extends in the Y direction is formed by a lithographic method and RIE etching. The band-shaped contact hole Cc is on the inner side of the W layer 48 b on an X-X′ line in a plan view. The band-shaped contact hole Cc and the W layer 48 e are in a same relationship. The contact hole Cc is filled to form a supply wiring metal layer Vdd which is connected to the P + layers 47 b and 47 e . In this case, upper surface positions of the SiO 2 layer 50 and the supply wiring metal layer Vdd are made the same by CMP. Accordingly, the supply wiring metal layer Vdd is prevented from protruding more outward than the band-shaped contact hole Cc in a plan view.

Next, as shown in FIGS. 3 CA to 3 CC , a SiO 2 layer 51 with a flat upper surface is formed so as to cover the entire stack. A ground wiring metal layer Vss 1 is formed via a contact hole Cd formed on the W layer 48 a . At the same time, a ground wiring metal layer Vss 2 is formed via a contact hole Ce formed on the W layer 48 f . The SiO 2 layer 52 with a flat upper surface is formed so as to cover the entire stack. A word wiring metal layer WL is formed via contact holes Cf and Cg formed on the TiN layers 24 A and 24 D. A SiO 2 layer 53 with a flat upper surface is formed so as to cover the entire stack. A bit output wiring metal layer BL and an inverted bit output wiring metal layer RBL are formed via contact holes Ch and Ci formed on the W layers 48 c and 48 d . Accordingly, an SRAM cell circuit is formed on the P layer substrate 1 .

The manufacturing method according to the third embodiment produces the following features.

(Feature 1)

In the first embodiment, the Si pillars 6 b and 6 e are formed displaced in the X direction. In contrast, in the present embodiment, centers of the Si pillars 6 B and 6 E are on a single line that extends in the Y direction. Although an arrangement of the Si pillars 6 A to 6 F in the SRAM cell in the present embodiment differs from the arrangement of the Si pillars 6 a to 6 f in the first embodiment, the present embodiment has the same features as the first embodiment. The P + layers 47 b and 47 e and the W layers 48 b and 48 e are formed by self-alignment with the Si pillars 6 B and 6 E. Accordingly, the P + layers 47 b and 47 e and the W layers 48 b and 48 e can reliably separate the N + layers 47 c and 47 d and the W layers 48 c and 48 d formed in top parts of the adjacent Si pillars 6 C and 6 D. At the same time, since the P + layers 47 b and 47 e cover the P + layers 46 b and 46 e , a low-resistance source region or a low-resistance drain region is formed.

(Feature 2)

In the present embodiment, the band-shaped contact hole Cc is on the inner side of the W layer 48 b on the X-X′ line. The band-shaped contact hole Cc and the W layer 48 e are in a same relationship. In addition, since the band-shaped contact hole Cc need only be connected to a part of the W layers 48 b and 48 e in a plan view, a decline in yield due to a displacement in mask alignment can be prevented. Furthermore, since the band-shaped contact hole Cc can be formed wider as compared to forming two independent contact holes on the W layers 48 b and 48 e , there is an advantage that pattern accuracy can be improved. Accordingly, an SRAM cell using a high-integration and high-accuracy SGT is formed at low cost.

Fourth Embodiment

Hereinafter, a manufacturing method of an SRAM cell circuit having an SGT according to a fourth embodiment of the present invention will be described with reference to FIGS. 4 A to 4 C . In FIGS. 4 A to 4 C , A represents a plan view, B represents a sectional structural diagram taken along an X-X′ line in A, and C represents a sectional structural diagram taken along a Y-Y′ line in A.

As shown in FIGS. 4 A to 4 C , the contact hole C 10 and the supply wiring metal layer VDD shown in FIGS. 2 GA to 2 GC are not formed. The W layer 50 b acts as the supply wiring metal layer VDD. The W layer 50 b is connected to a wiring metal layer which corresponds to the supply wiring metal layer VDD shown in FIGS. 1 TA to 1 TC on the outside of the SRAM cell region.

The manufacturing method according to the fourth embodiment produces the following features.

In the present embodiment, since the W layer 50 b acts as the supply wiring metal layer VDD, the formation step of the contact hole C 10 and the supply wiring metal layer VDD in the SRAM cell region shown in FIGS. 2 GA to 2 GC in the second embodiment is not necessary. Accordingly, a decline in the scale of integration and a decline in yield which accompany formation of a contact hole and a wiring metal layer in the SRAM cell can be prevented. In addition, when the present invention is applied to a logic circuit, since a distance from a unit circuit region to an external wiring lead-out terminal can be reduced, a conductor layer corresponding to the W layer 50 b described above can be more readily formed. In addition, in a microprocessor circuit, the present embodiment may only be applied to a logic circuit region.

While one SGT has been formed on one semiconductor pillar in the embodiments according to the present invention, the present invention can also be applied to circuit formation in which two or more SGTs are formed. The present invention can be applied to a connection between impurity layers in top parts of SGTs in uppermost parts of two semiconductor pillars on which two or more SGTs have been formed.

While the Si pillars 6 a to 6 f are formed in the first embodiment, the Si pillars may be replaced with semiconductor pillars made of other semiconductor materials. This similarly applies to other embodiments according to the present invention.

In addition, the N + layers 32 a , 32 c , 32 d , and 32 f and the P + layers 32 b and 32 e according to the first embodiment may be formed of Si or another semiconductor material layer containing donor or acceptor impurities. In addition, the N + layers 32 a , 32 c , 32 d , and 32 f and the P + layers 32 b and 32 e may be formed of different semiconductor material layers. This similarly applies to other embodiments according to the present invention.

In addition, in the first embodiment, the N + layers 32 a , 32 c , 32 d , and 32 f and the P + layers 32 b and 32 e are formed using a selective epitaxial crystal growth method. The N + layers 32 a , 32 c , 32 d , and 32 f and the P + layers 32 b and 32 e may be selectively formed by other methods including a method of repetitively performing CDE (Chemical Dry Etching) and ordinary epitaxial crystal growth to form the N + layers 32 a , 32 c , 32 d , and 32 f and the P + layers 32 b and 32 e on the top parts of the Si pillars 6 a to 6 f inside the depressions 30 A to 30 F. This similarly applies to other embodiments according to the present invention.

In addition, as the SiN layer 27 in outer circumferential parts of the Si pillars 6 a to 6 f , the SiO 2 layers 28 a to 28 f formed on exposed top parts of the Si pillars 6 a to 6 f and side surfaces of the mask material layers 7 a to 7 f , and the AlO layer 29 which surrounds the SiO 2 layers 28 a to 28 f , described in the first embodiment, another material layer made of a single layer or made up of a plurality of layers and containing an organic material or an inorganic material may be used as long as the materials serve the purpose of the present invention. This similarly applies to other embodiments according to the present invention.

In addition, in the first embodiment, the mask material layer 7 is formed of a SiO 2 layer, an aluminum oxide (Al 2 O 3 , also referred to as AlO) layer, and a SiO 2 layer. As the mask material layer 7 , another material layer made of a single layer or made up of a plurality of layers and containing an organic material or an inorganic material may be used as long as the materials serve the purpose of the present invention. This similarly applies to other embodiments according to the present invention.

In addition, in the first embodiment, the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb entirely formed by an ALD method are formed on both sides of the band-shaped SiGe layers 8 a and 8 b as shown in FIGS. 1 CA to 1 CC and FIGS. 1 DA to 1 DC . As the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb and the band-shaped SiGe layers 8 a and 8 b , another material layer made of a single layer or made up of a plurality of layers and containing an organic material or an inorganic material may be used as long as the materials serve the purpose of the present invention. This similarly applies to other embodiments according to the present invention.

In addition, as described with reference to FIGS. 1 AA to 1 GC , the band-shaped mask material layers 17 a and 17 b which extend in the X direction and which are perpendicular to the band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb and the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb which extend in the Y direction are formed by a method similar to the method of forming the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb . Accordingly, the Si pillars 6 a to 6 f are formed with high accuracy and high density in both the X direction and the Y direction. In addition, in the description of the present embodiment, the band-shaped mask material layers 17 a and 17 b are formed after forming the band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb and the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb . In contrast, even by a step of forming the band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb and the band-shaped SiN layers 13 aa , 13 ab , 13 ba , and 13 bb after forming the band-shaped mask material layers 17 a and 17 b , the Si pillars 6 a to 6 f can be formed in a same manner with high accuracy and high density. In addition, when there is leeway in the Y direction in terms of design, the band-shaped mask material layers 17 a and 17 b may be directly formed by a lithographic method and an RIE etching method instead of using the present method. In addition, when there is leeway in the X direction, the band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb may be directly formed by a lithographic method and an RIE etching method instead of using the present method. In addition, as long as SRAM cell performance can be satisfied, the band-shaped mask material layers 12 aa , 12 ab , 12 ba , and 12 bb and the band-shaped mask material layers 17 a and 17 b which extend in the X direction may be formed using SADP (Self-Aligned Double Patterning, refer to A. Raley, S. Thibaut, N. Mohanty, K. Subhadeep, S. Nakamura, et al.: “Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32 nm pitch applications” Proc. Of SPIE Vol. 9782, 2016) and SAQP (Self-Aligned Quadruple Patterning, refer to A. Raley, S. Thibaut, N. Mohanty, K. Subhadeep, S. Nakamura, et al.: “Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32 nm pitch applications” Proc. Of SPIE Vol. 9782, 2016). This similarly applies to other embodiments according to the present invention.

In addition, as described with reference to FIGS. 1 HA to 1 HC and FIGS. 1 IA to 1 IC in the first embodiment, after forming the SiN pillars 20 a , 20 b , 20 c , 20 d , 20 e , 20 f , 20 g , and 20 h which have rectangular mask material layers 19 a , 19 b , 19 c , 19 d , 19 e , 19 f , 19 g , and 19 h in top parts thereof, the rectangular mask material layers 19 b and 19 g and the SiN pillars 20 b and 20 g are removed. Accordingly, formation regions for the contact holes C 1 and C 2 without Si pillars are formed in the regions where the contact holes C 1 and C 2 are present as shown in FIG. 1 in a plan view. In contrast, the formation regions for the contact holes C 1 and C 2 may be formed by forming Si pillars in the formation regions for the contact holes C 1 and C 2 and subsequently removing the Si pillars. In addition, the formation regions for the contact holes C 1 and C 2 may be formed by a method of not forming Si pillars in regions where the contact holes C 1 and C 2 are present by forming the band-shaped mask material layers 17 a and 17 b and subsequently performing a step of removing the band-shaped mask material layers 17 a and 17 b in the formation regions for the contact holes C 1 and C 2 . As described above, the formation regions for the contact holes C 1 and C 2 may be formed by a method other than the method described in the first embodiment. This similarly applies to other embodiments according to the present invention.

In addition, in the first embodiment, as shown in FIGS. 1 TA to 1 TC , the N + layers 3 aa , 3 ab , 3 ba , and 3 bb and the P + layers 4 aa and 4 bb to be a source or a drain of an SGT are formed connected on the N layers 2 a and 2 b in a lower part of the Si pillars 6 a to 6 f . In contrast, the N + layers 3 aa , 3 ab , 3 ba , and 3 bb and the P + layers 4 aa and 4 bb may be formed in bottom parts of the Si pillars 6 a to 6 f and the N + layers 3 aa , 3 ab , 3 ba , and 3 bb and the P + layers 4 aa and 4 bb may be connected to each other via a metal layer or an alloy layer. In addition, the N + layers 3 aa , 3 ab , 3 ba , and 3 bb and the P + layers 4 aa and 4 bb may be formed connected to side surfaces of the bottom parts of the Si pillars 6 a to 6 f . As described above, the N + layers 3 aa , 3 ab , 3 ba , and 3 bb and the P + layers 4 aa and 4 bb to be a source or a drain of an SGT may be formed inside the bottom parts of the Si pillars 6 a to 6 f , in contact with an outer side of side surfaces of the Si pillars 6 a to 6 f , or in an outer circumference of the Si pillars 6 a to 6 f , and the respective layers may be electrically connected by other conductive materials. This similarly applies to other embodiments according to the present invention.

In addition, while the band-shaped mask material layers 9 a , 9 b , 12 aa , 12 ab , 12 ba , and 12 bb are formed so that positions of respective upper surfaces and bottom parts thereof in the vertical direction are the same, the positions of respective upper surfaces and bottom parts may differ in the vertical direction as long as the purpose of the present invention is served. This similarly applies to other embodiments according to the present invention. This similarly applies to other embodiments according to the present invention.

In addition, in the first embodiment, thicknesses and shapes of the band-shaped mask material layers 9 a , 9 b , 12 aa , 12 ab , 12 ba , and 12 bb change due to polishing by CMP, RIE etching, and cleaning. The change is not an issue as long as the purpose of the present invention is served. This similarly applies to other embodiments according to the present invention.

In addition, a material of the various wiring metal layers 34 a , 34 b , WL, Vdd, Vss, BL, and RBL according to the first embodiment is not limited to a metal and may be a conductive material layer such as a semiconductor layer containing a large amount of an alloy, acceptor impurities, or donor impurities and may be constructed by a single layer or a plurality of layers of the conductive material layer. This similarly applies to other embodiments according to the present invention.

In addition, in the first embodiment, the TiN layers 24 a , 24 b , 24 c , and 24 d are used as gate metal layers as shown in FIGS. 1 JA to 1 JC . As the TiN layers 24 a , 24 b , 24 c , and 24 d , a material layer made of a single layer or made up of a plurality of layers may be used as long as the materials serve the purpose of the present invention. The TiN layers 24 a , 24 b , 24 c , and 24 d can be formed of a conductor layer such as a single metal layer or a plurality of metal layers with at least a desired work function. Another conductive layer such as a W layer may be formed on an outer side of the conductive layer. In this case, the W layer acts as a metal wiring layer which connects the gate metal layers. A single metal layer or a plurality of metal layers may be used besides a W layer. In addition, while the HfO 2 layer 23 is used as the gate insulating layers, another material layer made of a single layer or made up of a plurality of layers may be used as each gate insulating layer. This similarly applies to other embodiments according to the present invention.

In the first embodiment, the Si pillars 6 a to 6 f have a circular shape in a plan view. The shape of a part of or all of the Si pillars 6 a to 6 f in a plan view may be a circle, an ellipse, a shape elongated in one direction, or the like. In addition, even in a logic circuit region which is formed separated from the SRAM cell region, a mixture of Si pillars with different shapes in a plan view can be formed in the logic circuit region in accordance with logic circuit design. These descriptions similarly apply to other embodiments according to the present invention.

In addition, in the first embodiment, the N + layers 3 aa , 3 ab , 3 ba , and 3 bb and the P + layers 4 aa and 4 bb are formed so as to be connected to bottom parts of the Si pillars 6 a to 6 f . An alloy layer made of a metal, silicide, or the like may be formed on upper surfaces of the N + layers 3 aa , 3 ab , 3 ba , and 3 bb and the P + layers 4 aa and 4 bb . In addition, a source or drain impurity region of an SGT may be formed by forming a P + layer or an N + layer containing donor or acceptor impurity atoms by, for example, an epitaxial crystal growth method on outer circumferences of the bottom parts of the Si pillars 6 a to 6 f . In this case, an N + layer or a P + layer may or may not be formed inside Si pillars in contact with the N + layer or the P + layer formed by the epitaxial crystal growth method. Alternatively, an extended metal layer or an extended alloy layer may be provided in contact with the P + layer or the N + layer. This similarly applies to other embodiments according to the present invention.

In addition, while SGTs are formed on the P layer substrate 1 in the first embodiment, a SOI (Silicon On Insulator) substrate may be used instead of the P layer substrate 1 . Alternatively, a substrate made of other materials may be used as long as the role of a substrate is served. This similarly applies to other embodiments according to the present invention.

In addition, while SGTs that constitute a source and a drain using the N + layers 3 aa , 3 ab , 3 ba , and 3 bb , the P + layers 4 aa and 4 bb , the N + layers 32 a , 32 c , 32 d , and 32 f , and the P + layers 32 b and 32 e which have conductivity of the same polarity in upper and lower positions of the Si pillars 6 a to 6 f have been described in the first embodiment, the present invention can also be applied to tunnel SGTs having a source and a drain with different polarities. This similarly applies to other embodiments according to the present invention.

In addition, in the first embodiment, the N + layers 32 a , 32 c , 32 d , and 32 f and the P + layers 32 b and 32 e are formed after forming the gate HfO 2 layer 23 and the gate TiN layers 24 a , 24 b , 24 c , and 24 d . In contrast, the gate HfO 2 layer 23 and the gate TiN layers 24 a , 24 b , 24 c , and 24 d may be formed after forming the N + layers 32 a , 32 c , 32 d , and 32 f and the P + layers 32 b and 32 e . This similarly applies to other embodiments according to the present invention.

In addition, in the second embodiment, the thin single-crystal Si layer 45 is formed by an ALD method and the P + layer 46 containing acceptor impurities is formed by an epitaxial crystal growth method. The thin single-crystal Si layer 45 is a material layer for obtaining the P + layer 46 with good crystallinity. A single layer or a plurality of layers of other material layers may be used as long as the material layers enable the P + layer 46 with good crystallinity to be obtained.

In addition, in a vertical NAND flash memory circuit, with a semiconductor pillar as a channel, a memory cell constituted of a tunnel oxide layer, a charge storage layer, an interlayer insulating layer, and a control conductor layer which surround the semiconductor pillar are formed in a plurality of stages in the vertical direction. Semiconductor pillars at both ends of the memory cells have a source line impurity layer which corresponds to a source and a bit line impurity layer which corresponds to a drain. In addition, with respect to one memory cell, if one of the memory cells on both sides serves as a source, the other memory call serves as a drain. In this manner, a vertical NAND flash memory circuit is a type of an SGT circuit. Therefore, the present invention can also be applied to a hybrid circuit equipped with a NAND flash memory circuit.

The present invention enables various embodiments and modifications to be devised without departing from the broad spirit and scope of the present invention. In addition, the embodiments described above are for explaining examples of the present invention and are not intended to limit the scope of the present invention. The embodiments and the modifications described above can be arbitrarily combined. Furthermore, even if parts of constituent features of the embodiments described above are removed as necessary, such removal of constituent features is within the technical ideas of the present invention.

A pillar-shaped semiconductor device and a manufacturing method thereof according to the present invention enable a high-density pillar-shaped semiconductor device to be obtained.