Semiconductor device

This application is based on and claims priority to Korean Patent Application No. 10-2022-0062921 filed in the Korean Intellectual Property Office on May 23, 2022, and Korean Patent Application No. 10-2022-0121609 filed in the Korean Intellectual Property Office on Sep. 26, 2022, the entire contents of which are incorporated herein by reference.

1. Field

One or more embodiments of the present disclosure relates to a semiconductor device, and more particularly to a semiconductor device and a method of training a data clock signal to obtain an optimal duty cycle for data transmission.

2. Description of the Related Art

Component devices such as a memory device and computing systems including a system on chip (SoC) require high performance. The system on chip may provide clock signals and data clock signals to the component device for the purpose of high-rate data inputs and outputs for the component device. A duty cycle of the clock signal may fluctuate according to varying temperatures and/or voltages, and when the accurate duty cycle is not used, a margin for reading data signals becomes degraded. In addition, as the frequency of the data clock signal is higher than the frequency of the clock signal, it may be necessary to adjust the duty cycle of the data clock signal to obtain an accurate margin for data transmission.

Aspects of the present disclosure provide a semiconductor device for training an optimal duty cycle of a data clock signal.

Aspects of the present disclosure provide a semiconductor device for training a data clock signal by using a write data pattern.

According to some example embodiments of the present disclosure, a semiconductor device may include: a data clock signal generator circuit configured to output a plurality of data clock signals that have different phases and that are used to generate a plurality of internal data clock signals of a memory device; a data transmitter configured to generate a data signal based on a test pattern transitioned once, delay the data signal once transitioned according to a delay value, and output the data signal to the memory device; a data receiver configured to receive an output signal from the memory device that includes first sampling data, the first sampling data being obtained by sampling the data signal based on a first internal data clock signal from the plurality of internal data clock signals; and a training circuit configured to change the delay value and determine a final value of the delay value based on the first sampling data.

The training circuit may be configured to determine the final value of the delay value based on a sampling delay value of the first sampling data, and the sampling delay value may correspond to when a bit value of the first sampling data is transitioned once.

The training circuit may be configured to determine the final value of the delay value based on an intermediate value of sampling delay values of the first sampling data, the intermediate value may be between a first sampling delay value and a second sampling delay value of the sampling delay values, the first sampling delay value may correspond to when a first bit value of the first sampling data is transitioned, and the second sampling delay value may correspond to when a second bit value of the first sampling data is transitioned, and the first and second bit values may both be transitioned from a same one of 1 to 0 or 0 to 1.

The training circuit may be configured to change a bit value of the test pattern, after determining the final value of the delay value, such that a timing when the data signal is transitioned is changed, the data receiver may be configured to receive an output signal from the memory device that includes second sampling data, the second sampling data being obtained by sampling the data signal that has the timing changed based on a second internal data clock signal from the plurality of internal data clock signals, and the training circuit may be configured to adjust a code that is used to generate the second internal data clock signal of the memory device, and may be configured to determine a final value of the code based on the second sampling data.

The training circuit may be configured to determine the final value of the code based on a sampling value of the code obtained from the second sampling data, and the sampling value of the code may correspond to when a bit value of the second sampling data is transitioned.

The training circuit may be configured to change the timing when the data signal is transitioned by one unit interval (UI) by changing one bit value of the test pattern.

The code may be used to adjust a delay of a data clock signal from the plurality of data clock signals and to generate the second internal data clock signal, and the second internal data clock signal may have a delay that is based on the code.

The first internal data clock signal and the second internal data clock signal may have a phase difference of 90 degrees.

According to some example embodiments of the present disclosure, a method for operating a semiconductor device may include: outputting a plurality of data clock signals having different phases and used in generating a plurality of internal data clock signals of a memory device; generating a data signal based on a test pattern transitioned once, delaying the data signal once transitioned according to a delay value, and outputting the data signal to the memory device; receiving an output signal from the memory device including first sampling data, the first sampling data being obtained by sampling the data signal based on a first internal data clock signal from the plurality of internal data clock signals; and determining a final value of the delay value based on the first sampling data.

The determining of the final value of the delay value may comprise determining a sampling delay value of the first sampling data, and the sampling delay value may correspond to when a bit value of the first sampling data is transitioned.

The determining of the final value of the delay value may comprise determining an intermediate value of sampling delay values of the first sampling data, the intermediate value may be between a first sampling delay value and a second sampling delay value of the sampling delay values, the first sampling delay value may correspond to when a first bit value of the first sampling data is transitioned, and the second sampling delay value may correspond to when a second bit value of the first sampling data is transitioned, and the first and second bit values may both be transitioned from a same one of 1 to 0 or 0 to 1.

The method may further include: changing a bit value of the test pattern, after determining the final value of the delay value, to change a timing when the data signal is transitioned; receiving an output signal including second sampling data from the memory device, the second sampling data being obtained by sampling the data signal that has the timing change based on a second internal data clock signal from the plurality of internal data clock signals; adjusting a code for generating the second internal data clock signal of the memory device; and determining a final value of the code based on the second sampling data.

The determining of the final value of the code may comprise determining a sampling value of the code obtained from the second sampling data, and the sampling value of the code may correspond to when a bit value of the second sampling data is transitioned.

The changing of the bit value of the test pattern may comprise changing the timing when the data signal is transitioned by one unit interval (UI).

The code may be used to adjust a delay of a data clock signal from the plurality of data clock signals and to generate the second internal data clock signal, and the second internal data clock signal may have a delay that is based on the code.

According to some example embodiments of the present disclosure, a computing system may include: a memory device comprising: a clock signal control circuit configured to receive and buffer a plurality of data clock signals with different phases and generate a plurality of internal data clock signals; and a plurality of sampler circuits configured to sample a data signal based on the plurality of internal data clock signals and output a plurality of sampling data; and a system on chip configured to serialize a test pattern to generate the data signal, delay the data signal according to a delay value, output the data signal to the memory device, determine a final value of the delay value based on a value of first sampling data from the plurality of sampling data, delay the data signal according to the final value of the delay value, and output the data signal that is delayed according to the final value of the delay value, the first sampling data may be obtained by sampling the data signal based on a first internal data clock signal from the plurality of internal data clock signals, and the first internal data clock signal may be synchronized with a timing when the data signal is transitioned.

The clock signal control circuit may be configured to generate a second internal data clock signal from the plurality of internal data clock signals by adjusting a phase of a data clock signal from the plurality of data clock signals according to a code, the system on chip may be configured to change one bit value of the test pattern to arrange a timing when the data signal is transitioned to correspond to an edge of the second internal data clock signal, adjust a value of the code, determine a final value of the code based on second sampling data, and store the final value of the code in the memory device, and the second sampling data may be obtained by sampling the data signal based on the second internal data clock signal.

The clock signal control circuit may comprise a buffer configured to generate the second internal data clock signal, and configured to adjust a delay of the data clock signal according to the code.

The first internal data clock signal and the second internal data clock signal may have a phase difference of 90 degrees.

The system on chip may be configured to determine the final value of the code based on a sampling value of the code obtained from the second sampling data, and the sampling value of the code may correspond to when a bit value of the second sampling data is transitioned.

FIG. 1 shows a block diagram of a computing system according to some example embodiments of the present disclosure.

FIG. 2 shows a block diagram of a semiconductor memory device according to some example embodiments of the present disclosure.

FIG. 3 shows a block diagram of a system on chip according to some example embodiments of the present disclosure.

FIG. 4 shows a block diagram of a clock signal control circuit and a write circuit according to some example embodiments of the present disclosure.

FIGS. 5 and 6 show graphs of waveforms of input and output signals of a clock signal control circuit and a write circuit according to some example embodiments of the present disclosure.

FIGS. 7 and 8 show tables of sampling data according to delay values of write DQ according to some example embodiments of the present disclosure.

FIGS. 9 to 11 show graphs of waveforms of input and output signals of a clock signal control circuit and a data I/O circuit according to some example embodiments of the present disclosure.

FIG. 12 shows a flowchart of a clock training method according to some example embodiments of the present disclosure.

FIGS. 13 and 14 show flowcharts of some stages of a clock training method according to some example embodiments of the present disclosure.

FIG. 15 shows a block diagram of a computer system according to some example embodiments of the present disclosure.

In the following detailed description, only certain embodiments have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the scope of the present disclosure.

Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive, and like reference numerals designate like elements throughout the specification. In the flowcharts described with reference to the drawings in this specification, the operation order may be changed, various operations may be merged, certain operations may be divided, and certain operations may not be performed.

An expression recited in the singular may be construed as singular or plural unless the expression “one”, “single”, etc., is used. Terms including ordinal numbers such as first, second, and the like, will be used only to describe various components, and are not to be interpreted as limiting these components. The terms may only be used to differentiate one component from others.

FIG. 1 shows a block diagram of a computing system according to some example embodiments.

Referring to FIG. 1 , the computing system 100 may include a system on chip 110 and a memory device 120 .

The system on chip 110 may be electrically connected to the memory device 120 . In some embodiments, the system on chip 110 and the memory device 120 may be connected to each other through a memory interface and may transmit/receive signals to/from each other through the memory interface. In some embodiments, a clock signal pin P 11 , a command/address pin P 12 , a data clock signal pin P 13 , and a data pin P 14 of the system on chip 110 may be connected to a clock signal pin P 21 , a command/address pin P 22 , a data clock signal pin P 23 , and a data pin P 24 of the memory device 120 .

The system on chip 110 may generate a command signal CMD, an address ADDR, a system clock signal CK, and a data clock signal WCK. The system on chip 110 may provide the system clock signal CK to the memory device 120 through the clock signal pins P 11 and P 21 , may provide the command signal CMD/address ADDR to the memory device 120 through the command/address pins P 12 and P 22 , and may provide the data clock signal WCK to the memory device 120 through the data clock signal pins P 13 and P 23 .

The system on chip 110 may receive a data input and output signal DQ and a data strobe signal DQS from the memory device 120 through the data pins P 14 and P 24 or may transmit data processing results to the memory device 120 . The DQS may be used to sample the DQ. The system on chip 110 provides a signal to the memory device 120 to control a memory operation of the memory device 120 . The signal may include a command signal CMD and an address ADDR. In some embodiments, the system on chip 110 may provide the command signal CMD and the address ADDR to the memory device 120 to access the memory cell array 121 and may control the memory operation such as read or write. According to the read operation, the DQ and the DQS may be transmitted to the system on chip 110 from the memory cell array 121 , and according to the write operation, the DQ and the DQS may be transmitted to the memory cell array 121 from the system on chip 110 . The DQ and the DQS are respectively bidirectional signals so the DQ and the DQS output to the memory device 120 from the system on chip 110 may be respectively referred to as a write DQ and a write DQS, and the DQ and the DQS output to the system on chip 110 from the memory device 120 may be respectively referred to as a read DQ and a read DQS.

The command signal CMD may include an activate command, a read/write command, and a refresh command. In some embodiments, the command signal CMD may further include a precharge command. The activate command may be a command for switching a target row of the memory cell array 121 to an active state so as to write data on the memory cell array 121 or read data from the memory cell array 121 . In response to the activate command, the memory cell of the target row may be activated (e.g., driving). The read/write command may be a command for performing a read or write operation at the target memory cell of the row switched to the active state. In some embodiments, the read command may be a command for activating an emphasis driving. The refresh command may be a command for performing a refresh operation at the memory cell array 121 .

The system on chip 110 may apply the system clock signal CK and the data clock signal WCK to the memory device 120 so as to control the data input and output. The system clock signal CK may be provided in the form of differential signals having complementary phases. The data clock signal WCK may also be provided in the form of differential signals having complementary phases. The system clock signal CK may be a clock signal relating to a command signal CMD applied to perform a data input and output operation or a transmission rate of the address ADDR. The data clock signal WCK may be a clock signal relating to input and output rates of the DQ and the DQS. In some embodiments, the command CMD and the address signal ADDR may be transmitted based on the system clock signal CK. The DQ and the DQS may be transmitted based on the data clock signal WCK.

The system on chip 110 may include a training circuit 111 . The training circuit 111 may perform memory core parameter training relating to memory cores including the memory cell array 121 of the memory device 120 , a row decoder, and a column decoder, and/or may perform peripheral circuit parameter training on remaining peripheral circuits excluding the memory cores. The training circuit 111 may determine optimal parameters on the memory core parameters of the memory device 120 and/or the peripheral circuit parameters. The system on chip 110 including the training circuit 111 may perform the training of the memory device 120 . In some embodiments, the training circuit 111 is included in the memory device 120 , and the memory device 120 may perform the training.

In some embodiments, the training circuit 111 may provide a write DQ to the memory device 120 , and may perform training on the data clock signal WCK based on the read DQ and the read DQS corresponding to the write DQ output from the memory device 120 .

The training circuit 111 may serialize a test pattern and may output a result to the memory device 120 through the write DQ. For example, the training circuit 111 may serialize a test pattern and may output a result to the memory device 120 as a data signal.

In some embodiments, the write DQ having the serialized test pattern may be transitioned once. For example, when the test pattern has eight bits, the test pattern by which the write DQ is transitioned to the logic “0” from the logic “1” once or is transitioned to the logic “1” from the logic “0” once such as 11110000 or 00001111 may be output to the memory device 120 . As used herein, the term “transitioned” (or similar language) may refer to a transition in a data pattern of bits from the logic “1” to the logic “0” or from the logic “0” to the logic “1”. For example, the data pattern 00001111 may be transitioned once, and a fifth bit of the data pattern may be transitioned (e.g., to “1” from “0”).

In some embodiments, the write DQ having the serialized test pattern may be transitioned at least once. For example, when the test pattern has eight bits, the test pattern by which the write DQ is transitioned to the logic “0” from the logic “1” at least once or is transitioned to the logic “1” from the logic “0” at least once such as 11110101, 11110011, 00001010, or 00001100 may be output to the memory device 120 .

The training circuit 111 may delay the write DQ and output a result to the memory device 120 . The training circuit 111 may adjust a delay value for delaying the write DQ. The memory device 120 may sample the write DQ according to an internal data clock signal IWCK. The memory device 120 may output write data obtained by sampling the write DQ as read data. For example, the memory device 120 may output the write data by using the read DQ and the read DQS. Hereinafter, read data output by the memory device 120 , that is, write data generated when the memory device 120 samples the write DQ, will be referred to as “write data”.

The training circuit 111 may determine a final value of the delay value based on a value of the write data. The value of the write data may be the logic “0” or the logic “1” according to a timing when the write DQ is transitioned and a sampling timing according to the internal data clock signal IWCK. For example, the value of the write data may be the logic “0” when the sampling timing according to the internal data clock signal IWCK is before the timing when the write DQ is transitioned to the logic “0” or the logic “1”, and the value of the write data may be the logic “1” when the sampling timing according to the internal data clock signal IWCK is after the timing when the write DQ is transitioned to the logic “0” or the logic “1”. The training circuit 111 may change the timing when the write DQ is transitioned to the logic “0” or the logic “1” by changing the delay value. That is, the training circuit 111 may delay the write DQ by changing the delay value, may receive the write data obtained by sampling the delayed write DQ, and may determine a final value of the delay value for transitioning the value of the write data. The training circuit 111 may fix the final value of the delay value for transitioning the value of the write data.

The training circuit 111 may change the test pattern so that the timing when the write DQ is transitioned may be changed per one unit interval (UI). In some embodiments, the training circuit 111 may perform the training of the internal data clock signal IWCK at the time of the write operation by changing the test pattern for each one bit. For example, when the training circuit 111 outputs the test pattern of 11110000 as the write DQ and fixes the delay value, the training circuit 111 may change the test pattern for each one bit as 11111000, 11111100, and 11111110.

The training circuit 111 may generate a code so that the memory device 120 may adjust a phase of the data clock signal WCK and may generate the internal data clock signal IWCK. The training circuit 111 may determine the final value of the code based on the value of the write data changeable according to the adjust value of the code. The training circuit 111 may program the final value of the code to the memory device 120 .

In some embodiments, the training circuit 111 may serialize the write DQ obtained by changing the test pattern for each bit and may output the result to the memory device 120 , and the memory device 120 may receive the write data obtained by sampling the write DQ. The training circuit 111 may provide a code to the memory device 120 so that the memory device 120 may shift the data clock signal WCK to generate the internal data clock signal IWCK. The training circuit 111 may adjust the value of the code. The clock signal control circuit 122 may adjust the delay of the data clock signal WCK according to the adjusted code. The clock signal control circuit 122 may buffer the delay-adjusted data clock signal WCK to generate the internal data clock signal IWCK. The data I/O circuit 123 may output the value-changed write data according to the delay of the internal data clock signal IWCK. For example, the value of the write data may be the logic “0” when the sampling timing according to the internal data clock signal IWCK is before the timing when the write DQ is transitioned to the logic “0” or the logic “1”, and the value of the write data may be the logic “1” when the sampling timing according to the internal data clock signal IWCK is after the timing when the write DQ is transitioned to the logic “0” or the logic “1”.

The training circuit 111 may change the sampling timing according to the internal data clock signal IWCK by adjusting the value of the code for adjusting the delay of the internal data clock signal IWCK. The training circuit 111 may adjust the value of the code for adjusting the delay of the internal data clock signal IWCK within the entire range, regarding the 1-bit changed test pattern. For example, when the code has four bits, and the training circuit 111 changes the test pattern by one bit and outputs a result, the value of the code for adjusting the delay of the internal data clock signal IWCK may be adjusted from 0000 to 1111.

In some embodiments, the training circuit 111 may adjust the value of the code to change the sampling timing according to the internal data clock signal IWCK, may receive the write data obtained by sampling the write DQ according to the changed sampling timing according to the internal data clock signal IWCK, and may determine the final value of the code for transitioning the value of the write data. In some embodiments, the training circuit 111 may determine the final values of a plurality of codes that correspond to test patterns changed for each bit. The system on chip 110 may store the final value of the code in mode registers of the memory device 120 according to a mode register write command.

In addition, the system on chip 110 may include various intellectual property (IP) circuits. The system on chip 110 may be referred to as an application processor (AP).

In some embodiments, the system on chip 110 may access the memory device 120 according to a request from a host that is outside the memory system 100 . The system on chip 110 may communicate with the host by using various protocols.

The memory device 120 may be a storage device that is based on the semiconductor device. In some embodiments, the memory device 120 may include a dynamic random access memory (DRAM) device. In some embodiments, the memory device 120 may be a static random access memory (SRAM) device, a thyristor random access memory (TRAM) device, a NAND flash memory device, a NOR flash memory device, a resistive random access memory (RRAM) device, a ferroelectric random access memory (FRAM) device, a phase change random access memory (PRAM) device, a magnetic random access memory (MRAM) device, a solid state drive (SSD), a memory card, and a universal flash storage (UFS). Hereinafter, the memory device 120 will be referred to as a DRAM device (i.e., a synchronous dynamic random access memory (SDRAM) device) synchronized with the data clock signal WCK output by the system on chip 110 . Particularly, the memory device 120 may be a low power double data rate 6 (LPDDR6) SDRAM. The memory device 120 may be a component device in addition to the storage device.

The memory device 120 may include a memory cell array 121 , a clock signal control circuit 122 , and a data input/output (I/O) circuit 123 . The memory cell array 121 may include a plurality of memory cells connected to a plurality of rows and a plurality of columns. In some embodiments, the row is defined by a word line, and the column may be defined by a bit line. The data I/O circuit 123 may store the data transmitted to the memory cell array 121 from the outside (e.g., external to the memory device 120 ) or may output the data stored in the memory cell array 121 to the outside of the memory device 120 (i.e., the system on chip 110 ).

The clock signal control circuit 122 may output the internal data clock signal IWCK based on the data clock signal WCK. The clock signal control circuit 122 may adjust the delay of the data clock signal WCK to output the internal data clock signal IWCK. The clock signal control circuit 122 may adjust the delay of the data clock signal WCK based on the code received from the system on chip 110 . The clock signal control circuit 122 may include a duty cycle adjusting circuit (e.g., a duty cycle adjuster (DCA) and a duty cycle corrector (DCC)). The clock signal control circuit 122 may include a slew rate adjust circuit. The slew rate adjust circuit may adjust a slew rate of the data clock signal WCK and may output a result as an internal data clock signal IWCK.

The data I/O circuit 123 may sample the write DQ based on the internal data clock signal IWCK. The data I/O circuit 123 may output the write data obtained by sampling the write DQ as the read DQ and/or the read DQS. In some embodiments, the data I/O circuit 123 may store the write data in the memory cell array 121 , may read the write data from the memory cell array 121 , and may output a result.

In some embodiments, the data I/O circuit 123 may sample the write DQ delayed by delay values according to the internal data clock signal IWCK. The data I/O circuit 123 may output a plurality of write data that correspond to the write DQ delayed by the delay values as the read DQ and/or the read DQS.

In some embodiments, the data I/O circuit 123 may sample the write DQ generated based on one test pattern according to the respective internal data clock signals IWCK of which the delay is adjusted according to a plurality of codes. The data I/O circuit 123 may output the write data that correspond to the respective internal data clock signals IWCK of which the delay is adjusted according to a plurality of codes as the read DQ and/or the read DQS.

FIG. 2 shows a block diagram of a semiconductor memory device according to some example embodiments.

Referring to FIG. 2 , the memory device 200 may include a memory cell array 210 , a sensing amplifier 211 , a control logic circuit 220 , an address buffer 230 , a row decoder 250 , a column decoder 260 , an I/O gating circuit 270 , a clock signal control circuit 280 , and a data I/O circuit 290 .

The memory cell array 210 may include a plurality of memory cells MC. In some embodiments, the memory cell array 210 may include a plurality of memory banks 210 a to 210 h . FIG. 2 shows eight memory banks BANK 0 to BANK 7 or 210 a to 210 h , but the number of the memory banks is not limited thereto. The respective memory banks 210 a to 210 h may include a plurality of rows, a plurality of columns, and a plurality of memory cells MC arranged on crossing points of the rows and the columns. In some embodiments, the rows may be defined by a plurality of word lines WL, and the columns may be defined by a plurality of bit lines BL.

The control logic circuit 220 may control an operation of the memory device 200 . For example, the control logic circuit 220 may generate control signals so that the memory device 200 may perform a read operation, a write operation, and an offset calibration operation. In some embodiments, the control logic circuit 220 may include a command decoder 221 . The command decoder 221 may decode a command signal CMD received from the system on chip (e.g., 110 of FIG. 1 ) to generate the control signals. The command decoder 221 may decode the command output by the system on chip 110 and may control internal constituent elements of the memory device 200 . For example, the command decoder 221 may decode an activate command, a read command, a write command, a precharge command, a mode register write command, and a multi-purpose command (MPC). The above-described commands may be predetermined in the Joint Electron Devices Engineering Council (JEDEC) standard.

In some embodiments, the control logic circuit 220 may further include a mode register 222 for setting an operation mode of the memory device 200 . The mode register 222 may store the code provided by the address buffer 230 . The number of the mode registers 222 , the address, and the code size may be defined in the JEDEC standard. As issuing the mode register write command and the code, the system on chip 110 may change values stored in the mode register 222 and may set an operating condition and an operation mode of the memory device 200 .

The address buffer 230 may receive the address ADDR provided by the system on chip 110 . The address ADDR may include a row address RA for indicating a row of the memory cell array 210 and a column address CA for indicating a column thereof. The row address RA may be provided to the row decoder 250 , and the column address CA may be provided to the column decoder 260 . In some embodiments, the row address RA may be provided to the row decoder 250 through a row address multiplexer (RA MUX) 251 . In some embodiments, the address ADDR may further include a bank address BA for indicating the memory bank. The bank address BA may be provided to the bank control logic 240 .

The address buffer 230 may provide the address received from the system on chip 110 together with the mode register write command to the mode register 222 and/or the clock signal control circuit 280 as a code OP. Here, the code OP may be transmitted through command and address transmitting paths between the system on chip 110 and the memory device 200 . The code OP may be stored in the mode register 222 so it may be referred to as an operation code (OPCODE) or an operand.

In some embodiments, the memory device 200 may further include a bank control logic 240 for generating a bank control signal in response to the bank address BA. The bank control logic 240 may activate the row decoder 250 corresponding to the bank address BA from among a plurality of row decoders 250 and may activate the column decoder 260 corresponding to the bank address BA from among a plurality of column decoders 260 in response to the bank control signal.

In some embodiments, the memory device 200 may further include a row address multiplexer 251 . The row address multiplexer 251 may receive the row address RA from the address buffer 230 , and may receive a row address REF_RA to be refreshed from the refresh counter 235 . The row address multiplexer 251 may selectively output the row address RA received from the address buffer 230 and the row address REF_RA received from the refresh counter 235 to the row decoder 250 .

The row decoder 250 may select the row to be activated from among a plurality of rows of the memory cell array 210 based on the row address. To achieve this, the row decoder 250 may apply a driving voltage to the word line that corresponds to the row to be activated. In some embodiments, a plurality of row decoders 250 a to 250 h that correspond to a plurality of memory banks 210 a to 210 h may be provided.

The column decoder 260 may select the column to be activated from among a plurality of columns of the memory cell array 210 based on the column address. To achieve this, the column decoder 260 may activate the sensing amplifier 211 that corresponds to the column address CA through the I/O gating circuit 270 . In some embodiments, a plurality of column decoders 260 a to 260 h that respectively correspond to a plurality of memory banks 210 a to 210 h may be provided. In some embodiments, the I/O gating circuit 270 gates the input/output data, and may include a data latch for storing data read from the memory cell array 210 and a write driver for writing data to the memory cell array 210 . The data read from the memory cell array 210 are sensed by the sensing amplifier 211 , and may be stored in the I/O gating circuit 270 (e.g., the data latch). In some embodiments, a plurality of sensing amplifiers 211 a to 211 h that respectively correspond to a plurality of memory banks 210 a to 210 h may be provided.

In some embodiments, the data (e.g., the data stored in the data latch) read from the memory cell array 210 may be provided to the system on chip 110 through the data I/O circuit 290 . The data to be programmed to the memory cell array 210 may be provided to the data I/O circuit 290 from the system on chip 110 , and the data provided to the data I/O circuit 290 may be provided to the I/O gating circuit 270 .

The clock signal control circuit 280 may receive the system clock signal CK and the data clock signal WCK. The clock signal control circuit 280 may buffer the system clock signal CK to generate the internal clock signal ICK. The phase of the buffered internal clock signal ICK may be almost identical with the phase of the system clock signal CK. In some embodiments, the clock signal control circuit 280 may generate the internal clock signal ICK by dividing the system clock signal CK. In some embodiments, the clock signal control circuit 280 may generate the internal data clock signal IWCK by using the data clock signal WCK. The clock signal control circuit 280 may adjust the delay of the data clock signal WCK by using the code OP. The clock signal control circuit 280 may include a slew rate adjust circuit. The slew rate adjust circuit may adjust the delay of the data clock signal WCK based on the code OP. The clock signal control circuit 280 may output the internal clock signal ICK and the internal data clock signal IWCK.

The DQ buffer 282 may receive a write DQ from the system on chip 110 or may output a read DQ to the system on chip 110 . As the DQ is a bidirectional signal, the DQ buffer 282 may include a receiver (not shown) for receiving the write DQ and a transmitter (not shown) for outputting the read DQ. The DQS buffer 284 may receive the write DQS and/or a write DQSB from the system on chip 110 or may output the read DQS and/or a read DQSB to the system on chip 110 . As the DQS is a bidirectional signal, the DQS buffer 284 may include a receiver (not shown) for receiving the write DQS and a transmitter (not shown) for outputting the read DQS.

The data I/O circuit 290 may include a read circuit 292 and a write circuit 294 . The read circuit 292 may receive read data from the sensing amplifier 211 . The read circuit 292 may serialize the read data, and may transmit the read DQS and the read DQ to the system on chip 110 through the DQ buffer 282 and the DQS buffer 284 . The read circuit 292 may be operable based on the internal data clock signal IWCK. The write circuit 294 may receive the write DQ and write DQS from the system on chip 110 through the DQ buffer 282 and the DQS buffer 284 . The write circuit 294 may sample or parallelize the write DQ by using the write DQS and may provide a sampling result to the write driver as write data. The write circuit 294 may be operable based on the internal data clock signal IWCK.

FIG. 3 shows a block diagram of a system on chip according to some example embodiments.

Referring to FIG. 3 , the system on chip 300 may include a memory controller 310 and a double data rate physical layer (DDR PHY) 320 . As used herein, the system on chip 300 may also be referred to as a semiconductor device. The memory controller 310 may control the memory device 200 of FIG. 2 through the DDR PHY 320 . The memory controller 310 may generate commands and addresses for accessing the memory device 200 . The memory controller 310 may generate data to be stored in the memory device 200 . The memory controller 310 may receive the data stored in the memory device 200 .

The DDR PHY 320 may also be referred to as a DDR PHY interface. The DDR PHY 320 may transmit the system clock signal CK, the data clock signal WCK, and the commands and the addresses CMD/ADDR to the memory device 200 based on communications from the memory controller 310 . The DDR PHY 320 may transmit the DQ and the DQS to the memory device 200 based on the communications by the memory controller 310 . The DDR PHY 320 may receive the DQ and the DQS from the memory device 200 . The paths for the DDR PHY 320 to transmit the DQ and the DQS to the memory device 200 and the paths for the memory device 200 to transmit the DQ and the DQS to the DDR PHY 320 may be identical to each other and may be shared.

The memory controller 310 may include a command scheduler 312 , a command queue 314 , a read data queue 316 , and a write data queue 318 . The command queue 314 may store the commands and the addresses issued by an external processor. The command and the address stored in the command queue 314 may be provided to the DDR PHY 320 based on communications from the command scheduler 312 . In this instance, the at least one command and the at least one address stored in the command queue 314 may be provided to the DDR PHY 320 in parallel. The command scheduler 312 may adjust an order of the command(s) and the address(es) stored in the command queue 314 , a time when the command(s) and the address(es) are input to the command queue 314 , and a time when the command(s) and the address(es) are output from the command queue 314 .

The read data queue 316 may store the read data transmitted from the memory device 200 through the DDR PHY 320 by a read request on the memory device 200 of the system on chip 300 . The read data stored in the read data queue 316 may be processed by an external processor. The write data queue 318 may store the write data to be stored in the memory device 200 . The write data stored in the write data queue 318 may be transmitted to the memory device 200 through the DDR PHY 320 according to the write request on the memory device 200 of the system on chip 300 . For example, the command queue 314 , the command scheduler 312 , the read data queue 316 , and the write data queue 318 of the memory controller 310 may be realized by using a hardware method, a software method, or a combination thereof in the system on chip 300 .

The DDR PHY 320 may include a clock signal generator 322 , a data clock signal generator 324 , a command and address generator 326 , a data receiver 328 , a data transmitter 330 , and a training circuit 332 . The clock signal generator 322 , the data clock signal generator 324 , the command and address generator 326 , the data receiver 328 , the data transmitter 330 , and the training circuit 332 of the DDR PHY 320 may be realized by using a hardware method, a software method, or a combination thereof in the system on chip 300 .

The clock signal generator 322 may generate the system clock signal CK output to the memory device 200 . The data clock signal generator 324 may generate the data clock signal WCK output to the memory device 200 . Although not shown in FIG. 3 , the clock signal generator 322 may include a DCC or a DCA for adjusting the duty cycle of the system clock signal CK. The data clock signal generator 324 may include a DCC or a DCA for adjusting the duty cycle of the data clock signal WCK.

The command and address generator 326 may receive the command or the address from the command queue 314 and may transmit the command or the address to the memory device 200 . For example, the number of the command and address transmitting paths between the command and address generator 326 and the memory device 200 , logic states of the signals transmitted through the above-noted transmitting paths, and transmission methods may be defined in the JEDEC standard of the memory device 200 .

The data receiver 328 may receive the read data (or the write data of FIG. 1 ) from the memory device 200 . The read data (or the write data of FIG. 1 ) received by the data receiver 328 from the memory device 200 may also be referred to as an output signal. The data receiver 328 may provide the received read data (e.g., an output signal) to the read data queue 316 . The data receiver 328 may arrange the read DQS and the read DQ or may adjust the skew between the read DQS and the read DQ. The data receiver 328 may include a delay locked loop (DLL) 329 including a plurality of delay cells. For example, the data receiver 328 may delay the read DQS or the read DQ based on a time unit delayed by one delay cell of the DLL 329 , and may find an optimal sampling point for the system on chip 300 to distinguish the read DQ.

The data transmitter 330 may receive the write data from the write data queue 318 . The data transmitter 330 may transmit or output the received write data to the memory device 200 . The write data (e.g., the write DQ) output by the data transmitter 330 may also be referred to as a data signal. The data transmitter 330 may arrange the write DQS and the write DQ or may adjust the skew between the write DQS and the write DQ. The data transmitter 330 may include a DLL 331 including a plurality of delay cells. The data transmitter 330 may delay the write DQS or the write DQ (e.g., a data signal) based on the time unit delayed by one delay cell of the DLL 331 , and may find the optimal sampling point for the memory device 200 to distinguish the write DQ.

The training circuit 332 may control the data transmitter 330 based on control of a training program. The training circuit 332 may output the test pattern as the write DQ. The data transmitter 330 may serialize the test pattern to output the write DQ.

The training circuit 332 may delay the write DQ by using the DLL 331 of the data transmitter 330 and may output a result. The training circuit 332 may change the delay value for delaying the write DQ and may output the write DQ. For example, the training circuit 332 may change the delay value for delaying the write DQ based on the time unit (hereinafter, a delay step) delayed by one delay cell of the DLL 331 . The training circuit 332 may output the write DQ according to the changed delay value.

The data transmitter 330 may delay the write DQ for respective delay steps and may output results, and the data receiver 328 may receive the write data generated by sampling the write DQ delayed for the respective delay steps and output by the memory device 200 of FIG. 2 , as read data (e.g., an output signal).

In some embodiments, the training circuit 332 may determine the final value of the delay value of the write DQ based on the value of the write data. For example, the training circuit 332 may fix the delay value of the write DQ by using the delay value when the value of the write data is transitioned to the logic “1” from the logic “0” or is transitioned to the logic “0” from the logic “1”.

After the delay value of the write DQ is fixed, the training circuit 332 may change the test pattern so that the timing when the write DQ is transitioned may be changed by 1 UI. That is, the training circuit 332 may change the timing when the write DQ is transitioned by 1 UI by changing one bit value of the test pattern. For example, when the test pattern is 8-bit data, the data transmitter 330 may output the write DQ obtained by serializing the test pattern for eight UIs. When first to fourth bit values of the test pattern are “0” and fifth to eighth bit values are “1”, the write DQ may have a voltage of the logic “0” for a period that corresponds to the first to fourth bit values (period of four UIs), and it may have a voltage of the logic “1” for a period that corresponds to the fifth to eighth bit values (period of four UIs). That is, the timing when the write DQ is transitioned to the voltage of the logic “1” from the voltage of the logic “0” may correspond to the fifth bit value of the test pattern. The training circuit 332 may change the fourth bit value of the test pattern to “1” so that the write DQ may have the voltage of the logic “0” for the period that corresponds to the first through third bit values (period of three UIs), or it may change the fifth bit value of the test pattern to “0” so that the write DQ may have the voltage of the logic “0” for the period that corresponds to the first through fifth bit values (period of five UIs). In some embodiments, the training circuit 332 may change the test pattern by one bit, and the data transmitter 330 may output the 1-bit changed test pattern.

The training circuit 332 may control the command and address generator 326 based on communications from the training program. For example, the command and address generator 326 may generate a read command and a write command for training by the training program and may transmit the same to the memory device 200 .

In further detail, the training circuit 332 may control the command and address generator 326 so that the command and address generator 326 may output a mode register write command MRW and a code CODE to the memory device 200 . The training circuit 332 may provide the value of the code CODE to the command and address generator 326 . The mode register write command MRW may be a command for writing the code CODE to the mode register 222 of the memory device 200 of FIG. 2 . The training circuit 332 may set the delay of the internal data clock signal IWCK output by the clock signal control circuit 280 by changing the value of the code CODE stored in the mode register 222 of the memory device 200 through the mode register write command MRW.

In some embodiments, the training circuit 332 may change the value of the code CODE based on the value of the write data obtained by sampling the write DQ based on the 1-bit changed test pattern. The training circuit 332 may change the value of the code CODE and may output the same when outputting the write DQ. In some embodiments, the data transmitter 330 may output the write DQ (e.g., a data signal) based on the 1-bit changed test pattern, and the data receiver 328 may receive the write data generated by sampling the write DQ with the internal data clock signal IWCK of which the delay is adjusted according to the value of the code CODE by the memory device 200 , as read data (e.g., an output signal). The training circuit 332 may determine the final value of the code CODE by using the value of the code CODE when the value of the write data is transitioned to the logic “1” from the logic “0” or is transitioned to the logic “0” from the logic “1”.

According to some embodiments, the training circuit 332 may perform clock signal training of the memory device 200 based on the read DQ of the data receiver 328 . As the training circuit 332 is positioned not in the memory device 200 but in the system on chip 300 , the training circuit 332 may determine the optimal duty cycle to which the signal delay and the slew rate according to a physical interface between the memory device 200 and the system on chip 300 is reflected.

FIG. 4 shows a block diagram of a clock signal control circuit and a write circuit according to some example embodiments.

Referring to FIG. 4 , the clock signal control circuit 400 may include a buffer 410 (for example, including buffers 410 a and 410 b ). The clock signal control circuit 400 may output a plurality of data clock signals WCK 0 , WCK 180 , WCK 90 , and WCK 270 as a plurality of internal data clock signals IWCK 0 , IWCK 180 , IWCK 90 , and IWCK 270 . The data clock signals WCK 0 , WCK 180 , WCK 90 , and WCK 270 may have phase differences of 90 degrees with each other.

The buffer 410 may receive the complementary data clock signals WCK 0 and WCK 180 or WCK 90 and WCK 270 , may adjust delays of the data clock signals WCK 0 and WCK 180 or WCK 90 and WCK 270 , and may output the same as the internal data clock signals IWCK 0 and IWCK 180 or IWCK 90 and IWCK 270 . The buffer 410 may adjust the delays of the data clock signals WCK 0 and WCK 180 or WCK 90 and WCK 270 according to the codes OP 11 , OP 12 , OP 21 , and OP 22 . In some embodiments, the buffer 410 may include a current mode logic (CML) to complementary metal-oxide semiconductor (CMOS) amplifier. In some embodiments, the buffer 410 may adjust the delays of the data clock signals WCK 0 , WCK 90 , WCK 180 , and WCK 270 by controlling the slew rates of the input data clock signals WCK 0 , WCK 90 , WCK 180 , and WCK 270 .

Table 1 exemplarily expresses steps for the buffer 410 b to adjust the delay of the data clock signal WCK 90 according to the value of the second code OP 21 [ n: 0] (n is a positive integer). A type of DELAY is “W” in Table 1. Regarding Table 1, the second code OP 21 [ n: 0] may be configured to be four bits, but the present disclosure is not limited thereto.

When the value of the code OP 21 [3:0] is ‘0000b’, the buffer 410 b may not adjust the delay of the data clock signal WCK 90 . When the value of the code OP 21 [3:0] is changed to one of the values of ‘0001b’ through ‘0111b’, the buffer 410 b may reduce the delay of the data clock signal WCK 90 by the step that corresponds to the value of the code OP 21 [3:0]. The buffer 410 b may adjust the delay of the data clock signal WCK 90 from step −1 to step −7. Similarly, when the value of the code OP 21 [3:0] changes to one of the values of ‘1001b’ through ‘1111b’, the buffer 410 b may increase the delay of the data clock signal WCK 90 by the step that corresponds to the value of the code OP 21 [3:0]. The buffer 410 b may adjust the delay of the data clock signal WCK 90 from step +1 to step +7. Sizes of the unit step in Table 1 may be predetermined. In an embodiment, the “1000b” reserved for future use (RFU) may be a reserved bit for expansion.

The read circuit 402 samples the write DQ in synchronization with the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 transmitted from the clock signal control circuit 400 , and may output sampling data SPD 0 , SPD 1 , SPD 2 , and SPD 3 obtained by sampling the write DQ. The read circuit 402 may include a plurality of sampler circuits 420 a , 420 b , 420 c , and 420 d (i.e., SA 0 , SA 1 , SA 2 and SA 3 ).

The internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 may be respectively applied to the sampler circuits 420 a , 420 b , 420 c , and 420 d . For example, the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 may be applied to clock signal input terminals of the sampler circuits 420 a , 420 b , 420 c , and 420 d , respectively.

The sampler circuits 420 a , 420 b , 420 c , and 420 d may sample the write DQ in synchronization with the applied internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 . For example, the sampler circuit 420 a may sample the first bit and fifth bit values of the write DQ at a rising edge of the internal data clock signal IWCK 0 . The sampler circuit 420 b may sample the second bit and sixth bit values of the write DQ at the rising edge of the internal data clock signal IWCK 90 . The sampler circuit 420 c may sample the third bit and seventh bit values of the write DQ at the rising edge of the internal data clock signal IWCK 180 . The sampler circuit 420 d may sample the fourth bit and eighth bit values of the write DQ at the rising edge of the internal data clock signal IWCK 270 . The sampling data SPD 0 , SPD 1 , SPD 2 , and SPD 3 obtained by sampling the write DQ are write data and may be stored in the memory cell array 210 of FIG. 2 .

The write DQ, the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 , and the sampling data SPD 0 , SPD 1 , SPD 2 , and SPD 3 will now be described with reference to FIGS. 5 to 11 .

FIGS. 5 and 6 show graphs of waveforms of input and output signals of a clock signal control circuit and a write circuit.

Referring to FIG. 5 , when the test pattern is “00001111”, the write DQ marked as DQ may be transitioned to the logic “1” from the logic “0”. For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , a waveform of the write DQ marked as DQ may be the third bit to sixth bit values of the test pattern.

For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the system on chip 300 may delay the write DQ marked as DQ. The system on chip 300 may delay the write DQ marked as DQ by one delay step. The system on chip 300 may delay the write DQ so that the timing when the write DQ marked as DQ is transitioned to the logic “1” from the logic “0” may be synchronized with the rising edge of the internal data clock signal IWCK 0 . It will be described hereafter that the timing when the write DQ marked as DQ is transitioned to the logic “1” from the logic “0” is synchronized with the rising edge of the internal data clock signal IWCK 0 , and the system on chip 300 may synchronize the timing when the write DQ marked as DQ is transitioned to the logic “1” from the logic “0” with the rising edges of the other internal data clock signals IWCK 90 , IWCK 180 , and IWCK 270 . Here, the test pattern may have data that are changed to have the timing when the write DQ marked as DQ sampled by the sampler circuits 420 b , 420 c , and 420 d receiving the respective internal data clock signals IWCK 90 , IWCK 180 , and IWCK 270 is transitioned to the logic “1” from the logic “0” in synchronization with the respective internal data clock signals IWCK 90 , IWCK 180 , and IWCK 270 . For example, the test pattern may be “10000111”, “11000011”, or “11100001”.

In some embodiments, the sampler circuit 420 a may output the sampling data SPD 0 by sampling the write DQ marked as DQ of which the delay value DELAY is adjusted. For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the sampler circuit 420 a may sample the write DQ marked as DQ that corresponds to the fifth bit value of the test pattern at the rising edge of the internal data clock signal IWCK 0 . When the write DQ marked as DQ is advanced to the step −7 for the period of PA 1 , the write DQ marked as DQ at the rising edge of the internal data clock signal IWCK 0 has the logic “1” so the value of the sampling data SPD 0 sampled by the sampler circuit 420 a may be “1”. In a like way, the value of the sampling data SPD 0 for the respective periods PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 may be “1”, . . . , “1”, “0”, “0”, . . . , “0”, . . . , “0”. For the period of PA 8 , the value of the sampling data SPD 0 may be transitioned to “0” from “1”. The system on chip 300 may fix the delay value of the write DQ marked as DQ to the delay value DELAY for the period of PA 8 when the value of the sampling data SPD 0 is transitioned to “0” from “1”.

Referring to FIG. 6 , when the test pattern is “00001111”, the write DQ marked as DQ may be transitioned to the logic “1” from the logic “0”. For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the waveform of the write DQ marked as DQ may have the third bit to sixth bit values of the test pattern.

For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the system on chip 300 may delay the write DQ marked as DQ. The system on chip 300 may delay the write DQ marked as DQ by one delay step. The system on chip 300 may delay the write DQ to synchronize the timing when the write DQ marked as DQ is transitioned to the logic “1” from the logic “0” with the rising edge of the internal data clock signal IWCK 0 .

In some embodiments, the sampler circuit 420 a may output the sampling data SPD 0 by sampling the write DQ marked as DQ of which the delay value DELAY is adjusted. For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the sampler circuit 420 a may sample the write DQ marked as DQ that corresponds to the fifth bit value of the test pattern at the rising edge of the internal data clock signal IWCK 0 . When the write DQ marked as DQ is delayed to the step +7 for the period of PA 1 , the write DQ marked as DQ at the rising edge of the internal data clock signal IWCK 0 has the logic “0” so the value of the sampling data SPD 0 sampled by the sampler circuit 420 a may be “0”. In a like way, the value of the sampling data SPD 0 for the respective periods PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 may be “0”, . . . , “0”, “1”, “1”, . . . , “1”, . . . , “1”. For the period of PA 8 , the value of the sampling data SPD 0 may be transitioned to “1” from “0”. The system on chip 300 may fix the delay value of the write DQ marked as DQ to the delay value DELAY for the period of PA 8 when the value of the sampling data SPD 0 is transitioned to “1” from “0”.

The delay value DELAY has been described to sequentially increase to the step −7 from the step +7 or decrease to the step +7 from the step −7, but the method for the system on chip 300 to adjust the delay value DELAY is not limited thereto.

A method for the system on chip 300 to determine the final value OP 21 of the first code will now be described with reference to FIGS. 7 and 8 .

FIGS. 7 and 8 show tables of sampling data according to delay values of write DQ according to some example embodiments.

The system on chip 300 may determine the final value of the delay value of the write DQ based on the value of the sampling data SPD 0 that corresponds to the delay value of the write DQ. When the test pattern is “00001111”, the system on chip 300 may determine the final value of the delay value of the write DQ based on the delay value DELAY by which the value of the sampling data SPD 0 is transitioned to “1” from “0”. In some embodiments, when the value of the sampling data SPD 0 is transitioned twice to “1” from “0” according to noise, the system on chip 300 may determine the final value of the delay value of the write DQ with an intermediate value of the delay values DELAY that are transitioned twice to “1” from “0”. When the test pattern is “11110000”, the system on chip 300 may determine the final value of the delay value of the write DQ based on the delay value DELAY by which the value of the sampling data SPD 0 is transitioned to “0” from “1”. In some embodiments, when the value of the sampling data SPD 0 is transitioned twice to “0” from “1” by noise, the system on chip 300 may determine the final value of the delay value of the write DQ with the intermediate value of the delay values DELAY that are transitioned twice to “0” from “1”.

Referring to FIG. 7 , when the test pattern is “00001111”, the value of the sampling data SPD 0 according to the delay value DELAY of the changed write DQ is changed to “0” from “1” at the step 0 so the system on chip 300 may determine the final value of the delay value of the write DQ to be a value for indicating the step 0.

When the test pattern is “11110000”, the value of the sampling data SPD 0 according to the delay value DELAY of the changed write DQ is changed to “1” from “0” at the step 0 so the system on chip 300 may determine the final value of the delay value of the write DQ to be a value indicating the step 0.

Referring to FIG. 8 , when the test pattern is “00001111”, the value of the sampling data SPD 0 according to the delay value DELAY of the changed write DQ may be transitioned twice to “0” from “1” by noise. Hence, the value of the sampling data SPD 0 is changed to “0” from “1” at the step 0, and is changed to “0” from “1” at the step +2 so the system on chip 300 may determine the final value of the delay value of the write DQ to be the value indicating the step +1 that is the intermediate value of the step 0 and the step +2. For example, the step 0 may be a first sampling delay value that corresponds to the value of the sampling data SPD 0 being transitioned a first time (e.g., a bit value transitioned to “0” from “1”), the step +2 may be a second sampling delay value that corresponds to the value of the sampling data SPD 0 being transitioned a second time (e.g., a bit value transitioned to “0” from “1”), and the intermediate value may be a delay value between the first sampling delay value and the second sampling delay value (e.g., the value indicating the step +1). For example, the value of the sampling data SPD 0 being transitioned the first time and the value of the sampling data SPD 0 being transitioned the second time may both comprise a bit value being transitioned from 1 to 0. However, the present disclosure is not limited thereto and in other embodiments the value of the sampling data SPD 0 being transitioned the first time and the value of the sampling data SPD 0 being transitioned the second time may both comprise a bit value being transitioned from 0 to 1. In other words, the value of the sampling data SPD 0 being transitioned the first time and the value of the sampling data SPD 0 being transitioned the second time may both comprise a bit value being transitioned from a same one of 1 to 0 or 0 to 1.

The system on chip 300 may determine the final value of the delay value of the write DQ, fix the write DQ with the final value of the determined delay value, and may output the same. By this, the write DQ and the internal data clock signal IWCK 0 may be arranged. When the write DQ and the internal data clock signal IWCK 0 are arranged, the system on chip 300 may train the internal data clock signals IWCK 90 , IWCK 180 , and IWCK 270 .

In some embodiments, the system on chip 300 may change the test pattern for each one bit, may serialize the changed test pattern, and may output the write DQ (e.g., may output a data signal). The system on chip 300 may provide the codes OP 21 , OP 12 , and OP 22 for controlling the buffer 410 corresponding to the write DQ based on the changed test pattern. The system on chip 300 may determine the final value of the codes OP 21 , OP 12 , and OP 22 based on the values of the sampling data SPD 1 , SPD 2 , and SPD 3 confirmed with the read DQ output from the memory device 200 . Hence, the system on chip 300 may train the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 so that the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 may have a constant phase difference.

FIGS. 9 to 11 show graphs of waveforms of input and output signals of a clock signal control circuit and a read circuit.

Referring to FIG. 9 , the system on chip 300 may provide the write DQ marked as DQ based on the test pattern of “00000111” generated by changing the fifth bit of the test pattern of “00001111” to “0” from “1”. The write DQ marked as DQ may be transitioned to the logic “1” from the logic “0” at the time that corresponds to the sixth bit of the test pattern of “00000111”. The system on chip 300 may adjust the code OP 21 for adjusting the delay of the internal data clock signal IWCK 90 provided to the sampler circuit 420 b for sampling the sixth bit. For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the waveform of the write DQ marked as DQ may be the third bit to sixth bit values of the test pattern.

The code OP 21 may be provided to the buffer 410 b of the clock signal control circuit 400 . For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the system on chip 300 may adjust the code OP 21 . For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the clock signal control circuit 400 may adjust the delay of the data clock signal WCK 90 with the steps of −7, . . . , −5, . . . , −1, 0, +1, . . . , +4, . . . , +7 according to the code OP 21 , and may output a result as the internal data clock signal IWCK 90 . The sampler circuit 420 b may output the sampling data SPD 1 according to the delay-adjusted internal data clock signal IWCK 90 . For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the sampler circuit 420 b may sample the write DQ marked as DQ that corresponds to the sixth bit value of the test pattern at the rising edge of the internal data clock signal IWCK 90 .

When the code OP 21 is provided to have the value of the step −7 for the period PA 1 , the write DQ marked as DQ at the rising edge of the internal data clock signal IWCK 90 is the logic “0” so the value of the sampling data SPD 1 sampled by the sampler circuit 420 b may be “0”. In a like way, for the respective periods PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the value of the sampling data SPD 1 may be “0”, . . . , “0”, “1”, “1”, . . . , “1”, . . . , “1”. For the period PA 8 , the value of the sampling data SPD 1 may be transitioned to “1” from “0”. The system on chip 300 may determine the final value of the code OP 21 to be the value (“0”) of the code OP 21 for the period PA 8 during which the value of the sampling data SPD 1 is transitioned to “1” from “0”.

The system on chip 300 may provide the code OP 21 for controlling the buffer 410 b to the memory device 200 , and may determine the final value of the code OP 21 based on the sampling data SPD 1 confirmed with the read DQ output from the memory device 200 . Hence, the system on chip 300 may train the internal data clock signals IWCK 0 and IWCK 90 so that a phase difference between the internal data clock signal IWCK 0 and the internal data clock signal IWCK 90 may be accurately 90 degrees.

Referring to FIG. 10 , the system on chip 300 may provide the write DQ marked as DQ based on the test pattern of “00000011” obtained by changing the sixth bit of the test pattern of “00000111” to “0” from “1”. The write DQ marked as DQ may be transitioned to the logic “1” from the logic “0” at the time that corresponds to the seventh bit of the test pattern of “00000011”. The system on chip 300 may adjust the code OP 12 for adjusting the delay of the internal data clock signal IWCK 180 provided to the sampler circuit 420 c for sampling the seventh bit. For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the waveform of the write DQ marked as DQ may be the fifth bit to eighth bit values of the test pattern.

The code OP 12 may be provided to the buffer 410 a of the clock signal control circuit 400 . For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the system on chip 300 may adjust the code OP 12 . For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the clock signal control circuit 400 may adjust the delay of the data clock signal WCK 180 with the steps −7, . . . , −5, . . . , −1, 0, +1, . . . , +4, . . . , +7 according to the code OP 12 , and may output a result as the internal data clock signal IWCK 180 . The sampler circuit 420 c may output the sampling data SPD 2 according to the delay-adjusted internal data clock signal IWCK 180 . For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the sampler circuit 420 c may sample the write DQ marked as DQ that corresponds to the seventh bit value of the test pattern at the rising edge of the internal data clock signal IWCK 180 .

When the code OP 12 is provided to have the value of the step −7 for the period PA 1 , the write DQ marked as DQ at the rising edge of the internal data clock signal IWCK 180 is the logic “0” so the value of the sampling data SPD 2 sampled by the sampler circuit 420 c may be “0”. In a like way, for the respective periods PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the value of the sampling data SPD 2 may be “0”, . . . , “0”, “1”, “1”, . . . , “1”, . . . , “1”. For the period of PA 8 , the value of the sampling data SPD 2 may be transitioned to “1” from “0”. The system on chip 300 may determine the final value of the code OP 12 to be the value (“0”) of the code OP 12 for the period of PA 8 in which the value of the sampling data SPD 2 is transitioned to “1” from “0”.

The system on chip 300 may provide the code OP 12 for controlling the buffer 410 a to the memory device 200 , and may determine the final value of the code OP 12 based on the sampling data SPD 2 confirmed with the read DQ output from the memory device 200 . Hence, the system on chip 300 may train the internal data clock signals IWCK 90 and IWCK 180 so that the phase difference between the internal data clock signal IWCK 90 and the internal data clock signal IWCK 180 may be accurately 90 degrees.

Referring to FIG. 11 , the system on chip 300 may provide the write DQ marked as DQ based on the test pattern “00000001” obtained by changing the seventh bit of the test pattern of “00000011” to “0” from “1”. The write DQ marked as DQ may be transitioned to the logic “1” from the logic “0” at the time that corresponds to the eighth bit of the test pattern of “00000001”. The system on chip 300 may adjust the code OP 22 for adjusting the delay of the internal data clock signal IWCK 270 provided to the sampler circuit 420 d for sampling the eighth bit. For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the waveform of the write DQ marked as DQ may be the fifth bit to eighth bit values of the test pattern.

The code OP 22 may be provided to the buffer 410 b of the clock signal control circuit 400 . For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the system on chip 300 may adjust the code OP 22 . For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the clock signal control circuit 400 may adjust the delay of the data clock signal WCK 270 with the steps −7, . . . , −5, . . . , −1, 0, +1, . . . , +4, . . . , +7 according to the code OP 22 , and may output the same as the internal data clock signal IWCK 270 . The sampler circuit 420 d may output the sampling data SPD 3 according to the delay-adjusted internal data clock signal IWCK 270 . For the respective periods PA 1 , . . . , PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the sampler circuit 420 d may sample the write DQ marked as DQ that corresponds to the eighth bit value of the test pattern at the rising edge of the internal data clock signal IWCK 270 .

For the period of PA 1 , when the code OP 22 is provided to have the value of the step −7, the write DQ marked as DQ at the rising edge of the internal data clock signal IWCK 270 is the logic “0” so the value of the sampling data SPD 3 sampled by the sampler circuit 420 d may be “0”. In a like way, for the respective periods PA 3 , . . . , PA 7 , PA 8 , PA 9 , . . . , PA 12 , . . . , PA 15 , the value of the sampling data SPD 3 may be “0”, . . . , “0”, “1”, “1”, . . . , “1”, . . . , “1”. For the period of PA 8 , the value of the sampling data SPD 3 may be transitioned to “1” from “0”. The system on chip 300 may determine the final value of the code OP 22 to be the value (“0”) of the code OP 22 for the period of PA 8 when the value of the sampling data SPD 3 is transitioned to “1” from “0”.

The system on chip 300 may provide the code OP 22 for controlling the buffer 410 b to the memory device 200 , and may determine the final value of the code OP 22 based on the sampling data SPD 3 confirmed with the read DQ output from the memory device 200 . Hence, the system on chip 300 may train the internal data clock signals IWCK 180 and IWCK 270 so that the phase difference between the internal data clock signal IWCK 180 and the internal data clock signal IWCK 270 may be accurately 90 degrees.

FIGS. 9 to 11 show that the codes OP 21 , OP 12 , and OP 22 sequentially increase from the step −7 to the step +7, but the method for the system on chip 300 to adjust the codes OP 21 , OP 12 , and OP 22 is not limited thereto.

FIG. 12 shows a flowchart of a clock training method according to some example embodiments.

Referring to FIG. 12 , the system on chip 300 may determine the final value of the delay value of the write DQ (S 1200 ). The system on chip 300 may delay the write DQ with the final value of the delay value of the write DQ and may output a result.

The system on chip 300 may determine the code OP 21 for adjusting the delay of the internal data clock signal IWCK 90 (S 1210 ). The system on chip 300 may determine the code OP 21 for adjusting the delay of the internal data clock signal IWCK 90 of the memory device 200 based on the read DQ output from the memory device 200 .

The system on chip 300 may determine the code OP 12 for adjusting the delay of the internal data clock signal IWCK 180 (S 1220 ). The system on chip 300 may determine the code OP 12 for adjusting the delay of the internal data clock signal IWCK 180 of the memory device 200 based on the read DQ output from the memory device 200 .

The system on chip 300 may determine the code OP 22 for adjusting the delay of the internal data clock signal IWCK 270 (S 1230 ). The system on chip 300 may determine the code OP 22 for adjusting the delay of the internal data clock signal IWCK 270 of the memory device 200 based on the read DQ output from the memory device 200 .

In some embodiments, order of the stages S 1210 , S 1220 , and S 1230 is not limited.

The system on chip 300 may issue the MRW command to program the codes OP 21 , OP 12 , and OP 22 to the mode register 222 of the memory device 200 (S 1240 ). The memory device 200 may adjust the delays of the internal data clock signals IWCK 90 , IWCK 180 , IWCK 270 by using the codes OP 21 , OP 12 , and OP 22 stored in the mode register 222 .

Hence, the system on chip 300 may perform the training of the data clock signal WCK of the memory device 200 in the write operation.

The respective stages of FIG. 12 will now be described in detail with reference to FIGS. 13 and 14 .

FIGS. 13 and 14 show flowcharts of some stages of a clock training method according to some example embodiments.

Referring to FIG. 13 , the system on chip 300 may output a plurality of data clock signals WCK 0 , WCK 180 , WCK 90 , and WCK 270 to the memory device 200 , and may output the write DQ sampled by the memory device 200 according to the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 generated based on a plurality of data clock signals WCK 0 , WCK 180 , WCK 90 , and WCK 270 (S 1300 ). The system on chip 300 may serialize the test pattern and may output a result as the write DQ (e.g., may output a result as a data signal). The test pattern may have the data arranged so that the write DQ may be transitioned corresponding to the rising edge of one of the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 . The system on chip 300 may delay the write DQ for respective groups of a plurality of step units by changing the delay value of the write DQ. In this instance, the system on chip 300 may set the codes OP 11 , OP 12 , OP 21 , and OP 22 as default values and may provide them.

The system on chip 300 may receive the read DQ (e.g., an output signal) from the memory device 200 (S 1302 ).

The system on chip 300 may determine the final value of the delay value for transitioning the sampling data by using the sampling data sampled by one of the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 from the read DQ (S 1304 ). The system on chip 300 may determine the final value of the delay value of the write DQ so that the write DQ may be arranged with one of the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 . The system on chip 300 may determine the final value of the delay value of the write DQ so that the rising edge of one of the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 and the transition timing of the write DQ may be arranged.

Referring to FIG. 14 , the stages S 1210 , S 1220 , and S 1230 of FIG. 12 are described. The system on chip 300 may output the write DQ so that the timing when the write DQ is transitioned may be changed by one unit interval (UI) (S 1400 ). The system on chip 300 may change the timing when the write DQ is transitioned by one UI by changing the test pattern by one bit.

The system on chip 300 may output the code OP 21 or OP 22 for adjusting the delay of the internal data clock signal IWCK 90 or IWCK 270 that has the 90 degrees of the phase difference from the internal data clock signal IWCK 0 arranged with the write DQ to the memory device 200 (S 1402 ). The system on chip 300 may increase/reduce the value of the code OP 21 or OP 22 and may provide a result. In this instance, the system on chip 300 may set the codes OP 11 , OP 12 , OP 22 or OP 11 , OP 12 , and OP 21 as default values and may provide them. When the timing when the write DQ is transitioned is advanced by one UI at the stage of S 1400 , the delay of the internal data clock signal IWCK 270 with the −90 degrees of the phase difference may be adjusted, and when the timing when the write DQ is transitioned is delayed by one UI, the delay of the internal data clock signal IWCK 270 with the +90 degrees of the phase difference may be adjusted. The system on chip 300 will be described hereinafter to delay the timing when the write DQ is transitioned by one UI.

The system on chip 300 may receive the read DQ from the memory device 200 (S 1404 ).

The system on chip 300 may determine the value of the code OP 21 for indicating the delay for the sampling data to be transitioned to be the final value of the code OP 21 by using the sampling data sampled by the internal data clock signal IWCK 90 in the read DQ (S 1406 ).

When the final value of the code OP 21 for delaying the internal data clock signal IWCK 90 is determined, the system on chip 300 may output the write DQ so that the timing when the write DQ is transitioned is changed by one UI (S 1410 ).

The system on chip 300 may output the code OP 12 for adjusting the delay of the internal data clock signal IWCK 180 with the 90 degrees of the phase difference from the internal data clock signal IWCK 90 arranged with the write DQ to the memory device 200 (S 1412 ). The system on chip 300 may increase/reduce the value of the code OP 12 and may provide a result. In this instance, the system on chip 300 may provide the code OP 21 with the value determined at the stage of S 1406 , may set the codes OP 11 and OP 22 as default values, and may provide the same.

The system on chip 300 may receive the read DQ from the memory device 200 (S 1414 ).

The system on chip 300 may determine the value of the code OP 12 for indicating the delay by which the sampling data are transitioned to be the final value of the code OP 12 by using the sampling data sampled by the internal data clock signal IWCK 180 in the read DQ (S 1416 ).

When the final value of the code OP 12 for delaying the internal data clock signal IWCK 180 is determined, the system on chip 300 may output the write DQ so that the timing when the write DQ is transitioned is changed by one UI (S 1420 ).

The system on chip 300 may output the code OP 22 for adjusting the delay of the internal data clock signal IWCK 270 with the 90 degrees of the phase difference from the internal data clock signal IWCK 180 arranged with the write DQ to the memory device 200 (S 1422 ). The system on chip 300 may increase/reduce the value of the code OP 22 and may provide a result. In this instance, the system on chip 300 may provide the codes OP 21 and OP 12 with the values determined at the stages of S 1406 and S 1416 , may set the code OP 11 as a default value, and may provide the same.

The system on chip 300 may receive the read DQ from the memory device 200 (S 1424 ).

The system on chip 300 may determine the value of the code OP 22 for indicating the delay for the sampling data to be transitioned to be the final value of the code OP 22 by using the sampling data sampled by the internal data clock signal IWCK 270 in the read DQ (S 1426 ).

In the above, the system on chip 300 may arrange the write DQ transitioned once with one internal data clock signal, may change the transition timing of the write DQ by each one UI, and may adjust the delay of the internal data clock signal in addition to the internal data clock signal arranged with the write DQ. Therefore, as the internal data clock signal may be trained to be arranged with the sampling timing of the write DQ, the signal may be sampled at the more accurate timing during the actual write operation.

FIG. 15 shows a block diagram of a computer system according to some example embodiments.

Referring to FIG. 15 , the computing system 1500 may include a processor 1510 , a memory 1520 , a memory controller 1530 , a storage device 1540 , a communication interface 1550 , and a bus 1560 . The computing system 1500 may further include other general-purpose constituent elements.

The processor 1510 may control general operations of respective elements of the computing system 1500 . The processor 1510 may be realized with at least one of various processing units including a central processing unit (CPU), an application processor (AP), and a graphics processing unit (GPU).

The memory 1520 may store various types of data and commands. The memory 1520 may be realized with the memory device described with reference to FIGS. 1 to 14 . The memory controller 1530 may control transmission of data or commands to/from the memory 1520 .

The processor 1510 and the memory controller 1530 may be realized with the system on chip described with reference to FIGS. 1 to 14 . In some embodiments, the memory controller 1530 may be provided to an internal element of the processor 1510 . In some embodiments, the memory controller 1530 may be provided to a chip in addition to the processor 1510 .

The memory controller 1530 may output the write DQ to the memory 1520 based on the test pattern with the data arranged so that the write DQ may be changed once. The memory controller 1530 may adjust the delay value of the write DQ so that one of the internal data clock signals IWCK 0 , IWCK 90 , IWCK 180 , and IWCK 270 and the write DQ may be arranged. The memory controller 1530 may, when the write DQ and one internal data clock signal (e.g., IWCK 0 ) are arranged, change the test pattern by one bit and may output the write DQ to the memory 1520 . The memory controller 1530 may output the code for adjusting the delay of the internal data clock signal IWCK 0 from among the remaining internal data clock signals and the internal data clock signal IWCK 90 with the phase difference (e.g., 90 degrees) that corresponds to one UI of the write DQ to the memory 1520 , and may determine the final value of the code for adjusting the delay of the internal data clock signal IWCK 90 by using the value of the sampling data in the read DQ transmitted from the memory 1520 . In a like way, in the case of the other internal data clock signals IWCK 180 and IWCK 270 , the memory controller 1530 may determine the final value of the code for adjusting the respective delays of the internal data clock signals IWCK 180 and IWCK 270 . The memory controller 1530 may provide the final value of the codes to the memory 1520 .

The storage device 1540 may non-temporarily store programs and data. In some embodiments, the storage device 1540 may be realized with a non-volatile memory. The communication interface 1550 may support a wired/wireless network communication of the computing system 1500 . Further, the communication interface 1550 may support various other communication methods in addition to the network communication. The bus 1560 may provide a communication function among the constituent elements of the computing system 1500 . The bus 1560 may include at least one type of bus according to communication protocols among the constituent elements.

In some embodiments, the respective constituent elements or combination of two or more of the constituent elements described with reference to FIGS. 1 to 15 may be realized with a digital circuit, a programmable or non-programmable logic device or array, and an application specific integrated circuit (ASIC).

While this disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.