Manufacturing method of display device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-077458, filed May 10, 2022, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a manufacturing method of a display device.

Recently, display devices to which an organic light emitting diode (OLED) is applied as a display element have been put into practical use. This display element comprises a lower electrode, an organic layer which covers the lower electrode, and an upper electrode which covers the organic layer.

When such a display device is manufactured, a technique which improves the display quality and reliability is required.

FIG. 1 is a diagram showing a configuration example of a display device according to a first embodiment.

FIG. 2 is a diagram showing an example of the layout of subpixels.

FIG. 3 is a diagram showing another example of the layout of subpixels.

FIG. 4 is a schematic cross-sectional view of the display device according to the first embodiment.

FIG. 5 is a diagram showing an example of a structure which could be applied to a partition and its vicinity according to the first embodiment.

FIG. 6 is the flowchart of the manufacturing method of the display device according to the first embodiment.

FIG. 7 A is a schematic cross-sectional view showing a process for forming a rib and the partition according to the first embodiment.

FIG. 7 B is a schematic cross-sectional view showing a process following FIG. 7 A .

FIG. 7 C is a schematic cross-sectional view showing a process following FIG. 7 B .

FIG. 7 D is a schematic cross-sectional view showing a process following FIG. 7 C .

FIG. 7 E is a schematic cross-sectional view showing a process following FIG. 7 D .

FIG. 7 F is a schematic cross-sectional view showing a process following FIG. 7 E .

FIG. 8 A is a schematic cross-sectional view showing a process for forming a display element.

FIG. 8 B is a schematic cross-sectional view showing a process following FIG. 8 A .

FIG. 8 C is a schematic cross-sectional view showing a process following FIG. 8 B .

FIG. 8 D is a schematic cross-sectional view showing a process following FIG. 8 C .

FIG. 8 E is a schematic cross-sectional view showing a process following FIG. 8 D .

FIG. 9 is a flowchart showing a manufacturing method according to a comparative example.

FIG. 10 is a diagram for explaining a misalignment which could be caused when the rib and the partition are formed by the manufacturing method of the comparative example.

FIG. 11 is the flowchart of the manufacturing method of a display device according to a second embodiment.

FIG. 12 A is a schematic cross-sectional view showing a process for forming a rib and a partition according to the second embodiment.

FIG. 12 B is a schematic cross-sectional view showing a process following FIG. 12 A .

FIG. 12 C is a schematic cross-sectional view showing a process following FIG. 12 B .

FIG. 12 D is a schematic cross-sectional view showing a process following FIG. 12 C .

FIG. 12 E is a schematic cross-sectional view showing a process following FIG. 12 D .

In general, according to one embodiment, a manufacturing method allows the manufacture of a display device comprising a partition including a lower portion and an upper portion, the lower portion being provided on a rib comprising a pixel aperture overlapping a display element, the upper portion protruding from a side surface of the lower portion. The method includes forming a lower electrode of the display element, forming a rib layer formed of a material of the rib on the lower electrode, forming a lower layer formed of a material of the lower portion on the rib layer, forming an upper layer formed of a material of the upper portion on the lower layer, forming a resist on the upper layer, forming the rib comprising the pixel aperture overlapping the lower electrode by removing, of the upper layer, the lower layer and the rib layer, a portion exposed from the resist by a first etching process, forming the upper portion by reducing widths of the resist and the upper layer by a second etching process after the first etching process, and forming the lower portion by making a width of the lower layer less than a width of the upper portion by a third etching process after the second etching process.

This manufacturing method can improve the display quality and reliability of a display device.

Embodiments will be described with reference to the accompanying drawings.

The disclosure is merely an example, and proper changes in keeping with the spirit of the invention, which are easily conceivable by a person of ordinary skill in the art, come within the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are illustrated schematically in the drawings, rather than as an accurate representation of what is implemented. However, such schematic illustration is merely exemplary, and in no way restricts the interpretation of the invention. In addition, in the specification and drawings, structural elements which function in the same or a similar manner to those described in connection with preceding drawings are denoted by like reference numbers, detailed description thereof being omitted unless necessary.

In the drawings, in order to facilitate understanding, an X-axis, a Y-axis and a Z-axis orthogonal to each other are shown depending on the need. A direction parallel to the X-axis is referred to as a first direction. A direction parallel to the Y-axis is referred to as a second direction. A direction parallel to the Z-axis is referred to as a third direction. When various elements are viewed parallel to the third direction Z, the appearance is defined as a plan view.

The display device of each embodiment is an organic electroluminescent (EL) display device comprising an organic light emitting diode (OLED) as a display element, and could be mounted on a television, a personal computer, a vehicle-mounted device, a tablet, a smartphone, a mobile phone, etc.

First Embodiment

FIG. 1 is a diagram showing a configuration example of a display device DSP according to a first embodiment. The display device DSP comprises a display area DA which displays an image and a surrounding area SA around the display area DA on an insulating substrate 10 . The substrate 10 may be glass or a resinous film having flexibility.

In the present embodiment, the substrate 10 is rectangular as seen in plan view. It should be noted that the shape of the substrate 10 in plan view is not limited to a rectangular shape and may be another shape such as a square shape, a circular shape or an elliptic shape.

The display area DA comprises a plurality of pixels PX arrayed in matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of subpixels SP. For example, each pixel PX includes a red subpixel SP 1 , a green subpixel SP 2 and a blue subpixel SP 3 . Each pixel PX may include a subpixel SP which exhibits another color such as white in addition to subpixels SP 1 , SP 2 and SP 3 or instead of one of subpixels SP 1 , SP 2 and SP 3 .

Each subpixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1 . The pixel circuit 1 comprises a pixel switch 2 , a drive transistor 3 and a capacitor 4 . The pixel switch 2 and the drive transistor 3 are, for example, switching elements consisting of thin-film transistors.

The gate electrode of the pixel switch 2 is connected to a scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to a signal line SL. The other one is connected to the gate electrode of the drive transistor 3 and the capacitor 4 . In the drive transistor 3 , one of the source electrode and the drain electrode is connected to a power line PL and the capacitor 4 , and the other one is connected to the display element DE. The display element DE is an organic light emitting diode (OLED) as a light emitting element.

It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may comprise more thin-film transistors and capacitors.

FIG. 2 is a diagram showing an example of the layout of subpixels SP 1 , SP 2 and SP 3 which constitute a pixel PX. In the example of FIG. 2 , subpixels SP 1 , SP 2 and SP 3 are arranged in order in the first direction X.

When subpixels SP 1 , SP 2 and SP 3 are provided in line with this layout in each pixel PX, in the display area DA, a column in which a plurality of subpixels SP 1 are provided in the second direction Y, a column in which a plurality of subpixels SP 2 are provided in the second direction Y and a column in which a plurality of subpixels SP 3 are provided in the second direction Y are formed. These columns are arranged in order in the first direction X.

A rib 5 and a partition 6 are provided in the display area DA. The rib 5 comprises a pixel aperture AP 1 in subpixel SP 1 , comprises a pixel aperture AP 2 in subpixel SP 2 and comprises a pixel aperture AP 3 in subpixel SP 3 . In the example of FIG. 2 , each of the pixel apertures AP 1 , AP 2 and AP 3 has a rectangular shape which is long in the second direction Y.

The partition 6 is provided in the boundary of adjacent subpixels SP 1 , SP 2 and SP 3 and overlaps the rib 5 as seen in plan view. The partition 6 comprises a plurality of first partitions 6 x extending in the first direction X and a plurality of second partitions 6 y extending in the second direction Y.

In the example of FIG. 2 , the first partitions 6 x and the second partitions 6 y are connected to each other. In this configuration, the partition 6 has a grating shape surrounding the pixel apertures AP 1 , AP 2 and AP 3 as a whole. In other words, the partition 6 comprises apertures in subpixels SP 1 , SP 2 and SP 3 in a manner similar to that of the rib 5 .

Subpixel SP 1 comprises a lower electrode LE 1 , an upper electrode UE 1 and an organic layer OR 1 overlapping the pixel aperture AP 1 . Subpixel SP 2 comprises a lower electrode LE 2 , an upper electrode UE 2 and an organic layer OR 2 overlapping the pixel aperture AP 2 . Subpixel SP 3 comprises a lower electrode LE 3 , an upper electrode UE 3 and an organic layer OR 3 overlapping the pixel aperture AP 3 .

The lower electrode LE 1 , the upper electrode UE 1 and the organic layer OR 1 constitute the display element DE 1 of subpixel SP 1 . The lower electrode LE 2 , the upper electrode UE 2 and the organic layer OR 2 constitute the display element DE 2 of subpixel SP 2 . The lower electrode LE 3 , the upper electrode UE 3 and the organic layer OR 3 constitute the display element DE 3 of subpixel SP 3 . Each of the display elements DE 1 , DE 2 and DE 3 may include a cap layer as described later.

The lower electrode LE 1 is connected to the pixel circuit 1 (see FIG. 1 ) of subpixel SP 1 through a contact hole CH 1 . The lower electrode LE 2 is connected to the pixel circuit 1 of subpixel SP 2 through a contact hole CH 2 . The lower electrode LE 3 is connected to the pixel circuit 1 of subpixel SP 3 through a contact hole CH 3 . In the example of FIG. 2 , the contact holes CH 1 , CH 2 and CH 3 overlap the first partition 6 x as a whole.

FIG. 3 is a diagram showing another example of the layout of subpixels SP 1 , SP 2 and SP 3 . In the example of FIG. 3 , subpixels SP 1 and SP 3 are arranged in the first direction X. Subpixels SP 2 and SP 3 are also arranged in the first direction X. Further, subpixels SP 1 and SP 2 are arranged in the second direction Y. The pixel aperture AP 2 is larger than the pixel aperture AP 1 . The pixel aperture AP 3 is larger than the pixel aperture AP 2 .

When subpixels SP 1 , SP 2 and SP 3 are provided in line with this layout, in the display area DA, a column in which subpixels SP 1 and SP 2 are alternately provided in the second direction Y and a column in which a plurality of subpixels SP 3 are repeatedly provided in the second direction Y are formed. These columns are alternately arranged in the first direction X.

In the example of FIG. 3 , the contact holes CH 1 and CH 2 entirely overlap the first partition 6 X between the pixel apertures AP 1 and AP 2 which are adjacent to each other in the second direction Y. The contact hole CH 3 entirely overlaps the first partition 6 x between two pixel apertures AP 3 which are adjacent to each other in the second direction Y.

FIG. 4 is a schematic cross-sectional view of the display device DSP. This cross-sectional view corresponds to, for example, the cross-sectional view taken along the III-III line of FIG. 3 . A circuit layer 11 is provided on the substrate 10 described above. The circuit layer 11 includes various circuits and lines such as the pixel circuit 1 , scanning line GL, signal line SL and power line PL shown in FIG. 1 .

The circuit layer 11 is covered with an organic insulating layer 12 . The organic insulating layer 12 functions as a planarization film which planarizes the irregularities formed by the circuit layer 11 . Although not shown in the section of FIG. 4 , all of the contact holes CH 1 , CH 2 and CH 3 described above are provided in the organic insulating layer 12 .

The lower electrodes LE 1 , LE 2 and LE 3 are provided on the organic insulating layer 12 . The rib 5 is provided on the organic insulating layer 12 and the lower electrodes LE 1 , LE 2 and LE 3 and comprises the pixel apertures AP 1 , AP 2 and AP 3 described above. The lower electrodes LE 1 , LE 2 and LE 3 are partly covered with the rib 5 .

The partition 6 includes a conductive lower portion 61 provided on the rib 5 and an upper portion 62 provided on the lower portion 61 . The upper portion 62 has a width greater than that of the lower portion 61 . By this configuration, in FIG. 4 , the both end portions of the upper portion 62 protrude relative to the side surfaces of the lower portion 61 . This shape of the partition 6 may be called an overhang shape.

The organic layer OR 1 covers the lower electrode LE 1 . The upper electrode UE 1 covers the organic layer OR 1 and faces the lower electrode LE 1 . The organic layer OR 2 covers the lower electrode LE 2 . The upper electrode UE 2 covers the organic layer OR 2 and faces the lower electrode LE 2 . The organic layer OR 3 covers the lower electrode LE 3 . The upper electrode UE 3 covers the organic layer OR 3 and faces the lower electrode LE 3 .

In the example of FIG. 4 , a cap layer CP 1 is provided on the upper electrode UE 1 . A cap layer CP 2 is provided on the upper electrode UE 2 . A cap layer CP 3 is provided on the upper electrode UE 3 . The cap layers CP 1 , CP 2 and CP 3 adjust the optical property of the light emitted from the organic layers OR 1 , OR 2 and OR 3 , respectively.

The organic layer OR 1 , the upper electrode UE 1 and the cap layer CP 1 are partly located on the upper portion 62 . These portions are spaced apart from the other portions of the organic layer OR 1 , the upper electrode UE 1 and the cap layer CP 1 (in other words, the portion which constitutes the display element DE 1 ). Similarly, the organic layer OR 2 , the upper electrode UE 2 and the cap layer CP 2 are partly located on the upper portion 62 , and these portions are spaced apart from the other portions of the organic layer OR 2 , the upper electrode UE 2 and the cap layer CP 2 (in other words, the portion which constitutes the display element DE 2 ). Further, the organic layer OR 3 , the upper electrode UE 3 and the cap layer CP 3 are partly located on the upper portion 62 , and these portions are spaced apart from the other portions of the organic layer OR 3 , the upper electrode UE 3 and the cap layer CP 3 (in other words, the portion which constitutes the display element DE 3 ).

A sealing layer SE 1 is provided in subpixel SP 1 . A sealing layer SE 2 is provided in subpixel SP 2 . A sealing layer SE 3 is provided in subpixel SP 3 . The sealing layer SE 1 continuously covers the cap layer CP 1 and the partition 6 around subpixel SP 1 . The sealing layer SE 2 continuously covers the cap layer CP 2 and the partition 6 around subpixel SP 2 . The sealing layer SE 3 continuously covers the cap layer CP 3 and the partition 6 around subpixel SP 3 .

The end portions of the sealing layers SE 1 , SE 2 and SE 3 are located above the upper portions 62 . In the example of FIG. 4 , the organic layer OR 1 , the upper electrode UE 1 , the cap layer CP 1 and the sealing layer SE 1 located on the upper portion 62 of the left partition 6 are spaced apart from the organic layer OR 3 , the upper electrode UE 3 , the cap layer CP 3 and the sealing layer SE 3 located on this upper portion 62 . The organic layer OR 2 , the upper electrode UE 2 , the cap layer CP 2 and the sealing layer SE 2 located on the upper portion 62 of the right partition 6 are spaced apart from the organic layer OR 3 , the upper electrode UE 3 , the cap layer CP 3 and the sealing layer SE 3 located on this upper portion 62 .

The sealing layers SE 1 , SE 2 and SE 3 are covered with a resin layer 13 . The resin layer 13 is covered with a sealing layer 14 . Further, the sealing layer 14 is covered with a resin layer 15 .

Each of the organic insulating layer 12 and the resin layers 13 and 15 is formed of an organic material. Each of the rib 5 and the sealing layers 14 , SE 1 , SE 2 and SE 3 is formed of, for example, an inorganic material such as silicon nitride (SiN), silicon oxide (SiO) or silicon oxynitride (SiON).

Each of the lower electrodes LE 1 , LE 2 and LE 3 comprises an intermediate layer formed of, for example, silver (Ag), and a pair of conductive oxide layers covering the upper and lower surfaces of the intermediate layer. Each conductive oxide layer may be formed of, for example, a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO).

Each of the upper electrodes UE 1 , UE 2 and UE 3 is formed of, for example, a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE 1 , LE 2 and LE 3 correspond to anodes, and the upper electrodes UE 1 , UE 2 and UE 3 correspond to cathodes.

For example, each of the organic layers OR 1 , OR 2 and OR 3 comprises a multilayer structure consisting of a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer.

Each of the cap layers CP 1 , CP 2 and CP 3 is formed by, for example, a multilayer body consisting of a plurality of transparent thin films. As the thin films, the multilayer body may include a thin film formed of an inorganic material and a thin film formed of an organic material. These thin films have refractive indices different from each other. The materials of the thin films constituting the multilayer body are different from the materials of the upper electrodes UE 1 , UE 2 and UE 3 and are also different from the materials of the sealing layers SE 1 , SE 2 and SE 3 . It should be noted that the cap layers CP 1 , CP 2 and CP 3 may be omitted.

Common voltage is applied to the partition 6 . This common voltage is applied to each of the upper electrodes UE 1 , UE 2 and UE 3 which are in contact with the side surfaces of the lower portions 61 . Pixel voltage is applied to the lower electrodes LE 1 , LE 2 and LE 3 through the pixel circuits 1 provided in subpixels SP 1 , SP 2 and SP 3 , respectively.

When a potential difference is formed between the lower electrode LE 1 and the upper electrode UE 1 , the light emitting layer of the organic layer OR 1 emits light in a red wavelength range. When a potential difference is formed between the lower electrode LE 2 and the upper electrode UE 2 , the light emitting layer of the organic layer OR 2 emits light in a green wavelength range. When a potential difference is formed between the lower electrode LE 3 and the upper electrode UE 3 , the light emitting layer of the organic layer OR 3 emits light in a blue wavelength range.

FIG. 5 is a diagram showing an example of a structure which could be applied to the partition 6 and its vicinity. This figure shows, of the partition 6 , the portion located between subpixels SP 1 and SP 3 . It should be noted that a similar configuration can be applied to, of the partition 6 , the portion located between subpixels SP 1 and SP 2 and the portion located between subpixels SP 2 and SP 3 .

The lower portion 61 comprises side surfaces SF 1 and SF 2 . The upper portion 62 comprises end portions ED 1 and ED 2 which protrude from the side surfaces SF 1 and SF 2 , respectively. The upper electrodes UE 1 and UE 3 are in contact with the side surfaces SF 1 and SF 2 under the end portions ED 1 and ED 2 , respectively. In the example of FIG. 5 , the side surfaces SF 1 and SF 2 are substantially parallel to a third direction Z. As another example, the side surfaces SF 1 and SF 2 may incline with respect to the third direction Z such that the lower portion 61 tapers toward the upper side.

The lower portion 61 may be formed of, for example, aluminum (Al). The lower portion 61 may be formed of an aluminum alloy such as an aluminum-neodymium alloy (AlNd) or may comprise a multilayer structure consisting of aluminum and an aluminum alloy. The lower portion 61 may comprise a multilayer structure consisting of a thin first metal layer formed of molybdenum (Mo), etc., and a thick second metal layer formed of aluminum or an aluminum alloy.

The upper portion 62 may be formed of, for example, titanium (Ti) or silicon oxide. The upper portion 62 may comprise a multilayer structure consisting of a first thin film formed of titanium or silicon oxide and a second thin film which covers the first thin film. The second thin film may be formed of, for example, a conductive oxide such as ITO, IZO or IGZO.

The upper portion 62 is formed so as to be thinner than the lower portion 61 . For example, the thickness of the lower portion 61 is approximately 1000 nm, and the thickness of the upper portion 62 is approximately 200 nm.

The organic layers OR 1 , OR 2 and OR 3 , the upper electrodes UE 1 , UE 2 and UE 3 and the cap layers CP 1 , CP 2 and CP 3 are formed by vapor deposition. Regarding this vapor deposition, a shadow area As which is the shadow of the partition 6 is formed on the upper side of the rib 5 . The organic layers OR 1 , OR 2 and OR 3 , the upper electrodes UE 1 , UE 2 and UE 3 and the cap layers CP 1 , CP 2 and CP 3 in the shadow area As are thinner than those in the other area.

In the shadow area As near the side surface SF 1 shown in FIG. 5 , the thicknesses of the organic layer OR 1 , the upper electrode UE 1 and the cap layer CP 1 decrease toward the side surface SF 1 . In the shadow area As near the side surface SF 2 , the thicknesses of the organic layer OR 3 , the upper electrode UE 3 and the cap layer CP 3 decrease toward the side surface SF 2 .

As shown in FIG. 5 , the width of the rib 5 in the width direction of the partition 6 (in other words, a direction orthogonal to the third direction Z) is defined as W 0 . The width of the partition 6 is defined as W 1 . The width of the shadow area As is defined as Ws. Width W 1 is equivalent to the distance between the end portions ED 1 and ED 2 of the upper portion 62 . Width Ws is equivalent to the distance in plan view between the upper portion 62 and the position at which the thicknesses of the organic layer OR 1 , OR 2 or OR 3 , the upper electrode UE 1 , UE 2 or UE 3 and the cap layer CP 1 , CP 2 or CP 3 start to decrease on the rib 5 .

If the shadow area As overlaps the pixel aperture AP 1 , AP 2 or AP 3 , the current density in the overlapping portion is increased, and the degradation of the display element DE 1 , DE 2 or DE 3 is accelerated. Therefore, the width W 0 of the rib 5 needs to be determined such that the shadow area As does not overlap the pixel aperture AP 1 , AP 2 or AP 3 . Specifically, width W 0 is determined so as to satisfy the following condition (1).

W0≥W1+Ws×2  (1)

Now, this specification explains the manufacturing method of the display device DSP.

FIG. 6 is the flowchart of the manufacturing method of the display device DSP according to the present embodiment. FIG. 7 A to FIG. 7 F are schematic cross-sectional views showing a process for forming the rib 5 and the partition 6 . FIG. 8 A to FIG. 8 E are schematic cross-sectional views showing a process for forming the display elements DE 1 , DE 2 and DE 3 .

To manufacture the display device DSP, first, the circuit layer 11 is formed on the substrate 10 , and the organic insulating layer 12 is formed on the circuit layer 11 , and the lower electrodes LE 1 , LE 2 and LE 3 are formed on the organic insulating layer 12 (process P 1 ).

Subsequently, as shown in FIG. 7 A , a rib layer 5 a is formed on the organic insulating layer 12 and the lower electrodes LE 1 , LE 2 and LE 3 (process P 2 ). A lower layer 61 a is formed on the rib layer 5 a (process P 3 ). An upper layer 62 a is formed on the lower layer 61 a (process P 4 ). A resist R 1 is formed on the upper layer 62 a (process P 5 ).

The rib layer 5 a is a layer which is the base of the rib 5 , and is formed of the material of the rib 5 . The lower layer 61 a is a layer which is the base of the lower portion 61 of the partition 6 , and is formed of the material of the lower portion 61 . The upper layer 62 a is a layer which is the base of the upper portion 62 of the partition 6 , and is formed of the material of the upper portion 62 .

The process P 5 of forming the resist R 1 includes, as shown in FIG. 6 , the process P 5 a of applying a resist material to the entire substrate, the process P 5 b of exposing the applied resist material, the process P 5 c of developing the resist material, and the process P 5 d of baking the developed resist material. Through these processes P 5 a , P 5 b , P 5 c and P 5 d , the resist R 1 having the same planar shape as the rib 5 shown in FIG. 2 and FIG. 3 is formed.

Subsequently, a first etching process P 6 is performed. In the first etching process P 6 , as shown in FIG. 7 B , of the upper layer 62 a , the lower layer 61 a and the rib layer 5 a , the portions exposed from the resist R 1 are removed. By this process, the rib 5 comprising the pixel apertures AP 1 , AP 2 and AP 3 overlapping the lower electrodes LE 1 , LE 2 and LE 3 is formed.

As shown in FIG. 6 , the first etching process P 6 includes first dry etching Poa for removing, of the upper layer 62 a , the portion exposed from the resist R 1 , second dry etching P 6 b for removing, of the lower layer 61 a , the portion exposed from the resist R 1 , and third dry etching P 6 c for removing, of the rib layer 5 a , the portion exposed from the resist R 1 . It should be noted that, instead of dry etching, wet etching may be applied to pattern at least one of the upper layer 62 a , the lower layer 61 a and the rib layer 5 a.

When the upper layer 62 a and the lower layer 61 a can be etched on the condition that the etch selectivity is less, the upper layer 62 a and the lower layer 61 a may be patterned together by one etching process. Similarly, when the lower layer 61 a and the rib layer 5 a can be etched on the condition that the etch selectivity is less, the lower layer 61 a and the rib layer 5 a may be patterned together by one etching process. Further, the upper layer 62 a , the lower layer 61 a and the rib layer 5 a may be patterned together by one etching process.

After the first etching process P 6 , a second etching process P 7 for reducing the widths of the resist R 1 and the upper layer 62 a is performed. In the present embodiment, the second etching process P 7 includes the ashing Pla of the resist R 1 , and fourth dry etching P 7 b for the upper layer 62 a.

In the ashing Pla, as shown in FIG. 7 C , the resist R 1 corrodes as a whole. In this way, the height and width of the resist R 1 are reduced. For example, before the ashing Pa, the height of the resist R 1 is approximately 2.0 μm. After the ashing Pa, the height is decreased to two thirds or less, for example, approximately 1.2 μm. The amount of reduction of the width of the resist R 1 by the ashing P 7 a is greater than or equal to at least twice the width Ws of the shadow area As described above. Hereinafter, the resist R 1 which underwent the ashing Pla is referred to as a resist R 1 a.

In the fourth dry etching P 7 b , as shown in FIG. 7 D , of the upper layer 62 a , the portion exposed from the resist R 1 a is removed. By this process, the upper portion 62 of the partition 6 is formed.

After the second etching process P 7 , a third etching process P 8 is performed. The third etching process P 8 includes isotropic wet etching for the lower layer 61 a . By this wet etching, as shown in FIG. 7 E , the width of the lower layer 61 a is made less than that of the upper portion 62 , thereby forming the lower portion 61 of the partition 6 .

After the rib 5 and the partition 6 are formed using the resist R 1 (resist R 1 a ) as described above, the resist R 1 a is removed by an exfoliation liquid as shown in FIG. 7 F (process P 9 ).

Subsequently, the display elements DE 1 , DE 2 and DE 3 are formed (process P 10 ). In the present embodiment, for example, this specification assumes a case where the display element DE 3 is formed firstly, and the display element DE 2 is formed secondly, and the display element DE 1 is formed lastly. It should be noted that the formation order of the display elements DE 1 , DE 2 and DE 3 is not limited to this example.

To form the display element DE 3 , first, as shown in FIG. 8 A , the organic layer OR 3 , the upper electrode UE 3 , the cap layer CP 3 and the sealing layer SE 3 are formed in order by vapor deposition for the entire substrate. At this time, the organic layer OR 3 , the upper electrode UE 3 and the cap layer CP 3 formed in subpixels SP 1 , SP 2 and SP 3 are divided by the partition 6 having an overhang shape. The sealing layer SE 3 continuously covers the display element DE 3 including the lower electrode LE 3 , the organic layer OR 3 , the upper electrode UE 3 and the cap layer CP 3 and the partition 6 .

Regarding the vapor deposition of the organic layer OR 3 , the upper electrode UE 3 and the cap layer CP 3 , the materials of these elements are emitted from an evaporation source at a predetermined spread angle θ. Thus, near the partition 6 , the shadow area As in which the amount of deposition of these materials is less is formed as described above.

Subsequently, as shown in FIG. 8 B , a resist R 2 is provided on the sealing layer SE 3 . The resist R 2 has been patterned so as to overlap subpixel SP 3 . The resist R 2 is also located above, of the partition 6 surrounding subpixel SP 3 , a portion which is close to subpixel SP 3 .

Further, of the organic layer OR 3 , the upper electrode UE 3 , the cap layer CP 3 and the sealing layer SE 3 , the portions exposed from the resist R 2 are removed as shown in FIG. 8 C by etching using the resist R 2 as a mask. This process enables the acquisition of the following substrate. In subpixel SP 3 , the display element DE 3 including the lower electrode LE 3 , the organic layer OR 3 , the upper electrode UE 3 and the cap layer CP 3 is formed, and the sealing layer SE 3 which covers the display element DE 3 is also formed. No display element or sealing layer is formed in subpixel SP 1 or SP 2 .

The etching in the process of FIG. 8 C includes, for example, dry etching for the sealing layer SE 3 , wet etching or ashing for the cap layer CP 3 , wet etching for the upper electrode UE 3 and ashing for the organic layer OR 3 .

Subsequently, the resist R 2 is removed, and a process for forming the display element DE 2 in subpixel SP 2 is performed by a procedure similar to that of the display element DE 3 . This process enables the acquisition of the following substrate. As shown in FIG. 8 D , further, in subpixel SP 2 , the display element DE 2 including the lower electrode LE 2 , the organic layer OR 2 , the upper electrode UE 2 and the cap layer CP 2 is formed, and the sealing layer SE 2 which covers the display element DE 2 is also formed.

After the formation of the display element DE 2 , a process for forming the display element DE 1 in subpixel SP 1 is performed by a procedure similar to that of the display element DE 3 . This process enables the acquisition of the following substrate. As shown in FIG. 8 E , further, in subpixel SP 1 , the display element DE 1 including the lower electrode LE 1 , the organic layer OR 1 , the upper electrode UE 1 and the cap layer CP 1 is formed, and the sealing layer SE 1 which covers the display element DE 1 is also formed.

After the formation of the display elements DE 1 , DE 2 and DE 3 , the processes of forming the resin layer 13 , the sealing layer 14 and the resin layer 15 are performed in order (process P 11 ). In this way, the display device DSP comprising the structure shown in FIG. 4 is completed.

The effects obtained by the display device DSP and the manufacturing method thereof in the present embodiment described above are explained with reference to FIG. 9 and FIG. 10 .

FIG. 9 is a flowchart showing a manufacturing method according to a comparative example of the present embodiment. In this manufacturing method, first, the circuit layer 11 , the organic insulating layer 12 and the lower electrodes LE 1 , LE 2 and LE 3 are formed (process Q 1 ).

Subsequently, the rib layer 5 a is formed (process Q 2 ), and a first resist is formed on the rib layer 5 a (process Q 3 ). The process Q 3 of forming the first resist includes the process Q 3 of applying a resist material to the upper side of the rib layer 5 a , the process Q 3 b of exposing the resist material, the process Q 3 c of developing the exposed resist material and the process Q 3 d of baking the developed resist material. In this way, the first resist having the same planar shape as the rib 5 is formed. After the formation of the first resist, of the rib layer 5 a , the portion exposed from the first resist is removed by etching (process Q 4 ). The rib 5 comprising the pixel apertures AP 1 , AP 2 and AP 3 is formed. Subsequently, the first resist is removed (process Q 5 ).

Subsequently, the lower layer 61 a which covers the rib 5 is formed (process Q 6 ). The upper layer 62 a which covers the lower layer 61 a is formed (process Q 7 ). Further, a second resist is formed on the upper layer 62 a (process Q 8 ). The process Q 8 of forming the second resist includes the process Q 8 a of applying a resist material to the upper side of the upper layer 62 a , the process Q 8 b of exposing the resist material, the process Q 8 c of developing the exposed resist material and the process Q 8 d of baking the developed resist material. In this way, the second resist having the same planar shape as the upper portion 62 of the partition 6 is formed.

After the formation of the second resist, of the upper layer 62 a , the portion exposed from the second resist is removed by etching (process Q 9 ). Further, of the lower layer 61 a , the portion exposed from the second resist is removed by etching (process Q 10 ). In this etching, the width of the lower layer 61 a is made less than that of the upper portion 62 , thereby forming the lower portion 61 .

Subsequently, the second resist is removed (process Q 11 ). The display elements DE 1 , DE 2 and DE 3 are formed by a procedure similar to that of FIG. 8 A to FIG. 8 E (process Q 12 ). The resin layer 13 , the sealing layer 14 and the resin layer 15 are formed (process Q 13 ).

As described above, in the manufacturing method of the comparative example, the first resist for patterning the rib layer 5 a which is the base of the rib 5 and the second resist for patterning the lower and upper layers 61 a and 62 a which are the base of the partition 6 are separate bodies formed by individual photolithographic processes (processes Q 3 a , Q 3 b , Q 3 c and Q 3 d and processes Q 8 a , Q 8 b , Q 8 c and Q 8 d ). In this case, there is a possibility that the first resist and the second resist deviate from the design positions because of the misalignment of the exposure position at the time of forming the first resist or the misalignment of the exposure position at the time of forming the second resist. If the first resist or the second resist deviates from the design position, the positions of the rib 5 and the partition 6 are also relatively misaligned.

FIG. 10 is a diagram for explaining a misalignment which could be caused when the rib 5 and the partition 6 are formed by the manufacturing method of the comparative example. Here, it is assumed that, when the rib 5 and the partition 6 are formed as designed, the center C 1 of the rib 5 is coincident with the center C 2 of the partition 6 at position C 0 . In a manner similar to that of the example of FIG. 5 , the width of the rib 5 is W 0 . The width of the upper portion 62 of the partition 6 is W 1 . The width of the shadow area As is Ws.

In FIG. 10 ( a ) , the rib 5 or the partition 6 is not misaligned, and both center C 1 and center C 2 are coincident with position C 0 .

In FIG. 10 ( b ) , center C 1 deviates from position C 0 to the left side by distance d 1 , and center C 2 deviates from position C 0 to the right side by distance d 2 .

In FIG. 10 ( c ) , center C 1 deviates from position C 0 to the right side by distance d 1 , and center C 2 deviates from position C 0 to the left side by distance d 2 .

Here, distance d 1 is assumed to be the maximum amount of deviation which could be caused at the time of forming the rib 5 from position C 0 . Distance d 2 is assumed to be the maximum amount of deviation which could be caused at the time of forming the partition 6 from position C 0 . In this case, FIG. 10 ( b ) corresponds to a state in which the partition 6 deviates to the right side with respect to the rib 5 to the maximum extent. FIG. 10 ( c ) corresponds to a state in which the partition 6 deviates to the left side with respect to the rib 5 to the maximum extent.

The width W 0 of the rib 5 needs to be determined such that the entire shadow area As is located on the rib 5 in the states of FIG. 10 ( b ) and FIG. 10 ( c ) . Therefore, in the state of FIG. 10 ( b ) , the distance L 1 between the partition 6 and the right end of the rib 5 has to be greater than or equal to the width Ws of the shadow area As. In the state of FIG. 10 ( c ) , the distance L 2 between the partition 6 and the left end of the rib 5 also has to be greater than or equal to width Ws. In consideration of the above matters, width W 0 is determined so as to satisfy the following condition (2).

W0≥W1+Ws×2+(d1+d2)×2  (2)

If width W 0 is increased to satisfy this condition, the pixel apertures AP 1 , AP 2 and AP 3 are made small. In this case, as the areas of the light emission of the display elements DE 1 , DE 2 and DE 3 are made small, the luminances of the display elements DE 1 , DE 2 and DE 3 are decreased. The luminances of the display elements DE 1 , DE 2 and DE 3 can be increased by supplying a high current to the display elements DE 1 , DE 2 and DE 3 . However, in this case, the degradation of the display elements DE 1 , DE 2 and DE 3 is accelerated, and the life of these display elements is shortened. Thus, in the manufacturing method of the comparative example, it is difficult to improve both the display quality and the reliability of the display device.

In the manufacturing method of the present embodiment, as shown in FIG. 7 A to FIG. 7 F , both the rib 5 and the partition 6 are formed using the resist R 1 . In this case, the relative misalignment of the rib 5 and the partition 6 shown in the comparative example is difficult to cause. Thus, it is possible to determine width W 0 by the condition (1) described above.

When width W 0 is determined by the condition (1), the pixel apertures AP 1 , AP 2 and AP 3 can be made large compared to the structure of the comparative example. In this case, the luminances of the display elements DE 1 , DE 2 and DE 3 are improved compared to the comparative example. If the pixel apertures AP 1 , AP 2 and AP 3 are made large while maintaining the luminances of the display elements DE 1 , DE 2 and DE 3 so as to be equal to those of the comparative example, the current densities of the display elements DE 1 , DE 2 and DE 3 are decreased. In this case, the life of the display elements DE 1 , DE 2 and DE 3 can be lengthened.

As a method for forming the display elements of organic EL display devices, the display elements of respective colors may be formed in series using a metal mask without providing the partition 6 . In this case, in consideration of the misalignment between the metal mask and the substrate, the rib 5 needs to be formed so as to be wider than that of the present embodiment and the comparative example. To the contrary, when the rib 5 , the partition 6 and the display elements DE 1 , DE 2 and DE 3 are formed by the method of the present embodiment, the width of the rib 5 can be largely reduced. Thus, for example, even a high-definition display device with a resolution greater than or equal to 1500 ppi can be manufactured.

Second Embodiment

A second embodiment is explained. The second embodiment is different from the first embodiment in terms of the manufacturing method of the display device DSP. The configuration of the display device DSP is the same as the first embodiment.

FIG. 11 is the flowchart of the manufacturing method of a display device DSP according to the second embodiment. FIG. 12 A to FIG. 12 E are schematic cross-sectional views showing a process for forming a rib 5 and a partition 6 according to the second embodiment.

First, in a manner similar to that of the first embodiment, a circuit layer 11 , an organic insulating layer 12 and lower electrodes LE 1 , LE 2 and LE 3 are formed (process P 1 ). Further, as shown in FIG. 12 A , a rib layer 5 a is formed (process P 2 ). A lower layer 61 a is formed (process P 3 ). An upper layer 62 a is formed (process P 4 ). A resist R 1 is formed (process P 5 ). The process P 5 of forming the resist R 1 includes processes P 5 a , P 5 b , P 5 c and P 5 d in a manner similar to that of the first embodiment.

Subsequently, a first etching process P 6 is performed, and as shown in FIG. 12 B , of the upper layer 62 a , the lower layer 61 a and the rib layer 5 a , the portions exposed from the resist R 1 are removed. For example, the first etching process P 6 includes dry etching processes P 6 a , P 6 b and P 6 c in a manner similar to that of the first embodiment.

After the first etching process P 6 , a second etching process P 7 for reducing the widths of the resist R 1 and the upper layer 62 a is performed. In the present embodiment, the second etching process P 7 includes fourth dry etching for reducing the widths of the resist R 1 and the upper layer 62 a by affecting both of them. In other words, the fourth dry etching is performed on the condition that the etch selectivity for the resist R 1 and the upper layer 62 a is less. As shown in FIG. 12 C , the fourth dry etching allows the formation of a resist R 1 a in which the height and width are reduced, and an upper portion 62 .

Subsequently, by a third etching process P 8 similar to that of the first embodiment, as shown in FIG. 12 D , the width of the lower layer 61 a is made less than that of the upper portion 62 , thereby forming the lower portion 61 of the partition 6 . Further, as shown in FIG. 12 E , the resist R 1 a is removed by an exfoliation liquid (process P 9 ).

After the formation of the rib 5 and the partition 6 , display elements DE 1 , DE 2 and DE 3 are formed by a procedure similar to that of FIG. 8 A to FIG. 8 E (process P 10 ). Subsequently, a resin layer 13 , a sealing layer 14 and a resin layer 15 are formed (process P 11 ).

In the manufacturing method of the embodiment described above, the widths of both the resist R 1 and the upper layer 62 a are reduced by the fourth dry etching. Thus, the number of etching processes can be reduced compared to the first embodiment. The display device DSP can be effectively manufactured.

To improve the accuracy of the patterning of the resist R 1 and the upper layer 62 a by the fourth dry etching, as shown by the broken line in FIG. 12 A and FIG. 12 B , the thickness of the resist R 1 may partly vary. The resist R 1 shown by the broken line includes a pair of thin portions J 1 and J 2 located in the both end portions in the width direction, and a thick portion K between the thin portions J 1 and J 2 . The thin portions J 1 and J 2 can be obtained by, for example, exposing areas corresponding to the thin portions J 1 and J 2 with a halftone in process P 5 b.

When the resist R 1 includes the thin portions J 1 and J 2 , in the fourth dry etching, the thin portions J 1 and J 2 are preferentially lost. Thus, the amount of reduction of the width of the resist R 1 can be accurately controlled. It should be noted that the thin portions J 1 and J 2 may be provided in the resist R 1 in the first embodiment.

All of the display devices and manufacturing methods thereof that can be implemented by a person of ordinary skill in the art through arbitrary design changes to the display device and manufacturing method thereof described above as the embodiments of the present invention come within the scope of the present invention as long as they are in keeping with the spirit of the present invention.

Various modification examples which may be conceived by a person of ordinary skill in the art in the scope of the idea of the present invention will also fall within the scope of the invention. For example, even if a person of ordinary skill in the art arbitrarily modifies the above embodiments by adding or deleting a structural element or changing the design of a structural element, or by adding or omitting a step or changing the condition of a step, all of the modifications fall within the scope of the present invention as long as they are in keeping with the spirit of the invention.

Further, other effects which may be obtained from each embodiment and are self-explanatory from the descriptions of the specification or can be arbitrarily conceived by a person of ordinary skill in the art are considered as the effects of the present invention as a matter of course.