Transmitting apparatus and interleaving method thereof

This is continuation of U.S. application Ser. No. 17/329,870 filed May 25, 2021, which is a continuation of U.S. application Ser. No. 16/510,405, filed on Jul. 12, 2019, now U.S. Pat. No. 11,050,411, issued on Jun. 29, 2021, which is a continuation of U.S. application Ser. No. 14/625,795 filed Feb. 19, 2015, now U.S. Pat. No. 10,425,110, issued on Sep. 24, 2019, which claims priority from U.S. Provisional Application No. 61/941,708 filed on Feb. 19, 2014 and Korean Patent Application No. 10-2015-0024183 filed on Feb. 17, 2015, the disclosures of which are incorporated herein by reference in their entirety.

1. Field

Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.

2. Description of the Related Art

In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as high quality digital televisions, portable multimedia players and portable broadcasting equipment are increasingly used in recent years, there is an increasing demand for methods for supporting various receiving methods of digital broadcasting services.

In order to meet such demand, standard groups are establishing various standards and are providing a variety of services to satisfy users needs. Therefore, there is a need for a method for providing improved services to users with high decoding and receiving performance.

Exemplary embodiments of the inventive concept may overcome the above disadvantages and other disadvantages not described above. However, it is understood that the exemplary embodiment are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.

The exemplary embodiments provide a transmitting apparatus which can map a bit included in a predetermined bit group from among a plurality of bit groups of a low density parity check (LDPC) codeword onto a predetermined bit of a modulation symbol, and transmit the bit, and an interleaving method thereof.

According to an aspect of an exemplary embodiment, there is provided a transmitting apparatus including: an encoder configured to generate an LDPC codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Each of the plurality of bit groups may be formed of M number of bits. M may be a common divisor of N ldpc and K ldpc and may be determined to satisfy Q ldpc =(N ldpc −K ldpc )/M. In this case, Q ldpc may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N ldpc may be a length of the LDPC codeword, and K ldpc may be a length of information word bits of the LDPC codeword.

The interleaver may include: a parity interleaver configured to interleave parity bits of the LDPC codeword; a group interleaver configured to divide the parity-interleaved LDPC codeword by the plurality of bit groups and rearrange an order of the plurality of bit groups in bit group wise; and a block interleaver configured to interleave the plurality of bit groups the order of which is rearranged.

The group interleaver may be configured to rearrange the order of the plurality of bit groups in bit group wise by using the following equation:

Y j =X π(j) (0≤ j<N group ),

where X j is a j th bit group before the plurality of bit groups are interleaved, Y j is a j th bit group after the plurality of bit groups are interleaved, N group is a total number of the plurality of bit groups, and π(j) is a parameter indicating an interleaving order.

Here, π(j) may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 6/15, π(j) may be defined as in table 11.

When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 10/15, π(j) may be defined as in table 14.

When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, π(j) may be defined as in table 15.

When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, π(j) may be defined as in table 17.

When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 8/15, π(j) may be defined as in table 18.

When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, π(j) may be defined as in table 21.

The block interleaver may be configured to interleave by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

The block interleaver may be configured to serially write, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then divide and write the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.

According to an aspect of another exemplary embodiment, there is provided an interleaving method of a transmitting apparatus, including: generating an LDPC codeword by LDPC encoding based on a parity check matrix; interleaving the LDPC codeword; and mapping the interleaved LDPC codeword onto a modulation symbol, wherein the mapping comprises mapping a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Each of the plurality of bit groups may be formed of M number of bits, and M may be a common divisor of N ldpc and K ldpc and may be determined to satisfy Q ldpc =(N ldpc −K ldpc )/M. In this case, Q ldpc may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N ldpc may be a length of the LDPC codeword, and K ldpc may be a length of information word bits of the LDPC codeword.

The interleaving may include: interleaving parity bits of the LDPC codeword; dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging an order of the plurality of bit groups in bit group wise; and interleaving the plurality of bit groups the order of which is rearranged.

The rearranging in bit group wise may include rearranging the order of the plurality of bit groups in bit group wise by using the following equation:

Y j =X π(j) (0≤1< N group ),

where X j is a j th bit group before the plurality of bit groups are interleaved, Y j is a j th bit group after the plurality of bit groups are interleaved, N group is a total number of the plurality of bit groups, and π(j) is a parameter indicating an interleaving order.

Here, π(j) may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 6/15, π(j) may be defined as in table 11.

When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 10/15, π(j) may be defined as in table 14.

When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, π(j) may be defined as in table 15.

When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, π(j) may be defined as in table 17.

When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 8/15, π(j) may be defined as in table 18.

When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, π(j) may be defined as in table 21.

The interleaving the plurality of bit groups may include interleaving by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

The interleaving the plurality of bit groups may include serially writing, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.

According to various exemplary embodiments, improved decoding and receiving performance can be provided.

The above and/or other aspects will be more apparent by describing in detail exemplary embodiments, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus, according to an exemplary embodiment;

FIGS. 2 to 4 are views to illustrate a configuration of a parity check matrix, according to exemplary embodiments;

FIG. 5 is a block diagram to illustrate a configuration of an interleaver, according to an exemplary embodiment;

FIGS. 6 to 8 are views to illustrate an interleaving method, according to exemplary embodiments;

FIGS. 9 to 14 are views to illustrate an interleaving method of a block interleaver, according to exemplary embodiments;

FIG. 15 is a view to illustrate an operation of a demultiplexer, according to an exemplary embodiment;

FIGS. 16 and 17 are views to illustrate a method for designing an interleaving pattern, according to exemplary embodiments;

FIG. 18 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment;

FIG. 19 is a block diagram to illustrate a configuration of a deinterleaver, according to an exemplary embodiment;

FIG. 20 is a view to illustrate a deinterleaving method of a block deinterleaver, according to an exemplary embodiment; and

FIG. 21 is a flowchart to illustrate an interleaving method, according to an exemplary embodiment.

Hereinafter, various exemplary embodiments will be described in greater detail with reference to the accompanying drawings.

In the following description, same reference numerals are used for the same elements when they are depicted in different drawings. The matters defined in the description, such as detailed construction and elements, are provided to assist in a comprehensive understanding of the exemplary embodiments. Thus, it is apparent that the exemplary embodiments can be carried out without those specifically defined matters. Also, functions or elements known in the related art are not described in detail since they would obscure the exemplary embodiments with unnecessary detail.

FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment. Referring to FIG. 1 , the transmitting apparatus 100 includes an encoder 110 , an interleaver 120 , and a modulator 130 (or a constellation mapper).

The encoder 110 generates a low density parity check (LDPC) codeword by performing LDPC encoding based on a parity check matrix. To achieve this, the encoder 110 may include an LDPC encoder (not shown) to perform the LDPC encoding.

Specifically, the encoder 110 LDPC-encodes information word (or information) bits to generate the LDPC codeword which is formed of information word bits and parity bits (that is, LDPC parity bits). Here, bits input to the encoder 110 may be used as the information word bits. Also, since an LDPC code is a systematic code, the information word bits may be included in the LDPC codeword as they are.

The LDPC codeword is formed of the information word bits and the parity bits. For example, the LDPC codeword is formed of N ldpc number of bits, and includes K ldpc number of information word bits and N parity =N ldpc −K ldpc number of parity bits.

In this case, the encoder 110 may generate the LDPC codeword by performing the LDPC encoding based on the parity check matrix. That is, since the LDPC encoding is a process for generating an LDPC codeword to satisfy H·C T =0, the encoder 110 may use the parity check matrix when performing the LDPC encoding. Herein, H is a parity check matrix and C is an LDPC codeword.

For the LDPC encoding, the transmitting apparatus 100 may include a memory and may pre-store parity check matrices of various formats.

For example, the transmitting apparatus 100 may pre-store parity check matrices which are defined in Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2), etc., or may pre-store parity check matrices which are defined in the North America digital broadcasting standard system Advanced Television System Committee (ATSC) 3.0 standards, which are currently being established. However, this is merely an example and the transmitting apparatus 100 may pre-store parity check matrices of other formats in addition to these parity check matrices.

Hereinafter, a parity check matrix according to various exemplary embodiments will be explained in detail with reference to the drawings. In the parity check matrix, elements other than elements having 1 have 0.

For example, the parity check matrix according to an exemplary embodiment may have a configuration of FIG. 2 .

Referring to FIG. 2 , a parity check matrix 200 is formed of an information word submatrix(or an information submatrix) 210 corresponding to information word bits, and a parity submatrix 220 corresponding to parity bits.

The information word submatrix 210 includes K ldpc number of columns and the parity submatrix 220 includes N parity =N ldpc −K ldpc number of columns. The number of rows of the parity check matrix 200 is identical to the number of columns of the parity submatrix 220 , N parity =N ldpc −K ldpc .

In addition, in the parity check matrix 200 , N ldpc is a length of an LDPC codeword, K ldpc is a length of information word bits, and N parity =N ldpc −K ldpc is a length of parity bits. The length of the LDPC codeword, the information word bits, and the parity bits mean the number of bits included in each of the LDPC codeword, the information word bits, and the parity bits.

Hereinafter, the configuration of the information word submatrix 210 and the parity submatrix 220 will be explained in detail.

The information word submatrix 210 includes K ldpc number of columns (that is, 0 th column to (K ldpc −1) th column), and follows the following rules:

First, M number of columns from among K ldpc number of columns of the information word submatrix 210 belong to the same group, and K ldpc number of columns is divided into K ldpc /M number of column groups. In each column group, a column is cyclic-shifted from an immediately previous column by Q ldpc . That is, Q ldpc may be a cyclic shift parameter value regarding columns in a column group of the information word submatrix 210 of the parity check matrix 200 .

Herein, M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210 (e.g., M=360), and Q ldpc is a size by which one column is cyclic-shifted from an immediately previous column in a same column group in the information word submatrix 210 . Also, M is a common divisor of N ldpc and K ldpc and is determined to satisfy Q ldpc =(N ldpc −K ldpc )/M. Here, M and Q ldpc are integers and K ldpc /M is also an integer. M and Q ldpc may have various values according to a length of the LDPC codeword and a code rate (CR)(or, coding rate).

For example, when M=360 and the length of the LDPC codeword, N ldpc , is 64800, Q ldpc may be defined as in table 1 presented below, and, when M=360 and the length N ldpc of the LDPC codeword is 16200, Q ldpc may be defined as in table 2 presented below.

Second, when the degree of the 0 th column of the i th column group (i=0, 1, . . . , K ldpc /M−1) is D i (herein, the degree is the number of value 1 existing in each column and all columns belonging to the same column group have the same degree), and a position (or an index) of each row where 1 exists in the 0 th column of the i th column group is R i,0 (0) , R i,0 (1) , . . . , R i,0 (D i −1) , an index R i,j (k) of a row where k th 1 is located in the j th column in the i th column group is determined by following Equation 1:

R i,j (k) =R i,(j-1) (k) +Q ldpc mod( N ldpc −K ldpc )  (1),

where k=0, 1, 2, . . . D i −1; i=0, 1, . . . , K ldpc /M−1; and j=1, 2, . . . , M−1.

Equation 1 can be expressed as following Equation 2:

R i,j (k) ={R i,(j-1) (k) +Q ldpc }mod( N ldpc −K ldpc )  (2),

where k=0, 1, 2, . . . D i −1; i=0, 1, . . . , K ldpc /M−1; and j=1, 2, . . . , M−1. Since j=1, 2, . . . , M−1, (j mod M) of Equation 2 may be regarded as j.

In the above equations, R i,j (k) is an index of a row where k th 1 is located in the j th column in the i th column group, N ldpc is a length of an LDPC codeword, K ldpc is a length of information word bits, D i is a degree of columns belonging to the i th column group, M is the number of columns belonging to a single column group, and Q ldpc is a size by which each column in the column group is cyclic-shifted.

As a result, referring to these equations, when only R i,0 (k) is known, the index R i,j (k) of the row where the k th 1 is located in the j th column in the i th column group can be known. Therefore, when the index value of the row where the k th 1 is located in the 0 th column of each column group is stored, a position of column and row where 1 is located in the parity check matrix 200 having the configuration of FIG. 2 (that is, in the information word submatrix 210 of the parity check matrix 200 ) can be known.

According to the above-described rules, all of the columns belonging to the i th column group have the same degree D i . Accordingly, the LDPC codeword which stores information on the parity check matrix according to the above-described rules may be briefly expressed as follows.

For example, when N ldpc is 30, K ldpc is 15, and Q ldpc is 3, position information of the row where 1 is located in the 0 th column of the three column groups may be expressed by a sequence of Equations 3 and may be referred to as “weight-1 position sequence”.

R 1,0 (1) =1, R 1,0 (2) =2, R 1,0 (3) =8, R 1,0 (4) =10,

R 2,0 (1) =0, R 2,0 (2) =9, R 2,0 (3) =13,

R 3,0 (1) =0, R 3,0 (2) =14  (3),

where R i,j (k) is an index of a row where k th 1 is located in the j th column in the i th column group.

The weight-1 position sequence like Equation 3 which expresses an index of a row where 1 is located in the 0 th column of each column group may be briefly expressed as in Table 3 presented below:

Table 3 shows positions of elements having value 1 in the parity check matrix, and the i th weight-1 position sequence is expressed by indexes of rows where 1 is located in the 0 th column belonging to the i th column group.

The information word submatrix 210 of the parity check matrix according to an exemplary embodiment may be defined as in Tables 4 to 8 presented below, based on the above descriptions.

Specifically, Tables 4 to 8 show indexes of rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 . That is, the information word submatrix 210 is formed of a plurality of column groups each including M number of columns, and positions of 1 in the 0 th column of each of the plurality of column groups may be defined by Tables 4 to 8.

Herein, the indexes of the rows where 1 is located in the 0 th column of the i th column group mean “addresses of parity bit accumulators”. The “addresses of parity bit accumulators” have the same meaning as defined in the DVB-C2/S2/T2 standards or the ATSC 3.0 standards which are currently being established, and thus, a detailed explanation thereof is omitted.

For example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 4 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 8/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 5 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 6 below.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 7 below.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 8 below.

In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the position of 1 in the information word submatrix 210 may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.

According to an exemplary embodiment, even when the order of numbers in a sequence corresponding to the i th column group of the parity check matrix 200 as shown in the above-described Tables 4 to 8 is changed, the changed parity check matrix is a parity check matrix used for the same code. Therefore, a case in which the order of numbers in the sequence corresponding to the i th column group in Tables 4 to 8 is changed is covered by the inventive concept.

According to an exemplary embodiment, even when the arrangement order of sequences corresponding to each column group is changed in Tables 4 to 8, cycle characteristics on a graph of a code and algebraic characteristics such as degree distribution are not changed. Therefore, a case in which the arrangement order of the sequences shown in Tables 4 to 8 is changed is also covered by the inventive concept.

In addition, even when a multiple of Q ldpc is equally added to all sequences corresponding to a certain column group in Tables 4 to 8, the cycle characteristics on the graph of the code or the algebraic characteristics such as degree distribution are not changed. Therefore, a result of equally adding a multiple of Q ldpc to the sequences shown in Tables 4 to 8 is also covered by the inventive concept. However, it should be noted that, when the resulting value obtained by adding the multiple of Q ldpc to a given sequence is greater than or equal to (N ldpc −K ldpc ), a value obtained by applying a modulo operation for (N ldpc −K ldpc ) to the resulting value should be applied instead.

Once positions of the rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Tables 4 to 8, positions of rows where 1 exists in another column of each column group may be defined since the positions of the rows where 1 exists in the 0 th column are cyclic-shifted by Q ldpc in the next column.

For example, in the case of Table 4, in the 0 th column of the 0 th column group of the information word submatrix 210 , 1 exists in the 1606 th row, 3402 nd row, 4961 st row, . . . .

In this case, since Q ldpc =(N ldpc −K ldpc )/M=(64800−25920)/360=108, the indexes of the rows where 1 is located in the 1st column of the 0 th column group may be 1714(=1606+108), 3510(=3402+108), 5069(=4961+108), . . . , and the indexes of the rows where 1 is located in the 2 nd column of the 0 th column group may be 1822(=1714+108), 3618(=3510+108), 5177(=5069+108), . . . .

In the above-described method, the indexes of the rows where 1 is located in all rows of each column group may be defined.

The parity submatrix 220 of the parity check matrix 200 shown in FIG. 2 may be defined as follows:

The parity submatrix 220 includes N ldpc −K ldpc number of columns (that is, K ldpc th column to (N ldpc −1) th column), and has a dual diagonal or staircase configuration. Accordingly, the degree of columns except the last column (that is, (N ldpc −1) th column) from among the columns included in the parity submatrix 220 is 2, and the degree of the last column is 1.

As a result, the information word submatrix 210 of the parity check matrix 200 may be defined by Tables 4 to 8, and the parity submatrix 220 of the parity check matrix 200 may have a dual diagonal configuration.

When the columns and rows of the parity check matrix 200 shown in FIG. 2 are permutated based on Equation 4 and Equation 5, the parity check matrix shown in FIG. 2 may be changed to a parity check matrix 300 shown in FIG. 3 .

Q ldpc ·i+j⇒M·j+i (0≤ i<M, 0≤ j<Q ldpc )  (4)

K ldpc +Q ldpc ·k+l⇒K ldpc +M·l+k (0≤ k<M, 0≤ l<Q ldpc )  (5)

The method for permutating based on Equation 4 and Equation 5 will be explained below. Since row permutation and column permutation apply the same principle, the row permutation will be explained by the way of an example.

In the case of the row permutation, regarding the X th row, i and j satisfying X=Q ldpc ×i+j are calculated and the X th row is permutated by assigning the calculated i and j to M×j+i. For example, regarding the 7 th row, i and j satisfying 7=2×i+j are 3 and 1, respectively. Therefore, the 7 th row is permutated to the 13 th row (10×1+3=13).

When the row permutation and the column permutation are performed in the above-described method, the parity check matrix of FIG. 2 may be converted into the parity check matrix of FIG. 3 .

Referring to FIG. 3 , the parity check matrix 300 is divided into a plurality of partial blocks, and a quasi-cyclic matrix of M×M corresponds to each partial block.

Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of matrix units of M×M. That is, the submatrices of M×M are arranged in the plurality of partial blocks, constituting the parity check matrix 300 .

Since the parity check matrix 300 is formed of the quasi-cyclic matrices of M×M, M number of columns may be referred to as a column block and M number of rows may be referred to as a row block. Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of N qc_column =N ldpc /M number of column blocks and N qc_row =N parity /M number of row blocks.

Hereinafter, the submatrix of M×M will be explained.

First, the (N qc_column −1) th column block of the 0 th row block has a form shown in Equation 6 presented below:

As described above, A 330 is an M×M matrix, values of the 0 th row and the (M−1) th column are all “0”, and, regarding 0≤i≤(M−2), the (i+1) th row of the i th column is “1” and the other values are “0”.

Second, regarding 0≤i≤(N ldpc −K ldpc )/M−1 in the parity submatrix 320 , the row block of the (K ldpc /M+i) th column block is configured by a unit matrix I M×M 340 . In addition, regarding 0≤i≤(N ldpc −K ldpc )/M−2, the (i+1) th row block of the (K ldpc /M+i) th column block is configured by a unit matrix I M×M 340 .

Third, a block 350 constituting the information word submatrix 310 may have a cyclic-shifted format of a cyclic matrix P, P α ij , or an added format of the cyclic-shifted matrix P α ij of the cyclic matrix P (or an overlapping format).

For example, a format in which the cyclic matrix P is cyclic-shifted to the right by 1 may be expressed by Equation 7 presented below:

The cyclic matrix P is a square matrix having an M×M size and is a matrix in which a weight of each of M number of rows is 1 and a weight of each of M number of columns is 1. When a ij is 0, the cyclic matrix P, that is, P 0 indicates a unit matrix I M×M , and when a ij is ∞, P ∞ is a zero matrix.

A submatrix existing where the i th row block and the j th column block intersect in the parity check matrix 300 of FIG. 3 may be P α ij . Accordingly, i and j indicate the number of row blocks and the number of column blocks in the partial blocks corresponding to the information word. Accordingly, in the parity check matrix 300 , the total number of columns is N ldpc =M×N qc_column , and the total number of rows is N parity =M×N qc_row . That is, the parity check matrix 300 is formed of N qc_column number of “column blocks” and N qc_row number of “row blocks”.

Hereinafter, a method for performing LDPC encoding based on the parity check matrix 200 as shown in FIG. 2 will be explained. An LDPC encoding process when the parity check matrix 200 is defined as shown in Table 4 by way of an example will be explained for the convenience of explanation.

First, when information word bits having a length of K ldpc are [i 0 , i 1 , i 2 , . . . , i K ldpc −1 ], and parity bits having a length of N ldpc −K ldpc are [p 0 , p 1 , p 2 , . . . p N ldpc −K ldpc −1 ], the LDPC encoding is performed by the following process.

Step 1) Parity bits are initialized as ‘0’. That is, p 0 =p 1 =p 2 = . . . =p N ldpc −K ldpc −1 =0.

Step 2) The 0 th information word bit i 0 is accumulated in a parity bit having the address of the parity bit defined in the first row (that is, the row of i=0) of table 4 as the index of the parity bit. This may be expressed by Equation 8 presented below:

Herein, i 0 is a 0 th information word bit, p i is an i th parity bit, and ⊕ is a binary operation. According to the binary operation, 1⊕1 equals 0, 1⊕0 equals 1, 0⊕1 equals 1, 0⊕0 equals 0.

Step 3) The other 359 information word bits i m (m=1, 2, . . . , 359) are accumulated in the parity bit. The other information word bits may belong to the same column group as that of i 0 . In this case, the address of the parity bit may be determined based on Equation 9 presented below:

( x +( m mod 360)× Q ldpc )mod( N ldpc −K ldpc )  (9)

Herein, x is an address of a parity bit accumulator corresponding to the information word bit i 0 , and Q ldpc is a size by which each column is cyclic-shifted in the information word submatrix, and may be 108 in the case of table 4. In addition, since m=1, 2, . . . , 359, (m mod 360) in Equation 9 may be regarded as m.

As a result, information word bits i m (m=1, 2, . . . , 359) are accumulated in the parity bits having the address of the parity bit calculated based on Equation 9 as the index. For example, an operation as shown in Equation 10 presented below may be performed for the information word bit

Herein, i 1 is a 1 st information word bit, p i is an i th parity bit, and ⊕ is a binary operation. According to the binary operation, 1δ1 equals 0, 1δ0 equals 1, 0δ1 equals 1, 0δ0 equals 0.

Step 4) The 360 th information word bits i 360 is accumulated in a parity bit having the address of the parity bit defined in the 2 nd row (that is, the row of i=1) of table 4 as the index of the parity bit.

Step 5) The other 359 information word bits belonging to the same group as that of the information word bit i 360 are accumulated in the parity bit. In this case, the address of the parity bit may be determined based on Equation 9. However, in this case, x is the address of the parity bit accumulator corresponding to the information word bit i 360 .

Step 6) Steps 4 and 5 described above are repeated for all of the column groups of table 4.

Step 7) As a result, a parity bit p i is calculated based on Equation 11 presented below. In this case, i is initialized as 1.

p i =p i ⊕p i-1 i= 1,2, . . . , N ldpc −K ldpc −1  (11)

In Equation 11, p i is an i th parity bit, N ldpc is a length of an LDPC codeword, K ldpc is a length of an information word of the LDPC codeword, and ⊕ is a binary operation.

As a result, the encoder 110 may calculate the parity bits according to the above-described method.

In another example, a parity check matrix according to an exemplary embodiment may have a configuration as shown in FIG. 4 .

Referring to FIG. 4 , the parity check matrix 400 may be formed of 5 matrices A, B, C, Z, and D. Hereinafter, the configuration of each matrix will be explained to explain the configuration of the parity check matrix 400 .

First, M 1 , M 2 , Q 1 , and Q 2 , which are parameter values related to the parity check matrix 400 as shown in FIG. 4 , may be defined as shown in table 9 presented below according to the length and the code rate of the LDPC codeword.

The matrix A is formed of K number of columns and g number of rows, and the matrix C is formed of K+g number of columns and N−K-g number of rows. Herein, K is a length of information word bits, and N is a length of the LDPC codeword.

Indexes of rows where 1 is located in the 0 th column of the i th column group in the matrix A and the matrix C may be defined based on table 10 according to the length and the code rate of the LDPC codeword. In this case, an interval at which a pattern of a column is repeated in each of the matrix A and the matrix C, that is, the number of columns belonging to the same group, may be 360.

For example, when the length N of the LDPC codeword is 64800 and the code rate is 6/15, the indexes of rows where 1 is located in the 0 th column of the i th column group in the matrix A and the matrix C are defined as shown in table 10 presented below:

In the above-described example, the length of the LDPC codeword is 64800 and the code rate 6/15. However, this is merely an example and the indexes of rows where 1 is located in the 0 th column of the i th column group in the matrix A and the matrix C may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.

Hereinafter, positions of rows where 1 exists in the matrix A and the matrix C will be explained with reference to table 10 by way of an example.

Since the length N of the LDPC codeword is 64800 and the code rate is 6/15 in table 10, M 1 =1080, M 2 =37800, Q 1 =3, and Q 2 =105 in the parity check matrix 400 defined by table 10 with reference to table 9.

Herein, Q 1 is a size by which columns of the same column group are cyclic-shifted in the matrix A, and Q 2 is a size by which columns of the same column group are cyclic-shifted in the matrix C.

In addition, Q 1 =M 1 /L, Q 2 =M 2 /L, M 1 =g, and M 2 =N−K−g, and L is an interval at which a pattern of a column is repeated in the matrix A and the matrix C, and for example, may be 360.

The index of the row where 1 is located in the matrix A and the matrix C may be determined based on the M 1 value.

For example, since M 1 =1080 in the case of table 10, the positions of the rows where 1 exists in the 0 th column of the i th column group in the matrix A may be determined based on values smaller than 1080 from among the index values of table 10, and the positions of the rows where 1 exists in the 0 th column of the i th column group in the matrix C may be determined based on values greater than or equal to 1080 from among the index values of table 10.

Specifically, in table 10, the sequence corresponding to the 0 th column group is “71, 276, 856, 6867, 12964, 17373, 18159, 26420, 28460, 28477”. Accordingly, in the case of the 0 th column of the 0 th column group of the matrix A, 1 may be located in the 71 st row, 276th row, and 856 th row, and, in the case of the 0 th column of the 0 th column group of the matrix C, 1 may be located in the 6867 th row, 12964 th row, 17373 rd row, 18159 th row, 26420 th row, 28460 th row, and 28477 th row.

Once positions of 1 in the 0 th column of each column group of the matrix A are defined, positions of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Q 1 . Once positions of 1 in the 0 th column of each column group of the matrix C are defined, position of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Q 2 .

In the above-described example, in the case of the 0 th column of the 0 th column group of the matrix A, 1 exists in the 71 st row, 276 th row, and 856 th row. In this case, since Q 1 =3, the indexes of rows where 1 exists in the 1st column of the 0 th column group are 74(=71+3), 279(=276+3), and 859(=856+3), and the index of rows where 1 exists in the 2 nd column of the 0 th column group are 77(=74+3), 282 (=279+3), and 862(=859+3).

In the case of the 0 th column of the 0 th column group of the matrix C, 1 exists in the 6867 th row, 12964 th row, 17373 rd row, 18159 th row, 26420 th row, 28460 th row, and 28477th row. In this case, since Q 2 =105, the index of rows where 1 exists in the 1st column of the 0 th column group are 6972(=6867+105), 13069(=12964+105), 17478(=17373+105), 18264(=18159+105), 26525(=26420+105), 28565(=28460+105), 28582(=28477+105), and the indexes of rows where 1 exists in the 2 nd column of the 0 th column group are 7077(=6972+105), 13174(=13069+105), 17583(=17478+105), 18369(=18264+105), 26630(=26525+105), 28670(=28565+105), 28687(=28582+105).

In this method, the positions of rows where 1 exists in all column groups of the matrix A and the matrix C are defined.

The matrix B may have a dual diagonal configuration, the matrix D may have a diagonal configuration (that is, the matrix D is an identity matrix), and the matrix Z may be a zero matrix.

As a result, the parity check matrix 400 shown in FIG. 4 may be defined by the matrices A, B, C, D, and Z having the above-described configurations.

Hereinafter, a method for performing LDPC encoding based on the parity check matrix 400 shown in FIG. 4 will be explained. An LDPC encoding process when the parity check matrix 400 is defined as shown in Table 10 by way of an example will be explained for the convenience of explanation.

For example, when an information word block S=(s 0 , s 1 , . . . , s K−1 ) is LDPC-encoded, an LDPC codeword Λ=(λ 0 , λ 1 , . . . , λ N−1 )=(s 0 , s 1 , . . . , S K−1 , p 0 , p 1 , . . . , P M 1 +M 2 −1 ) including a parity bit P=(p 0 , p 1 , . . . , P M 1 +M 2 −1 ) may be generated.

M 1 and M 2 indicate the size of the matrix B having the dual diagonal configuration and the size of the matrix C having the diagonal configuration, respectively, and M 1 =g, M 2 =N−K−g.

A process of calculating a parity bit is as follows. In the following explanation, the parity check matrix 400 is defined as shown in table 10 by way of an example, for the convenience of explanation.

Step 1) λ and p are initialized as λ i =s i (i=0, 1, . . . , K−1), p j =0 (j=0, 1, . . . , M 1 +M 2 −1).

Step 2) The 0 th information word bit λ 0 is accumulated in the address of the parity bit defined in the first row (that is, the row of i=0) of table 10. This may be expressed by Equation 12 presented below:

Step 3) Regarding the next L−1 number of information word bits λ m (m=1, 2, . . . , L−1), λ m is accumulated in the parity bit address calculated based on Equation 13 presented below:

(χ+ m×Q 1 )mod M 1 (if χ< M 1 )

M 1 +{(χ× M 1 +m×Q 2 )mod M 2 }(if χ≤ M 1 )  (13)

Herein, x is an address of a parity bit accumulator corresponding to the 0 th information word bit λ 0 .

In addition, Q 1 =M 1 /L and Q 2 =M 2 /L. In addition, since the length N of the LDPC codeword is 64800 and the code rate is 6/15 in table 10, M 1 =1080, M 2 =37800, Q 1 =3, Q 2 =105, and L=360 with reference to table 9.

Accordingly, an operation as shown in Equation 14 presented below may be performed for the 1st information word bit λ 1 :

Step 4) Since the same address of the parity bit as in the second row (that is the row of i=1) of table 10 is given to the Lth information word bit λ L , in a similar method to the above-described method, the address of the parity bit regarding the next L−1 number of information word bits λ m (m=L+1, L+2, 2L−1) is calculated based on Equation 13. In this case, x is the address of the parity bit accumulator corresponding to the information word bit λ L , and may be obtained based on the second row of table 10.

Step 5) The above-described processes are repeated for L number of new information word bits of each group by considering new rows of table 10 as the address of the parity bit accumulator.

Step 6) After the above-described processes are repeated for the codeword bits λ 0 to λ K−1 , values regarding Equation 15 presented below are calculated in sequence from i=1:

P i =P i ⊕P i-1 ( i= 1,2, . . . , M 1 −1)  (15)

Step 7) Parity bits λ K to λ K+M 1 −1 corresponding to the matrix B having the dual diagonal configuration are calculated based on Equation 16 presented below:

λ K+L×t+s =P Q 1 ×S+t (0≤ s<L, 0≤ t<Q 1 )  (16)

Step 8) The address of the parity bit accumulator regarding L number of new codeword bits λ K to λ K+M 1 −1 of each group is calculated based on table 10 and Equation 13.

Step 9) After the codeword bits λ K to λ K+M 1 −1 are calculated, parity bits λ K+M 1 to λ K+M 1 +M 2 −1 corresponding to the matrix C having the diagonal configuration are calculated based on Equation 17 presented below:

λ K+M 1 +L×t+s =p M 1 +Q 2 ×S+t (0≤ s<L, 0 t≤Q 2 )  (17)

As a result, the parity bits may be calculated in the above-described method.

Referring back to FIG. 1 , the encoder 110 may perform the LDPC encoding by using various code rates such as 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. In addition, the encoder 110 may generate an LDPC codeword having various lengths such as 16200, 64800, etc., based on the length of the information word bits and the code rate.

In this case, the encoder 110 may perform the LDPC encoding by using the parity check matrix, and the parity check matrix is configured as shown in FIGS. 2 to 4 .

In addition, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH) encoding as well as LDPC encoding. To achieve this, the encoder 110 may further include a BCH encoder (not shown) to perform BCH encoding.

In this case, the encoder 110 may perform encoding in an order of BCH encoding and LDPC encoding. Specifically, the encoder 110 may add BCH parity bits to input bits by performing BCH encoding and LDPC-encodes the information word bits including the input bits and the BCH parity bits, thereby generating the LDPC codeword.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoder 110 , and interleaves the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 may interleave the LDPC codeword such that a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword (that is, a plurality of groups or a plurality of blocks) is mapped onto a predetermined bit of a modulation symbol. Accordingly, the modulator 130 may map a bit included in a predetermined group from among the plurality of groups of the LDPC codeword onto a predetermined bit of the modulation symbol.

To achieve this, as shown in FIG. 5 , the interleaver 120 may include a parity interleaver 121 , a group interleaver (or a group-wise interleaver 122 ), a group twist interleaver 123 and a block interleaver 124 .

The parity interleaver 121 interleaves the parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the configuration of FIG. 2 , the parity interleaver 121 may interleave only the parity bits of the LDPC codeword by using Equations 18 presented below:

u i =c i for 0≤ i≤K ldpc , and

u K ldpc +M·t+s =c K ldpc +Q ldpc ·s+t for 0≤ s≤M, 0≤ t≤Q ldpc   (18),

where M is an interval at which a pattern of a column group is repeated in the information word submatrix 210 , that is, the number of columns included in a column group (for example, M=360), and Q ldpc is a size by which each column is cyclic-shifted in the information word submatrix 210 . That is, the parity interleaver 121 performs parity interleaving with respect to the LDPC codeword c=(c 0 , c 1 , . . . c N ldpc −1 ), and outputs U=(u 0 , u 1 , . . . , u N ldpc −1 ).

The LDPC codeword parity-interleaved in the above-described method may be configured such that a predetermined number of continuous bits of the LDPC codeword have similar decoding characteristics (cycle distribution, a degree of a column, etc.).

For example, the LDPC codeword may have the same characteristics on the basis of M number of continuous bits. Herein, M is an interval at which a pattern of a column group is repeated in the information word submatrix 210 and, for example, may be 360.

Specifically, a product of the LDPC codeword bits and the parity check matrix should be “0”. This means that a sum of products of the i th LDPC codeword bit, c i (i=0, 1, . . . , N ldpc −1) and the column of the parity check matrix should be a “0” vector. Accordingly, the LDPC codeword bit may be regarded as corresponding to the i th column of the parity check matrix.

In the case of the parity check matrix 200 of FIG. 2 , M number of columns in the information word submatrix 210 belong to the same group and the information word submatrix 210 has the same characteristics on the basis of a column group (for example, the columns belonging to the same column group have the same degree distribution and the same cycle characteristic).

In this case, since M number of continuous bits in the information word bits correspond to the same column group of the information word submatrix 210 , the information word bits may be formed of M number of continuous bits having the same codeword characteristics. When the parity bits of the LDPC codeword are interleaved by the parity interleaver 121 , the parity bits of the LDPC codeword may be formed of M number of continuous bits having the same codeword characteristics.

However, regarding the LDPC codeword encoded based on the parity check matrix 300 of FIG. 3 and the parity check matrix 400 of FIG. 4 , parity interleaving may not be performed. In this case, the parity interleaver 121 may be omitted.

The group interleaver 122 may divide the parity-interleaved LDPC codeword into a plurality of bit groups and rearrange the order of the plurality of bit groups in bit group wise (or bit group unit). That is, the group interleaver 122 may interleave the plurality of bit groups in bit group wise.

To achieve this, the group interleaver 122 divides the parity-interleaved LDPC codeword into a plurality of bit groups by using Equation 19 or Equation 20 presented below.

X j = { u k | j = ⌊ k 360 ⌋ , 0 ≤ k ≤ N ldpc } ⁢ for ⁢ 0 ≤ j < N group ( 19 ) X j = { u k | 360 × j ≤ k < 360 × ( j + 1 ) , 0 ≤ k < N ldpc } ⁢ for ( 20 ) 0 ≤ j < N group

where N group is the total number of bit groups, N is the j th bit group, and u k is the k th LDPC codeword bit input to the group interleaver 122 . In addition,

⌊ k 360 ⌋

is the largest integer below k/360.

Since 360 in these equations indicates an example of the interval M at which the pattern of a column group is repeated in the information word submatrix, 360 in these equations can be changed to M.

The LDPC codeword which is divided into the plurality of bit groups may be as shown in FIG. 6 .

Referring to FIG. 6 , the LDPC codeword is divided into the plurality of bit groups and each bit group is formed of M number of continuous bits. When M is 360, each of the plurality of bit groups may be formed of 360 bits. Accordingly, the bit groups may be formed of bits corresponding to the column groups of the parity check matrix.

Specifically, since the LDPC codeword is divided by M number of continuous bits, K ldpc number of information word bits are divided into (K ldpc /M) number of bit groups and N ldpc −K ldpc number of parity bits are divided into (N ldpc −K ldpc )/M number of bit groups. Accordingly, the LDPC codeword may be divided into (N ldpc /M) number of bit groups in total.

For example, when M=360 and the length N ldpc of the LDPC codeword is 16200, the number of groups N groups constituting the LDPC codeword is 45(=16200/360), and, when M=360 and the length N ldpc of the LDPC codeword is 64800, the number of bit groups N group constituting the LDPC codeword is 180(=64800/360).

As described above, the group interleaver 122 divides the LDPC codeword such that M number of continuous bits are included in a same group since the LDPC codeword has the same codeword characteristics on the basis of M number of continuous bits. Accordingly, when the LDPC codeword is grouped by M number of continuous bits, the bits having the same codeword characteristics belong to the same group.

In the above-described example, the number of bits constituting each bit group is M. However, this is merely an example and the number of bits constituting each bit group is variable.

For example, the number of bits constituting each bit group may be an aliquot part of M. That is, the number of bits constituting each bit group may be an aliquot part of the number of columns constituting a column group of the information word submatrix of the parity check matrix. In this case, each bit group may be formed of aliquot part of M number of bits. For example, when the number of columns constituting a column group of the information word submatrix is 360, that is, M=360, the group interleaver 122 may divide the LDPC codeword into a plurality of bit groups such that the number of bits constituting each bit group is one of the aliquot parts of 360.

In the following explanation, the number of bits constituting a bit group is M by way of an example, for the convenience of explanation.

Thereafter, the group interleaver 122 interleaves the LDPC codeword in bit group wise. Specifically, the group interleaver 122 may group the LDPC codeword into the plurality of bit groups and rearrange the plurality of bit groups in bit group wise. That is, the group interleaver 122 changes positions of the plurality of bit groups constituting the LDPC codeword and rearranges the order of the plurality of bit groups constituting the LDPC codeword in bit group wise.

Herein, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise such that bit groups including bits mapped onto the same modulation symbol from among the plurality of bit groups are spaced apart from one another at predetermined intervals.

In this case, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by considering at least one of the number of rows and columns of the block interleaver 124 , the number of bit groups of the LDPC codeword, and the number of bits included in each bit group, such that bit groups including bits mapped onto the same modulation symbol are spaced apart from one another at predetermined intervals.

To achieve this, the group interleaver 122 may rearrange the order of the plurality of groups in bit group wise by using Equation 21 presented below:

Y j =X π(j) (0≤ j<N group )  (21),

where X j is the j th bit group before group interleaving, and Y j is the j th bit group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a modulation method, and a code rate. That is, π(j) denotes a permutation order for group wise interleaving.

Accordingly, X π(j) is a π(j) th bit group before group interleaving, and Equation 21 means that the pre-interleaving π(j) th bit group is interleaved into the j th bit group.

According to an exemplary embodiment, an example of π(j) may be defined as in Tables 11 to 22 presented below.

In this case, π(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in bit group wise based on π(j) satisfying the corresponding length of the LDPC codeword and code rate.

For example, when the encoder 110 performs LDPC encoding at a code rate of 6/15 to generate an LDPC codeword of a length of 64800, the group interleaver 122 may perform interleaving by using π(j) which is defined according to the length of the LDPC codeword of 16200 and the code rate of 6/15 in tables 11 to 22 presented below.

For example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method(or modulation format) is 16-Quadrature Amplitude Modulation (QAM), π(j) may be defined as in table 11 presented below. In particular, table 11 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 4.

In the case of Table 11, Equation 21 may be expressed as Y 0 =X π(0) =X 55 , Y 1 =X π(1) =X 146 , Y 2 =X π(2) =X 83 , . . . , Y 178 =X π(178) =X 132 , and Y 179 =X π(179) =X 135 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 55 th bit group to the 0 th bit group, the 146 th bit group to the 1 st bit group, the 83 rd bit group to the 2 nd bit group, . . . , the 132 nd bit group to the 178 th bit group, and the 135 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 16-QAM, π(j) may be defined as in table 12 presented below. In particular, table 12 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 5.

In the case of Table 12, Equation 21 may be expressed as Y 0 =X π(0) =X 58 , Y 1 =X π(1) =X 55 , Y 2 =X π(2) =X 111 , . . . , Y 178 =X π(178) =X 171 , and Y 179 =X π(179) =X 155 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 58 th bit group to the 0 th bit group, the 55 th bit group to the 1 st bit group, the 111 th bit group to the 2 nd bit group, . . . , the 171 st bit group to the 178 th bit group, and the 155 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, π(j) may be defined as in table 13 presented below. In particular, table 13 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 6.

In the case of Table 13, Equation 21 may be expressed as Y 0 =X π(0) =X 74 , Y 1 =X π(1) =X 53 , Y 2 =X π(2) =X 84 , Y 178 =X π(178) =X 159 , and Y 179 = π(179) =X 163 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 74 th bit group to the 0 th bit group, the 53 rd bit group to the 1 st bit group, the 84 th bit group to the 2 nd bit group, . . . , the 159 th bit group to the 178 th bit group, and the 163 rd bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, π(j) may be defined as in table 14 presented below. In particular, table 14 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 7.

In the case of Table 14, Equation 21 may be expressed as Y 0 =X π(0) =X 68 , Y 1 =X π(1) =X 71 , Y 2 =X π(2) =X 54 , Y 178 =X π(178) =X 135 , and Y 179 =X π(179) =X 24 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 68 th bit group to the 0 th bit group, the 71 st bit group to the 1 st bit group, the 54 th bit group to the 2 nd bit group, . . . , the 135 th bit group to the 178 th bit group, and the 24 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 16-QAM, π(j) may be defined as in table 15 presented below. In particular, table 15 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 8.

In the case of Table 15, Equation 21 may be expressed as Y 0 =X π(0) =X 120 , Y 1 =X π(1) =X 32 , Y 2 =X π(2) =X 38 , Y 178 =X π(178) =X 101 , and Y 179 =X π(l79) =X 39 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 120 th bit group to the 0 th bit group, the 32 nd bit group to the 1 st bit group, the 38 th bit group to the 2 nd bit group, . . . , the 101 st bit group to the 178 th bit group, and the 39 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 16-QAM, π(j) may be defined as in table 16 presented below. In particular, table 16 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 10.

In the case of Table 16, Equation 21 may be expressed as Y 0 =X π(0) =X 163 , Y 1 =X π(1) =X 160 , Y 2 =X π(2) =X 138 , . . . , Y 178 =X π(178) =X 148 , and Y 179 =X π(l79) =X 98 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 163 rd bit group to the 0 th bit group, the 160 th bit group to the 1 st bit group, the 138th bit group to the 2 nd bit group, . . . , the 148 th bit group to the 178 th bit group, and the 98 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 64-QAM, π(j) may be defined as in table 17 presented below. In particular, table 17 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 4.

In the case of Table 17, Equation 21 may be expressed as Y 0 =X π(0) =X 29 , Y 1 =X π(1) =X 17 , Y 2 =X π(2) =X 38 , . . . , Y 178 =X π(178) =X 117 , and Y 179 =X π(179) =X 155 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 29 th bit group to the 0 th bit group, the 17 th bit group to the 1 st bit group, the 38 th bit group to the 2 nd bit group, . . . , the 117 th bit group to the 178 th bit group, and the 155 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 64-QAM, π(j) may be defined as in table 18 presented below. In particular, table 18 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 5.

In the case of Table 18, Equation 21 may be expressed as Y 0 =X π(0) =X 86 , Y 1 =X π(1) =X 71 , Y 2 =X π(2) =X 51 , . . . , Y 178 =X π(178) =X 174 , and Y 179 =X π(l79) =X 128 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 86 th bit group to the 0 th bit group, the 71 st bit group to the 1 st bit group, the 51 st bit group to the 2 nd bit group, . . . , the 174 th bit group to the 178 th bit group, and the 128 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, π(j) may be defined as in table 19 presented below. In particular, table 19 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 6.

In the case of Table 19, Equation 21 may be expressed as Y 0 =X π(0) =X 73 , Y 1 =X π(1) =X 36 , Y 2 =X π(2) =X 21 , . . . , Y 178 =X π(178) =X 149 , and Y 179 =X π(179) =X 135 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 73 rd bit group to the 0 th bit group, the 36 th bit group to the 1 st bit group, the 21 st bit group to the 2 nd bit group, . . . , the 149 th bit group to the 178 th bit group, and the 135 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, π(j) may be defined as in table 20 presented below. In particular, table 20 may be applied when LDPC encoding is performed ‘based on the parity check matrix defined by table 7.

In the case of Table 20, Equation 21 may be expressed as Y 0 =X π(0) =X 113 , Y 1 =X π(1) =X 115 , Y 2 =X π(2) =X 47 , . . . , Y 178 =X π(178) =X 130 , and Y 179 =X π(l79) =X 176 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 113 th bit group to the 0 th bit group, the 115 th bit group to the 1 st bit group, the 47th bit group to the 2 nd bit group, . . . , the 130 th bit group to the 178 th bit group, and the 176 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 64-QAM, π(j) may be defined as in table 21 presented below. In particular, table 21 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 8.

In the case of Table 21, Equation 21 may be expressed as Y 0 =X π(0) =X 83 , Y 1 =X π(1) =X 93 , Y 2 =X π(2) =X 94 , . . . , Y 178 =X π(178) =X 2 , and Y 179 =X π(179) =X 14 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 83 rd bit group to the 0 th bit group, the 93 rd bit group to the 1 st bit group, the 94 th bit group to the 2 nd bit group, . . . , the 2 nd bit group to the 178 th bit group, and the 14 th bit group to the 179 th bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 64-QAM, π(j) may be defined as in table 22 presented below. In particular, table 22 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 10.

In the case of Table 22, Equation 21 may be expressed as Y 0 =X π(0) =X 175 , Y 1 =X π(1) =X 177 , Y 2 =X π(2) =X 173 , . . . , Y 178 =X π(178) =X 31 , and Y 179 =X π(l79) =X 72 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 175 th bit group to the 0 th bit group, the 177 th bit group to the 1 st bit group, the 173 rd bit group to the 2 nd bit group, . . . , the 31 st bit group to the 178 th bit group, and the 72 nd bit group to the 179 th bit group.

In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the interleaving pattern may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.

As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by using Equation 21 and Tables 11 to 22.

“j-th block of Group-wise Interleaver output” in tables 11 to 22 indicates the j-th bit group output from the group interleaver 122 after interleaving, and “π(j)-th block of Group-wise Interleaver input” indicates the π(j)-th bit group input to the group interleaver 122 .

In addition, since the order of the bit groups constituting the LDPC codeword is rearranged by the group interleaver 122 in bit group wise, and then the bit groups are block-interleaved by the block interleaver 124 , which will be described below, “Order of bit groups to be block interleaved” is set forth in Tables 11 to 22 in relation to π(j).

The LDPC codeword which is group-interleaved in the above-described method is illustrated in FIG. 7 . Comparing the LDPC codeword of FIG. 7 and the LDPC codeword of FIG. 6 before group interleaving, it can be seen that the order of the plurality of bit groups constituting the LDPC codeword is rearranged.

That is, as shown in FIGS. 6 and 7 , the groups of the LDPC codeword are arranged in order of bit group X 0 , bit group X 1 , . . . , bit group X Ngroup-1 before being group-interleaved, and are arranged in an order of bit group Y 0 , bit group Y 1 , . . . , bit group Y Ngroup-1 after being group-interleaved. In this case, the order of arranging the bit groups by the group interleaving may be determined based on Tables 11 to 22.

The group twist interleaver 123 interleaves bits in a same group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by changing the order of the bits in the same bit group.

In this case, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by cyclic-shifting a predetermined number of bits from among the bits in the same bit group.

For example, as shown in FIG. 8 , the group twist interleaver 123 may cyclic-shift bits included in the bit group Y 1 to the right by 1 bit. In this case, the bits located in the 0 th position, the 1 st position, the 2 nd position, . . . , the 358 th position, and the 359 th position in the bit group Y 1 as shown in FIG. 8 are cyclic-shifted to the right by 1 bit. As a result, the bit located in the 359 th position before being cyclic-shifted is located in the front of the bit group Y 1 and the bits located in the 0 th position, the 1 st position, the 2 nd position, . . . , the 358 th position before being cyclic-shifted are shifted to the right serially by 1 bit and located.

In addition, the group twist interleaver 123 may rearrange the order of bits in each bit group by cyclic-shifting a different number of bits in each bit group.

For example, the group twist interleaver 123 may cyclic-shift the bits included in the bit group Y 1 to the right by 1 bit, and may cyclic-shift the bits included in the bit group Y 2 to the right by 3 bits.

However, the above-described group twist interleaver 123 may be omitted according to circumstances.

In addition, the group twist interleaver 123 is placed after the group interleaver 122 in the above-described example. However, this is merely an example. That is, the group twist interleaver 123 changes only the order of bits in a certain bit group and does not change the order of the bit groups. Therefore, the group twist interleaver 123 may be placed before the group interleaver 122 .

The block interleaver 124 interleaves the plurality of bit groups the order of which has been rearranged. Specifically, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise (or bits group unit). The block interleaver 124 is formed of a plurality of columns each including a plurality of rows and may interleave by dividing the plurality of rearranged bit groups based on a modulation order determined according to a modulation method.

In this case, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise. Specifically, the block interleaver 124 may interleave by dividing the plurality of rearranged bit groups according to a modulation order by using a first part and a second part.

Specifically, the block interleaver 124 interleaves by dividing each of the plurality of columns into a first part and a second part, writing the plurality of bit groups in the plurality of columns of the first part serially in bit group wise, dividing the bits of the other bit groups into groups (or sub bit groups) each including a predetermined number of bits based on the number of columns, and writing the sub bit groups in the plurality of columns of the second part serially.

Herein, the number of bit groups which are interleaved in bit group wise may be determined by at least one of the number of rows and columns constituting the block interleaver 124 , the number of bit groups and the number of bits included in each bit group. In other words, the block interleaver 124 may determine the bit groups which are to be interleaved in bit group wise considering at least one of the number of rows and columns constituting the block interleaver 124 , the number of bit groups and the number of bits included in each bit group, interleave the corresponding bit groups in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. For example, the block interleaver 124 may interleave at least part of the plurality of bit groups in bit group wise using the first part, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups using the second part.

Meanwhile, interleaving bit groups in bit group wise means that the bits included in the same bit group are written in the same column. In other words, the block interleaver 124 , in case of bit groups which are interleaved in bit group wise, may not divide the bits included in the same bit groups and write the bits in the same column, and in case of bit groups which are not interleaved in bit group wise, may divide the bits in the bit groups and write the bits in different columns.

Accordingly, the number of rows constituting the first part is a multiple of the number of bits included in one bit group (for example, 360), and the number of rows constituting the second part may be less than the number of bits included in one bit group.

In addition, in all bit groups interleaved by the first part, the bits included in the same bit group are written and interleaved in the same column of the first part, and in at least one group interleaved by the second part, the bits are divided and written in at least two columns of the second part.

The specific interleaving method will be described later.

Meanwhile, the group twist interleaver 123 changes only the order of bits in the bit group and does not change the order of bit groups by interleaving. Accordingly, the order of the bit groups to be block-interleaved by the block interleaver 124 , that is, the order of the bit groups to be input to the block interleaver 124 , may be determined by the group interleaver 122 . Specifically, the order of the bit groups to be block-interleaved by the block interleaver 124 may be determined by π(j) defined in Tables 11 to 22.

As described above, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged in bit group wise by using the plurality of columns each including the plurality of rows.

In this case, the block interleaver 124 may interleave the LDPC codeword by dividing the plurality of columns into at least two parts. For example, the block interleaver 124 may divide each of the plurality of columns into the first part and the second part and interleave the plurality of bit groups constituting the LDPC codeword.

In this case, the block interleaver 124 may divide each of the plurality of columns into N number of parts (N is an integer greater than or equal to 2) according to whether the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124 , and may perform interleaving.

When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124 , the block interleaver 124 may interleave the plurality of bit groups constituting the LDPC codeword in bit group wise without dividing each of the plurality of columns into parts.

Specifically, the block interleaver 124 may interleave by writing the plurality of bit groups of the LDPC codeword on each of the columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

In this case, the block interleaver 124 may interleave by writing bits included in a predetermined number of bit groups, which corresponds to a quotient obtained by dividing the number of bit groups of the LDPC codeword by the number of columns of the block interleaver 124 , on each of the plurality of columns serially in a column direction, and reading each row of the plurality of columns in which the bits are written in a row direction.

Hereinafter, the group located in the j th position after being interleaved by the group interleaver 122 will be referred to as group Y j .

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R 1 number of rows. In addition, it is assumed that the LDPC codeword is formed of N group number of bit groups and the number of bit groups N group is a multiple of C.

In this case, when the quotient obtained by dividing N group number of bit groups constituting the LDPC codeword by C number of columns constituting the block interleaver 124 is A (=N group /C) (A is an integer greater than 0), the block interleaver 124 may interleave by writing A (=N group /C) number of bit groups on each column serially in a column direction and reading bits written on each column in a row direction.

For example, as shown in FIG. 9 , the block interleaver 124 writes bits included in bit group Y 0 , bit group Y 1 , . . . , bit group Y A−1 , . . . , in the 1 st column from the 1 st row to the R 1 th row, writes bits included in bit group Y A , bit group Y A+1 , . . . , bit group Y 2A-1 in the 2nd column from the 1 st row to the R 1 th row, . . . , and writes bits included in bit group Y CA-A , bit group Y CA-A+1 , . . . , bit group Y CA-1 in the column C from the 1 st row to the R 1 th row. The block interleaver 124 may read the bits written in each row of the plurality of columns in a row direction.

Accordingly, the block interleaver 124 interleaves all bit groups constituting the LDPC codeword in bit group wise.

However, when the number of bit groups of the LDPC codeword is not an integer multiple of the number of columns of the block interleaver 124 , the block interleaver 124 may divide each column into 2 parts and interleave a part of the plurality of bit groups of the LDPC codeword in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. In this case, the bits included in the other bit groups, that is, the bits included in the number of groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns are not interleaved in bit group wise, but interleaved by being divided according to the number of columns.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.

In this case, the block interleaver 124 may divide the plurality of columns into the first part and the second part based on at least one of the number of columns of the block interleaver 124 , the number of bit groups of the LDPC codeword, and the number of bits of bit groups.

Here, each of the plurality of bit groups may be formed of 360 bits. In addition, the number of bit groups of the LDPC codeword is determined based on the length of the LDPC codeword and the number of bits included in the bit group. For example, when an LDPC codeword in the length of 16200 is divided such that each bit group has 360 bits, the LDPC codeword is divided into 45 bit groups. Alternatively, when an LDPC codeword in the length of 64800 is divided such that each bit group has 360 bits, the LDPC codeword may be divided into 180 bit groups. Further, the number of columns constituting the block interleaver 124 may be determined according to a modulation method. This will be explained in detail below.

Accordingly, the number of rows constituting each of the first part and the second part may be determined based on the number of columns constituting the block interleaver 124 , the number of bit groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of bit groups.

Specifically, in each of the plurality of columns, the first part may be formed of as many rows as the number of bits included in at least one bit group which can be written in each column in bit group wise from among the plurality of bit groups of the LDPC codeword, according to the number of columns constituting the block interleaver 124 , the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group.

In each of the plurality of columns, the second part may be formed of rows excluding as many rows as the number of bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise. Specifically, the number rows of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver 124 . In other words, the number of rows of the second part may be the same value as a quotient when the number of bits included in the remaining bit groups which are not written in the first part from among bit groups constituting the LDPC codeword is divided by the number of columns.

That is, the block interleaver 124 may divide each of the plurality of columns into the first part including as many rows as the number of bits included in bit groups which can be written in each column in bit group wise, and the second part including the other rows.

Accordingly, the first part may be formed of as many rows as the number of bits included in bit groups, that is, as many rows as an integer multiple of M. However, since the number of codeword bits constituting each bit group may be an aliquot part of M as described above, the first part may be formed of as many rows as an integer multiple of the number of bits constituting each bit group.

In this case, the block interleaver 124 may interleave by writing and reading the LDPC codeword in the first part and the second part in the same method.

Specifically, the block interleaver 124 may interleave by writing the LDPC codeword in the plurality of columns constituting each of the first part and the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in which the LDPC codeword is written in a row direction.

That is, the block interleaver 124 may interleave by writing the bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise in each of the plurality of columns of the first part serially, dividing the bits included in the other bit groups except the at least some bit groups and writing in each of the plurality of columns of the second part in a column direction, and reading the bits written in each of the plurality of columns constituting each of the first part and the second part in a row direction.

In this case, the block interleaver 124 may interleave by dividing the other bit groups except the at least some bit groups from among the plurality of bit groups based on the number of columns constituting the block interleaver 124 .

Specifically, the block interleaver 124 may interleave by dividing the bits included in the other bit groups by the number of a plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the second part, where the divided bits are written, in a row direction.

That is, the block interleaver 124 may divide the bits included in the other bit groups except the bit groups written in the first part from among the plurality of bit groups of the LDPC codeword, that is, the bits in the number of bit groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns, by the number of columns, and may write the divided bits in each column of the second part serially in a column direction.

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R 1 number of rows. In addition, it is assumed that the LDPC codeword is formed of N group number of bit groups, the number of bit groups N group is not a multiple of C, and A×C+1=N group (A is an integer greater than 0). In other words, it is assumed that when the number of bit groups constituting the LDPC codeword is divided by the number of columns, the quotient is A and the remainder is 1.

In this case, as shown in FIGS. 10 and 11 , the block interleaver 124 may divide each column into a first part including R 1 number of rows and a second part including R 2 number of rows. In this case, R 1 may correspond to the number of bits included in bit groups which can be written in each column in bit group wise, and R 2 may be R 1 subtracted from the number of rows of each column.

That is, in the above-described example, the number of bit groups which can be written in each column in bit group wise is A, and the first part of each column may be formed of as many rows as the number of bits included in A number of bit groups, that is, may be formed of as many rows as A×M number.

In this case, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise, that is, A number of bit groups, in the first part of each column in the column direction.

That is, as shown in FIGS. 10 and 11 , the block interleaver 124 writes the bits included in each of bit group Y 0 , bit group Y 1 , . . . , group Y A−1 in the 1 st to R 1 th rows of the first part of the 1 st column, writes bits included in each of bit group Y A , bit group Y A+1 , . . . , bit group Y 2A4-1 in the 1 st to R 1 th rows of the first part of the 2 nd column, . . . , writes bits included in each of bit group Y CA-A , bit group Y CA-A+1 , . . . , bit group Y CA-1 in the 1 st to Rid rows of the first part of the column C.

As described above, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise in the first part of each column.

In other words, in the above exemplary embodiment, the bits included in each of bit group (Y 0 ), bit group (Y 1 ), . . . , bit group (Y A−1 ) may not be divided and all of the bits may be written in the first column, the bits included in each of bit group (Y A ), bit group (Y A+1 ), . . . , bit group (Y 2A-1 ) may not be divided and all of the bits may be written in the second column, . . . , and the bits included in each of bit group (Y CA-A ), bit group (Y CA-A+1 ), . . . , group (Y CA-1 ) may not be divided and all of the bits may be written in the C column. As such, all bit groups interleaved by the first part are written in the same column of the first part.

Thereafter, the block interleaver 124 divides bits included in the other bit groups except the bit groups written in the first part of each column from among the plurality of bit groups, and writes the bits in the second part of each column in the column direction. In this case, the block interleaver 124 divides the bits included in the other bit groups except the bit groups written in the first part of each column by the number of columns, so that the same number of bits are written in the second part of each column, and writes the divided bits in the second part of each column in the column direction.

In the above-described example, since A×C+1=N group when the bit groups constituting the LDPC codeword are written in the first part serially, the last bit group Y Ngroup-1 of the LDPC codeword is not written in the first part and remains. Accordingly, the block interleaver 124 divides the bits included in the bit group Y Ngroup-1 into C number of sub bit groups as shown in FIG. 10 , and writes the divided bits (that is, the bits corresponding to the quotient when the bits included in the last group (Y Ngroup-1 ) are divided by C) in the second part of each column serially.

The bits divided based on the number of columns may be referred to as sub bit groups. In this case, each of the sub bit groups may be written in each column of the second part. That is, the bits included in the bit groups may be divided and may form the sub bit groups.

That is, the block interleaver 124 writes the bits in the 1 st to R 2 th rows of the second part of the 1 st column, writes the bits in the 1 st to R 2 th rows of the second part of the 2 nd column, . . . , and writes the bits in the 1 st to R 2 th rows of the second part of the column C. In this case, the block interleaver 124 may write the bits in the second part of each column in the column direction as shown in FIG. 10 .

That is, in the second part, the bits constituting the bit group may not be written in the same column and may be written in the plurality of columns. In other words, in the above example, the last bit group (Y Ngroup-1 ) is formed of M number of bits and thus, the bits included in the last bit group (Y Ngroup-1 ) may be divided by M/C and written in each column. That is, the bits included in the last bit group (Y Ngroup-1 ) are divided by M/C, forming M/C number of sub bit groups, and each of the sub bit groups may be written in each column of the second part.

Accordingly, in at least one bit group which is interleaved by the second part, the bits included in the at least one bit group are divided and written in at least two columns constituting the second part.

In the above-described example, the block interleaver 124 writes the bits in the second part in the column direction. However, this is merely an example. That is, the block interleaver 124 may write the bits in the plurality of columns of the second part in the row direction. In this case, the block interleaver 124 may write the bits in the first part in the same method as described above.

Specifically, referring to FIG. 11 , the block interleaver 124 writes the bits from the 1 st row of the second part in the 1 st column to the 1 st row of the second part in the column C, writes the bits from the 2 nd row of the second part in the 1st column to the 2 nd row of the second part in the column C, . . . , etc., and writes the bits from the R 2 th row of the second part in the 1 st column to the R 2 th row of the second part in the column C.

On the other hand, the block interleaver 124 reads the bits written in each row of each part serially in the row direction. That is, as shown in FIGS. 10 and 11 , the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns serially in the row direction, and reads the bits written in each row of the second part of the plurality of columns serially in the row direction.

Accordingly, the block interleaver 124 may interleave a part of the plurality of bit groups constituting the LDPC codeword in bit group wise, and divide and interleave some of the remaining bit groups. That is, the block interleaver 124 may interleave by writing the LDPC codeword constituting a predetermined number of bit groups from among the plurality of bit groups in the plurality of columns of the first part in bit group wise, dividing the bits of the other bit groups and writing the bits in each of the columns of the second part, and reading the plurality of columns of the first and second parts in the row direction.

As described above, the block interleaver 124 may interleave the plurality of bit groups in the methods described above with reference to FIGS. 9 to 11 .

In particular, in the case of FIG. 10 , the bits included in the bit group which does not belong to the first part are written in the second part in the column direction and read in the row direction. In view of this, the order of the bits included in the bit group which does not belong to the first part is rearranged. Since the bits included in the bit group which does not belong to the first part are interleaved as described above, bit error rate (BER)/frame error rate (FER) performance can be improved in comparison with a case in which such bits are not interleaved.

However, the bit group which does not belong to the first part may not be interleaved as shown in FIG. 11 . That is, since the block interleaver 124 writes and reads the bits included in the group which does not belong to the first part in and from the second part in the row direction, the order of the bits included in the group which does not belong to the first part is not changed and the bits are output to the modulator 130 serially. In this case, the bits included in the group which does not belong to the first part may be output serially and mapped onto a modulation symbol.

In FIGS. 10 and 11 , the last single bit group of the plurality of bit groups is written in the second part. However, this is merely an example. The number of bit groups written in the second part may vary according to the total number of bit groups of the LDPC codeword, the number of columns and rows, the number of transmission antennas, etc.

The block interleaver 124 may have a configuration as shown in tables 23 and 24 presented below:

Herein, C (or N C ) is the number of columns of the block interleaver 124 , R 1 is the number of rows constituting the first part in each column, and R 2 is the number of rows constituting the second part in each column.

Referring to Tables 23 and 24, the number of columns has the same value as a modulation order according to a modulation method, and each of a plurality of columns is formed of rows corresponding to the number of bits constituting the LDPC codeword divided by the number of a plurality of columns.

For example, when the length N ldpc of the LDPC codeword is 64800 and the modulation method is 16-QAM, the block interleaver 124 is formed of 4 columns as the modulation order is 4 in the case of 16-QAM, and each column is formed of rows as many as R 1 +R 2 =16200(=64800/4). In another example, when the length N ldpc of the LDPC codeword is 64800 and the modulation method is 64-QAM, the block interleaver 124 is formed of 6 columns as the modulation order is 6 in the case of 64-QAM, and each column is formed of rows as many as R 1 +R 2 =10800(=64800/6).

Meanwhile, referring to Tables 23 and 24, when the number of bit groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R 1 corresponds to the number of rows constituting each column, and R 2 is 0. In addition, when the number of bit groups constituting an LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R 1 number of rows, and the second part formed of R 2 number of rows.

When the number of columns of the block interleaver 124 is equal to the number of bits constituting a modulation symbol, bits included in a same bit group are mapped onto a single bit of each modulation symbol as shown in Tables 23 and 24.

For example, when N ldpc =64800 and the modulation method is 16-QAM, the block interleaver 124 may be formed of four (4) columns each including 16200 rows. In this case, the bits included in each of the plurality of bit groups are written in the four (4) columns and the bits written in the same row in each column are output serially. In this case, since four (4) bits constitute a single modulation symbol in the modulation method of 16-QAM, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the 1 st column may be mapped onto the first bit of each modulation symbol.

In another example, when N ldpc =64800 and the modulation method is 64-QAM, the block interleaver 124 may be formed of six (6) columns each including 10800 rows. In this case, the bits included in each of the plurality of bit groups are written in the six (6) columns and the bits written in the same row in each column are output serially. In this case, since six (6) bits constitute a single modulation symbol in the modulation method of 64-QAM, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the 1 st column may be mapped onto the first bit of each modulation symbol.

Referring to Tables 23 and 24, the total number of rows of the block interleaver 124 , that is, R 1 +R 2 , is N ldpc /C.

In addition, the number of rows of the first part, R 1 , is an integer multiple of the number of bits included in each group, M (e.g., M=360), and maybe expressed as └N group /C┘×M, and the number of rows of the second part, R 2 , may be N ldpc /C−R 1 . Herein, └N group /C┘ is the largest integer below N group /C. Since R 1 is an integer multiple of the number of bits included in each group, M, bits may be written in R 1 in bit groups wise.

In addition, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, it can be seen from Tables 23 and 24 that the block interleaver 124 interleaves by dividing each column into two parts.

Specifically, the length of the LDPC codeword divided by the number of columns is the total number of rows included in the each column. In this case, when the number of bit groups of the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, each column is divided into two parts.

For example, it is assumed that the number of columns of the block interleaver 124 is identical to the number of bits constituting a modulation symbol, and an LDPC codeword is formed of 64800 bits as shown in Table 28. In this case, each bit group of the LDPC codeword is formed of 360 bits, and the LDPC codeword is formed of 64800/360(=180) bit groups.

When the modulation method is 16-QAM, the block interleaver 124 may be formed of four (4) columns and each column may have 64800/4(=16200) rows.

In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/4(=45), bits can be written in each column in bit group wise without dividing each column into two parts. That is, bits included in 45 bit groups which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, that is, 45×360(=16200) bits can be written in each column.

However, when the modulation method is 256-QAM, the block interleaver 124 may be formed of eight (8) columns and each column may have 64800/8(=8100) rows.

In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/8=22.5, the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight (8) columns into two parts to perform interleaving in bit group wise.

In this case, since the bits should be written in the first part of each column in bit group wise, the number of bit groups which can be written in the first part of each column in bit group wise is 22, which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, and accordingly, the first part of each column has 22×360(=7920) rows. Accordingly, 7920 bits included in 22 bit groups may be written in the first part of each column.

The second part of each column has rows which are the rows of the first part subtracted from the total rows of each column. Accordingly, the second part of each column includes 8100−7920(=180) rows.

In this case, the bits included in the other bit groups which have not been written in the first part are divided and written in the second part of each column.

Specifically, since 22×8(=176) bit groups are written in the first part, the number of bit groups to be written in the second part is 180−176 (=4) (for example, bit group Y 176 , bit group Y 177 , bit group Y 178 , and bit group Y 179 from among bit group Y 0 , bit group Y 1 , bit group Y 2 , . . . , bit group Y 178 , and bit group Y 179 constituting the LDPC codeword).

Accordingly, the block interleaver 124 may write the four (4) bit groups which have not been written in the first part and remains from among the groups constituting the LDPC codeword in the second part of each column serially.

That is, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y 176 in the 1st row to the 180 th row of the second part of the 1st column in the column direction, and may write the other 180 bits in the Pt row to the 180 th row of the second part of the 2 nd column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y 177 in the 1st row to the 180 th row of the second part of the 3 rd column in the column direction, and may write the other 180 bits in the Pt row to the 180 th row of the second part of the 4 th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y 178 in the Pt row to the 180 th row of the second part of the 5 th column in the column direction, and may write the other 180 bits in the Pt row to the 180 th row of the second part of the 6 th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y 179 in the 1st row to the 180 th row of the second part of the 7 th column in the column direction, and may write the other 180 bits in the Pt row to the 180 th row of the second part of the 8 th column in the column direction.

Accordingly, the bits included in the bit group which has not been written in the first part and remains are not written in the same column in the second part and may be divided and written in the plurality of columns.

Hereinafter, the block interleaver 124 of FIG. 5 according to an exemplary embodiment will be explained in detail with reference to FIG. 12 .

In a group-interleaved LDPC codeword (v 0 , v 1 , . . . , v N ldpc −1 ), Y 1 is continuously arranged like V={Y 0 , Y 1 , . . . Y N group −1 }.

The LDPC codeword after group interleaving may be interleaved by the block interleaver 124 as shown in FIG. 12 . In this case, the block interleaver 124 divide a plurality of columns into the first part(Part 1) and the second part(Part 2) based on the number of columns of the block interleaver 124 and the number of bits of bit groups. In this case, in the first part, the bits constituting the bit groups may be written in the same column, and in the second part, the bits constituting the bit groups may be written in a plurality of columns(i.e. the bits constituting the bit groups may be written in at least two columns).

Specifically, input bits vi are written serially from the first part to the second part column wise, and then read out serially from the first part to the second part row wise. That is, the data bits V, are written serially into the block interleaver column-wise starting in the first aprt and continuing column-wise finishing in the second part, and then read out serially row-wise from the first part and then row-wise from the second part. Accordingly, the bit included in the same bit group in the first part may be mapped onto a single bit of each modulation symbol.

In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 vary according to a modulation format and a length of the LDPC codeword as in Table 25 presented below. That is, the first part and the second part block interleaving configurations for each modulation format and code length are specified in Table 25 presented below. Herein, the number of columns of the block interleaver 124 may be equal to the number of bits constituting a modulation symbol. In addition, a sum of the number of rows of the first part, N r1 and the number of rows of the second part, N r2 , is equal to N ldpc /N C (herein, N C is the number of columns). In addition, since N r1 (=└N group /N c ┘×360) is a multiple of 360, a multiple of bit groups may be written in the first part.

Hereinafter, an operation of the block interleaver 124 will be explained in detail.

Specifically, as shown in FIG. 12 , the input bit v i (0≤i<N C ×N r1 ) is written in r i row of c i column of the first part of the block interleaver 124 . Herein, c i and r i are

c i = ⌊ i N r ⁢ 1 ⌋

and r i =(i mod N r1 ), respectively.

In addition, the input bit v i (N C ×N r1 ≤i<N ldpc ) is written in r row of c i column of the second part of the block interleaver 124 . Herein, c i and r i satisfy

c i = ⌊ ( i - N C × N r ⁢ 1 ) N r ⁢ 2 ⌋

and r i =N r1 +{(i−N C ×N r1 )mod N r2 }, respectively.

An output bit q j (0≤j<N ldpc ) is read from c j column of r j row. Herein, r j and c j satisfy

r j = ⌊ j N c ⌋

and c j =(j mod N C ), respectively.

For example, when the length N ldpc of an LDPC codeword is 64800 and the modulation method is 256-QAM, the order of bits output from the block interleaver 124 may be (q 0 , q 1 , q 2 , . . . , q 63357 , q 63358 , q 63359 , q 63360 , q 63361 , . . . , q 64799 )=(v 0 , v 7920 , v 15840 , . . . , v 47519 , v 55439 , v 63359 , v 63360 , v 63540 , . . . , v 64799 ). Herein, the indexes of the right side of the foregoing equation may be specifically expressed for the eight (8) columns as 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, . . . , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, . . . , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Hereinafter, the interleaving operation of the block interleaver 124 will be explained in detail.

The block interleaver 124 may interleave by writing a plurality of bit groups in each column in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

In this case, the number of columns constituting the block interleaver 124 may vary according to a modulation method, and the number of rows may be the length of the LDPC codeword/the number of columns.

For example, when the modulation method is 16-QAM, the block interleaver 124 may be formed of 4 columns. In this case, when the length N ldpc of the LDPC codeword is 16200, the number of rows is 16200 (=64800/4). In another example, when the modulation method is 64-QAM, the block interleaver 124 may be formed of 6 columns. In this case, when the length N ldpc of the LDPC codeword is 64800, the number of rows is 10800 (=64800/6).

Hereinafter, the method for interleaving the plurality of bit groups in bit group wise by the block interleaver 124 will be explained in detail.

When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 may interleave by writing the bit groups as many as the number of bit groups divided by the number of columns in each column serially in bit group wise.

For example, when the modulation method is 16-QAM and the length N ldpc of the LDPC codeword is 64800, the block interleaver 124 may be formed of four (4) columns each including 16200 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length N ldpc of the LDPC codeword is 64800, the number of bit groups (=180) of the LDPC codeword may be an integer multiple of the number of columns (=4) when the modulation method is 16-QAM. That is, no remainder is generated when the number of bit groups of the LDPC codeword is divided by the number of columns.

In this case, as shown in FIG. 13 , the block interleaver 124 writes the bits included in each of the bit group Y 0 , bit group Y 1 , . . . , bit group Y 44 in the 1 st row to 16200 th row of the first column, writes the bits included in each of the bit group Y 45 , the bit group Y 46 , . . . , the bit group Y 89 in the 1st row to 16200 th row of the second column, writes the bits included in each of the bit group Y 90 , the bit group Y 91 , . . . , the bit group Y 134 in the 1st row to 16200 th row of the third column, and writes the bits included in each of the bit group Y 135 , the bit group Y 136 , . . . , the bit group Y 179 in the 1st row to 16200 th row of the fourth column. In addition, the block interleaver 124 may read the bits written in each row of the two columns serially in the row direction.

In another, when the modulation method is 64-QAM and the length N ldpc of the LDPC codeword is 64800, the block interleaver 124 may be formed of six (6) columns each including 10800 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length N ldpc of the LDPC codeword is 64800, the number of bit groups (=180) of the LDPC codeword may be an integer multiple of the number of columns (=4) when the modulation method is 64-QAM. That is, no remainder is generated when the number of bit groups of the LDPC codeword is divided by the number of columns.

In this case, as shown in FIG. 14 , the block interleaver 124 writes the bits included in each of the bit group Y 0 , bit group Y 1 , . . . , bit group Y 29 in the 1st row to 10800 th row of the first column, writes the bits included in each of the bit group Y 30 , the bit group Y 31 , . . . , the bit group Y 59 in the 1st row to 10800 th row of the second column, writes the bits included in each of the bit group Y 60 , the bit group Y 61 , . . . , the bit group Y 89 in the 1st row to 10800 th row of the third column, writes the bits included in each of the bit group Y 90 , the bit group Y 91 , . . . , the bit group Y 119 in the 1st row to 10800 th row of the fourth column, writes the bits included in each of the bit group Y 120 , the bit group Y 121 , . . . , the bit group Y 149 in the 1st row to 10800 th row of the fifth column, and writes the bits included in each of the bit group Y 150 , the bit group Y 151 , . . . , the bit group Y 179 in the 1st row to 10800 th row of the sixth column. In addition, the block interleaver 124 may read the bits written in each row of the two columns serially in the row direction.

As described above, when the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns of the block interleaver 124 , the block interleaver 124 may interleave the plurality of bit groups in bit group wise, and accordingly, the bits belonging to the same bit group may be written in the same column.

As described above, the block interleaver 124 may interleave the plurality of bit groups of the LDPC codeword in the method described above with reference to FIGS. 13 and 14 .

The modulator 130 maps the interleaved LDPC codeword onto a modulation symbol. Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword, modulate the demultiplexed LDPC codeword, and map the LDPC codeword onto a constellation.

In this case, the modulator 130 may generate a modulation symbol using the bits included in each of a plurality of bit groups.

In other words, as described above, the bits included in different bit groups are written in each column of the block interleaver 124 , and the block interleaver 124 reads the bits written in each column in the row direction. In this case, the modulator 130 generates a modulation symbol by mapping the bits read in each column onto each bit of the modulation symbol. Accordingly, each bit of the modulation symbol belongs to a different bit group.

For example, it is assumed that the modulation symbol consists of C number of bits. In this case, the bits which are read from each row of C number of columns of the block interleaver 124 may be mapped onto each bit of the modulation symbol and thus, each bit of the modulation symbol consisting of C number of bits belong to C number of different bit groups.

Hereinbelow, the above feature will be described in greater detail.

First, the modulator 130 demultiplexes the interleaved LDPC codeword. To achieve this, the modulator 130 may include a demultiplexer (not shown) to demultiplex the interleaved LDPC codeword.

The demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, the demultiplexer (not shown) performs serial-to-parallel conversion with respect to the interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword into a cell having a predetermined number of bits (or a data cell).

For example, as shown in FIG. 15 , the demultiplexer (not shown) receives the LDPC codeword Q=(q 0 , q 1 , q 2 , . . . ) output from the interleaver 120 , outputs the received LDPC codeword bits to a plurality of substreams serially, converts the input LDPC codeword bits into cells, and outputs the cells.

In this case, the bits having the same index in each of the plurality of substreams may constitute the same cell. Accordingly, the cells may be configured like (y 0,0 , y 1,0 , . . . , y ηMOD−1,0 )=(q 0 , q 1 , q ηMOD−1 ), (y 0,1 , y 1,1 , . . . , y ηMOD−1,1 )=(q ηMOD , q ηMOD+1 , . . . , q 2xηMOD−1 ), . . . .

Herein, the number of substreams, N substreams , may be equal to the number of bits constituting a modulation symbol, η MOD . Accordingly, the number of bits constituting each cell may be equal to the number of bits constituting a modulation symbol (that is, a modulation order).

For example, when the modulation method is 16-QAM, the number of bits constituting the modulation symbol, η MOD , is 4 and thus the number of substreams, N substreams , is 4, and the cells may be configured like (y 0,0 , y 1,0 , y 2,0 , y 3,0 )=(q 0 , q 1 , q 2 , q 3 ), (y 0,1 , y 1,1 , y 2,1 , y 3,1 )=(q 4 ,q 5 , q 6 ,q 7 ), (Y 0,2 , Y 1,2 , Y 2,2 , Y 3,2 )=(q 8 , q 9 , q 10 , q 11 ), . . . .

In another example, when the modulation method is 64-QAM, the number of bits constituting the modulation symbol, η MOD , is 6 and thus the number of substreams, N substreams , is 6, and the cells may be configured like (y 0,0 , y 1,0 , y 2,0 , y 3,0 , y 4,0 , y 5,0 )=(q 0 , q 1 , q 2 , q 3 , q 4 , q 5 ), (y 0,1 , y 1,1 , Y 2,1 , Y 3,1 , y 4,1 , y 5,1 )=(q 6 ,q 7 , q 8 ,q 9 , q 10 ,q 11 ), (Y 0,2 , Y 1,2 , y 2,2 , y 3,2 , y 4,2 , y 5,2 )=(q 12 , q 13 , q 14 , q 15 , q 16 , q 17 ), . . . .

The modulator 130 may map the demultiplexed LDPC codeword onto modulation symbols.

Specifically, the modulator 130 may modulate bits (that is, cells) output from the demultiplexer (not shown) in various modulation methods such as Quadrature Phase Shift Keying (QPSK), 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, etc. For example, when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, the number of bits constituting the modulation symbol, η MOD (that is, the modulation order), may be 2, 4, 6, 8, 10 and 12, respectively.

In this case, since each cell output from the demultiplexer (not shown) is formed of as many bits as the number of bits constituting the modulation symbol, the modulator 130 may generate the modulation symbol by mapping each cell output from the demultiplexer (not shown) onto a constellation point serially. Herein, the modulation symbol corresponds to a constellation point on the constellation.

However, the above-described demultiplexer (not shown) may be omitted according to circumstances. In this case, the modulator 130 may generate modulation symbols by grouping a predetermined number of bits from interleaved bits serially and mapping the predetermined number of bits onto constellation points. In this case, the modulator 130 may generate the modulation symbols by mapping η MOD number of bits onto the constellation points serially according to a modulation method.

The modulator 130 may modulate by mapping cells output from the demultiplexer (not shown) onto constellation points in a non-uniform constellation (NUC) method.

In the non-uniform constellation method, once a constellation point of the first quadrant is defined, constellation points in the other three quadrants may be determined as follows. For example, when a set of constellation points defined for the first quadrant is X, the set becomes −conj(X) in the case of the second quadrant, becomes conj(X) in the case of the third quadrant, and becomes −(X) in the case of the fourth quadrant.

That is, once the first quadrant is defined, the other quadrants may be expressed as follows:

1 Quarter (first quadrant)=X 2 Quarter (second quadrant)=−conj(X) 3 Quarter (third quadrant)=conj(X) 4 Quarter (fourth quadrant)=− X

Specifically, when the non-uniform M-QAM is used, M number of constellation points may be defined as z={z 0 , z 1 , . . . , z M−1 }. In this case, when the constellation points existing in the first quadrant are defined as {x 0 , x 1 , x 2 , . . . , x M/4-1 }, z may be defined as follows:

from z 0 to z M/4-1 =from x 0 to x M/4 from z M/4 to z 2×M/4-1 =−conj(from x 0 to x M/4 ) from z 2×M/4 to z 3×M/4-1 =conj(from x 0 to x M/4 ) from z 3×m/4 to z 4×m/4-1 =−(from x 0 to x m/4 )

Accordingly, the modulator 130 may map the bits [y 0 , . . . , y m-1 ] output from the demultiplexer (not shown) onto constellation points in the non-uniform constellation method by mapping the output bits onto z L having an index of

L = ∑ i = 0 m - 1 ( y 1 × 2 m - 1 ) .

An example of the constellation defined according to the non-uniform constellation method may be expressed as in tables 26 to 30 presented below when the code rate is 5/15, 7/15, 9/15, 11/15, 13/15:

Table 26 indicates non-uniform QPSK, table 27 indicates non-uniform 16-QAM, Tables 28 and 29 indicate non-uniform 64-QAM, and table 30 indicates non-uniform 256-QAM.

Referring to these tables, the constellation point of the first quadrant may be defined with reference to tables 26 to 30, and the constellation points in the other three quadrants may be defined in the above-described method.

However, this is merely an example and the modulator 130 may map the output bits outputted from the demultiplexer (not shown) onto the constellation points in various methods.

The interleaving is performed in the above-described method for the following reasons.

Specifically, when the LDPC codeword bits are mapped onto the modulation symbol, the bits may have different reliability (that is, receiving performance or receiving probability) according to where the bits are mapped onto in the modulation symbol. The LDPC codeword bits may have different codeword characteristics according to the configuration of a parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1 existing in the column of the parity check matrix, that is, the column degree.

Accordingly, the interleaver 120 may interleave to map the LDPC codeword bits having a specific codeword characteristic onto specific bits in the modulation symbol by considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

For example, when the LDPC codeword formed of bit groups X 0 to X 179 is group-interleaved based on Equation 21 and Table 11, the group interleaver 122 may output the bit groups in the order of X 55 , X 146 , X 83 , . . . , X 132 , X 135 .

In this case, when the modulation method is 16-QAM, the number of columns of the block interleaver 124 is four (4) and each column may be formed of 16200 rows.

Accordingly, from among the 180 groups constituting the LDPC codeword, 45 bit groups (X 55 , X 146 , X 83 , X 52 , X 62 , X 176 , X 160 , X 68 , X 53 , X 56 , X 81 , X 97 , X 79 , X 113 , X 163 , X 61 , X 58 , X 69 , X 133 , X 108 , X 66 , X 71 , X 86 , X 144 , X 57 , X 67 , X 116 , X 59 , X 70 , X 156 , X 172 , X 65 , X 149 , X 155 , X 82 , X 138 , X 136 , X 141 , X 111 , X 96 , X 170 , X 90 , X 140 , X 64 , X 159 ) may be inputted to the first column of the block interleaver 124 , 45 bit groups (X 15 , X 14 , X 37 , X 54 , X 44 , X 63 , X 43 , X 18 , X 47 , X 7 , X 25 , X 34 , X 29 , X 30 , X 26 , X 39 , X 16 , X 41 , X 45 , X 36 , X 0 , X 23 , X 32 , X 28 , X 27 , X 38 , X 48 , X 33 , X 22 , X 49 , X 51 , X 60 , X 46 , X 21 , X 4 , X 3 , X 20 , X 13 , X 50 , X 35 , X 24 , X 40 , X 17 , X 42 , X 6 ) may be inputted to the second column of the block interleaver 124 , 45 bit groups (X 112 , X 93 , X 127 , X 101 , X 94 , X 115 , X 105 , X 31 , X 19 , X 177 , X 74 , X 10 , X 145 , X 162 , X 102 , X 120 , X 126 , X 95 , X 73 , X 152 , X 129 , X 174 , X 125 , X 72 , X 128 , X 78 , X 171 , X 8 , X 142 , X 178 , X 154 , X 85 , X 107 , X 75 , X 12 , X 9 , X 151 , X 77 , X 117 , X 109 , X 80 , X 106 , X 134 , X 98 , X 1 ) may be inputted to the third column of the block interleaver 124 , and 45 bit groups (X 122 , X 173 , X 161 , X 150 , X 110 , X 175 , X 166 , X 131 , X 119 , X 103 , X 139 , X 148 , X 157 , X 114 , X 147 , X 87 , X 158 , X 121 , X 164 , X 104 , X 89 , X 179 , X 123 , X 118 , X 99 , X 88 , X 11 , X 92 , X 165 , X 84 , X 168 , X 124 , X 169 , X 2 , X 130 , X 167 , X 153 , X 137 , X 143 , X 91 , X 100 , X 5 , X 76 , X 132 , X 135 ) may be inputted to the fourth column of the block interleaver 124 .

In addition, the block interleaver 124 may output the bits inputted to the Pt row to the last row of each column serially, and the bits outputted from the block interleaver 124 may be inputted to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the bits may be outputted serially without changing the order of bits inputted to the demultiplexer (not shown). Accordingly, the bits included in each of the bit groups X 55 , X 15 , X 112 , and X 122 may constitute the modulation symbol.

When the modulation method is 64-QAM, the number of columns of the block interleaver 124 is six (6) and each column may be formed of 10800 rows.

Accordingly, from among the 180 groups constituting the LDPC codeword, 30 bit groups (X 55 , X 146 , X 83 , X 52 , X 62 , X 176 , X 160 , X 68 , X 53 , X 56 , X 81 , X 97 , X 79 , X 113 , X 163 , X 61 , X 58 , X 69 , X 133 , X 108 , X 66 , X 71 , X 86 , X 144 , X 57 , X 67 , X 116 , X 59 , X 70 , X 156 ) may be inputted to the first column of the block interleaver 124 , 30 bit groups (X 172 , X 65 , X 149 , X 155 , X 82 , X 138 , X 136 , X 141 , X 111 , X 96 , X 170 , X 90 , X 140 , X 64 , X 159 , X 15 , X 14 , X 37 , X 54 , X 44 , X 63 , X 43 , X 18 , X 47 , X 7 , X 25 , X 34 , X 29 , X 30 , X 26 ) may be inputted to the second column of the block interleaver 124 , 30 bit groups (X 39 , X 16 , X 41 , X 45 , X 36 , X 0 , X 23 , X 32 , X 28 , X 27 , X 38 , X 48 , X 33 , X 22 , X 49 , X 51 , X 60 , X 46 , X 21 , X 4 , X 3 , X 20 , X 13 , X 50 , X 35 , X 24 , X 40 , X 17 , X 42 , X 6 ) may be inputted to the third column of the block interleaver 124 , 30 bit groups (X 112 , X 93 , X 127 , X 101 , X 94 , X 115 , X 105 , X 31 , X 19 , X 177 , X 74 , X 10 , X 145 , X 162 , X 102 , X 120 , X 126 , X 95 , X 73 , X 152 , X 129 , X 174 , X 125 , X 72 , X 128 , X 78 , X 171 , X 8 , X 142 , X 178 ) may be inputted to the fourth column of the block interleaver 124 , 30 bit groups (X 154 , X 85 , X 107 , X 75 , X 12 , X 9 , X 151 , X 77 , X 117 , X 109 , X 80 , X 106 , X 134 , X 98 , X 1 , X 122 , X 173 , X 161 , X 150 , X 110 , X 175 , X 166 , X 131 , X 119 , X 103 , X 139 , X 148 , X 157 , X 114 , X 147 ) may be inputted to the fifth column of the block interleaver 124 , and 30 bit groups (X 87 , X 158 , X 121 , X 164 , X 104 , X 89 , X 179 , X 123 , X 118 , X 99 , X 88 , X 11 , X 92 , X 165 , X 84 , X 168 , X 124 , X 169 , X 2 , X 130 , X 167 , X 153 , X 137 , X 143 , X 91 , X 100 , X 5 , X 76 , X 132 , X 135 ) may be inputted to the sixth column of the block interleaver 124 .

In addition, the block interleaver 124 may output the bits inputted to the Pt row to the last row of each column serially, and the bits outputted from the block interleaver 124 may be inputted to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the bits may be outputted serially without changing the order of bits inputted to the demultiplexer (not shown). Accordingly, the bits included in each of the bit groups X 55 , X 172 , X 39 , X 112 , X 154 , and X 87 may constitute the modulation symbol.

As described above, since a specific bit is mapped onto a specific bit in a modulation symbol through interleaving, a receiver side can achieve high receiving performance and high decoding performance.

That is, when LDPC codeword bits of high decoding performance are mapped onto high reliability bits from among bits of each modulation symbol, the receiver side may show high decoding performance, but there is a problem that the LDPC codeword bits of the high decoding performance may not be received. In addition, when the LDPC codeword bits of high decoding performance are mapped onto low reliability bits from among the bits of the modulation symbol, initial receiving performance is excellent, and thus, overall performance is also excellent. However, when many bits showing poor decoding performance are received, error propagation may occur.

Accordingly, when LDPC codeword bits are mapped onto modulation symbols, an LDPC codeword bit having a specific codeword characteristic is mapped onto a specific bit of a modulation symbol by considering both codeword characteristics of the LDPC codeword bits and reliability of the bits of the modulation symbol, and is transmitted to the receiver side. Accordingly, the receiver side can achieve high receiving performance and decoding performance.

Hereinafter, a method for determining π(j), which is a parameter used for group interleaving, according to various exemplary embodiments, will be explained.

According to an exemplary embodiment, when the length of the LDPC codeword is 64800, the size of the bit group is determined to be 360 and thus 180 bit groups exist. In addition, there may be 180! possible interleaving patterns (Herein, factorial means A!=A×(A−1)× . . . ×2×1) regarding an integer A.

In this case, since a reliability level between the bits constituting a modulation symbol may be the same according to a modulation order, many number of interleaving patterns may be regarded as the same interleaving operation when theoretical performance is considered. For example, when an MSB bit of the X-axis (or rear part-axis) and an MSB bit the Y-axis(or imaginary part-axis) of a certain modulation symbol have the same theoretical reliability, the same theoretical performance can be achieved regardless of the way how specific bits are interleaved to be mapped onto the two MSB bits.

However, such a theoretical prediction may become incorrect as a real channel environment is established. For example, in the case of the QPSK modulation method, two bits of a symbol in a part of a symmetric channel like an additive white Gaussian noise (AWGN) channel theoretically have the same reliability. Therefore, there should be no difference in the performance theoretically when any interleaving method is used. However, in a real channel environment, the performance may be different depending on the interleaving method. In the case of a well-known Rayleigh channel which is not a real channel, the performance of QPSK greatly depends on the interleaving method and thus the performance can be predicted somewhat only by the reliability between bits of a symbol according to a modulation method. However, there should be a limit to predicting the performance.

In addition, since code performance by interleaving may be greatly changed according to a channel which evaluates performance, channels should be always considered to drive an interleaving pattern. For example, a good interleaving pattern in the AWGN channel may be not good in the Rayleigh channel. If a channel environment where a given system is used is closer to the Rayleigh channel, an interleaving pattern which is better in the Rayleigh channel than in the AWGN channel may be selected.

As such, not only a specific channel environment but also various channel environments considered in a system should be considered in order to derive a good interleaving pattern. In addition, since there is a limit to predicting real performance only by theoretical performance prediction, the performance should be evaluated by directly conducting computation experiments and then the interleaving pattern should be finally determined.

However, since there are so many number of possible interleaving patterns to be applied (for example, 180!), reducing the number of interleaving patterns used to predict and test performance is an important factor in designing a high performance interleaver.

Therefore, the interleaver is designed through the following steps according to an exemplary embodiment.

1) Channels C 1 , C 2 , . . . , C k to be considered by a system are determined. 2) A certain interleaver pattern is generated. 3) A theoretical performance value is predicted by applying the interleaver generated in step 2) to each of the channels determined in step 1). There are various methods for predicting a theoretical performance value, but a well-known noise threshold determining method like density evolution analysis is used according to an exemplary embodiment. The noise threshold recited herein refers to a value that can be expressed by a minimum necessary signal-to-noise ratio (SNR) capable of error-free transmission on the assumption that a cycle-free characteristic is satisfied when the length of a code is infinite and the code is expressed by the Tanner graph. The density evolution analysis may be implemented in various ways, but is not the subject matter of the inventive concept and thus a detailed description thereof is omitted. 4) When noise thresholds for the channels are expressed as TH 1 [i], TH 2 [i], . . . , TH k [i] for the i-th generated interleaver, a final determination threshold value may be defined as follows:

TH[i]=W 1 ×TH 1 [i]M+W 2 ×TH 2 [i]+ . . . +W k ×TH k [i],

where W 1 +W 2 + . . . +W k =1, W 1 , W 2 , . . . , W k >0

Here, W 1 , W 2 , . . . , W k are adjusted according to importance of the channels. That is, W 1 , W 2 , . . . , W k are adjusted to a larger value in a more important channel and W 1 , W 2 , . . . , W k are adjusted to a smaller value in a less important channel (for example, if the weight values of AWGN and Rayleigh channels are W 1 and W 2 , respectively, W 1 may be set to 0.25 and W 2 may be set to 0.75 when one of the channels is determined to be more important.).

5) B number of interleaver patterns are selected in an ascending order of TH[i] values from among the tested interleaver patterns and are directly tested by conducting performance computation experiments. An FER level for the test is determined as 10{circumflex over ( )}−3 (for example, B=100). 6) D number of best interleaver patterns are selected from among the B number of interleaver patterns tested in step 5) (for example, D=5).

In general, an interleaver pattern which has a great SNR gain in the area of FER=10{circumflex over ( )}−3 may be selected as a good performance interleaver in step of 5). However, according to an exemplary embodiment, as shown in FIG. 16 , performance of FER required in the system based on the result of real computation experiments for the area of FER=10{circumflex over ( )}−3 may be predicted through extrapolation, and then an interleaver pattern having good performance in comparison with the expected performance in the FER required in the system may be determined as a good interleaver pattern. According to an exemplary embodiment, the extrapolation based on a linear function may be applied. However, various extrapolation methods may be applied. FIG. 16 illustrates an example of performance extrapolation predicted by the result of computation experiments.

7) The D number of interleaver patterns selected in step 6) are tested by conducting performance computation experiments in each channel. Herein, the FER level for testing is selected as FER required in the system (for example, FER=10{circumflex over ( )}− 6 ) 8) When an error floor is not observed after the computation experiments, an interleaving pattern having the greatest SNR gain is determined as a final interleaving pattern.

FIG. 17 is a view schematically showing a process of determining B number of interleaver patterns in the steps 2), 3), 4), and 5) of the above-described method for determining the interleaving pattern in the case of AWGN and Rayleigh channels for example.

Referring to FIG. 17 , necessary variables i, j, and etc. are initialized in operation S 1701 , and a noise threshold for the AWGN channel THIN and a noise threshold for the Rayleigh channel TH2[i] are calculated in operation S 1702 . Then, a final determination noise threshold TH[i] defined in step 4) is calculated in operation S 1703 , and is compared with a previously calculated final determination noise threshold TH[i−1] in operation S 1704 . When the final determination noise threshold TH[i] is smaller than the previously calculated final determination noise threshold TH[i−1], TH_S[i] is replaced with the TH[i] and is stored in operation S 1706 . Next, i, j values increase by 1 in operation S 1707 and this process is repeated until the i value exceeds A which is pre-defined in operation S 1708 . In this case, A is the total number of interleaver patterns to be tested in steps 2), 3), 4), and 5) and A is typically determined to be greater than or equal to 10000. When all operations described above are completed, interleaver patterns corresponding to TH_S[0], TH_S[1], . . . , TH_S[B−1] which are stored in a descending order of final noise thresholds values in operation S 1709 .

The transmitting apparatus 100 may transmit the signal mapped onto the constellation to a receiving apparatus (for example, 1200 of FIG. 18 ). For example, the transmitting apparatus 100 may map the signal mapped onto the constellation onto an Orthogonal Frequency Division Multiplexing (OFDM) frame using OFDM, and may transmit the signal to the receiving apparatus 1200 through an allocated channel.

FIG. 18 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment. Referring to FIG. 18 , the receiving apparatus 1200 includes a demodulator 1210 , a multiplexer 1220 , a deinterleaver 1230 and a decoder 1240 .

The demodulator 1210 receives and demodulates a signal transmitted from the transmitting apparatus 100 . Specifically, the demodulator 1210 generates a value corresponding to an LDPC codeword by demodulating the received signal, and outputs the value to the multiplexer 1220 . In this case, the demodulator 1210 may use a demodulation method corresponding to a modulation method used in the transmitting apparatus 100 . To do so, the transmitting apparatus 100 may transmit information regarding the modulation method to the receiving apparatus 1200 , or the transmitting apparatus 100 may perform modulation using a pre-defined modulation method between the transmitting apparatus 100 and the receiving apparatus 1200 .

The value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There are various methods for determining the channel value, and for example, a method for determining a Log Likelihood Ratio (LLR) value may be the method for determining the channel value.

The LLR value is a log value for a ratio of the probability that a bit transmitted from the transmitting apparatus 100 is 0 and the probability that the bit is 1. In addition, the LLR value may be a bit value which is determined by a hard decision, or may be a representative value which is determined according to a section to which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 belongs.

The multiplexer 1220 multiplexes the output value of the demodulator 1210 and outputs the value to the deinterleaver 1230 .

Specifically, the multiplexer 1220 is an element corresponding to a demultiplexer (not shown) provided in the transmitting apparatus 100 , and performs an operation corresponding to the demultiplexer (not shown). That is, the multiplexer 1220 performs an inverse operation of the operation of the demultiplexer (not shown), and performs cell-to-bit conversion with respect to the output value of the demodulator 1210 and outputs the LLR value in the unit of bit. However, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100 , the multiplexer 1220 may be omitted from the receiving apparatus 1200 .

The information regarding whether the demultiplexing operation is performed or not may be provided by the transmitting apparatus 100 , or may be pre-defined between the transmitting apparatus 100 and the receiving apparatus 1200 .

The deinterleaver 1230 deinterleaves the output value of the multiplexer 1220 and outputs the values to the decoder 1240 .

Specifically, the deinterleaver 1230 is an element corresponding to the interleaver 120 of the transmitting apparatus 100 and performs an operation corresponding to the interleaver 120 . That is, the deinterleaver 1230 deinterleaves the LLR value by performing the interleaving operation of the interleaver 120 inversely.

To do so, the deinterleaver 1230 may include a block deinterleaver 1231 , a group twist deinterleaver 1232 , a group deinterleaver 1233 , and a parity deinterleaver 1234 as shown in FIG. 18 .

The block deinterleaver 1231 deinterleaves the output of the multiplexer 1220 and outputs the value to the group twist deinterleaver 1232 .

Specifically, the block deinterleaver 1231 is an element corresponding to the block interleaver 124 provided in the transmitting apparatus 100 and performs the interleaving operation of the block interleaver 124 inversely.

That is, the block deinterleaver 1231 deinterleaves by writing the LLR value output from the multiplexer 1220 in each row in the row direction and reading each column of the plurality of rows in which the LLR value is written in the column direction by using at least one row formed of the plurality of columns.

In this case, when the block interleaver 124 interleaves by dividing the column into two parts, the block deinterleaver 1231 may deinterleave by dividing the row into two parts.

In addition, when the block interleaver 124 writes and reads in and from the bit group that does not belong to the first part in the row direction, the block deinterleaver 1231 may deinterleave by writing and reading values corresponding to the group that does not belong to the first part in the row direction.

Hereinafter, the block deinterleaver 1231 will be explained with reference to FIG. 20 . However, this is merely an example and the block deinterleaver 1231 may be implemented in other methods.

An input LLR v i (0≤i≤N ldpc ) is written in a r i row and a c i column of the block deinterleaver 1231 . Herein, c i =(i mod N c ) and

On the other hand, an output LLR q i (0≤i≤N c ×N r1 ) is read from a c i column and a r i row of the first part of the block deinterleaver 1231 . Herein,

c i = ⌊ i N r ⁢ 1 ⌋ ,

r i =(i mod N r1 ).

In addition, an output LLR q i (N c ×N r1 ≤i≤N ldpc ) is read from a c i column and a r i row of the second part. Herein,

c i = ⌊ ( i - N c × N r ⁢ 1 ) N r ⁢ 2 ⌋ ,

r i =N r1 +{(i−N c ×N r1 ) mode N r2 }.

The group twist deinterleaver 1232 deinterleaves the output value of the block deinterleaver 1231 and outputs the value to the group deinterleaver 1233 .

Specifically, the group twist deinterleaver 1232 is an element corresponding to the group twist interleaver 123 provided in the transmitting apparatus 100 , and may perform the interleaving operation of the group twist interleaver 123 inversely.

That is, the group twist deinterleaver 1232 may rearrange the LLR values of the same bit group by changing the order of the LLR values existing in the same bit group. When the group twist operation is not performed in the transmitting apparatus 100 , the group twist deinterleaver 1232 may be omitted.

The group deinterleaver 1233 (or the group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 1232 and outputs the value to the parity deinterleaver 1234 .

Specifically, the group deinterleaver 1233 is an element corresponding to the group interleaver 122 provided in the transmitting apparatus 100 and may perform the interleaving operation of the group interleaver 122 inversely.

That is, the group deinterleaver 1233 may rearrange the order of the plurality of bit groups in bit group wise. In this case, the group deinterleaver 1233 may rearrange the order of the plurality of bit groups in bit group wise by applying the interleaving method of Tables 11 to 22 inversely according to a length of the LDPC codeword, a modulation method and a code rate.

The parity deinterleaver 1234 performs parity deinterleaving with respect to the output value of the group deinterleaver 1233 and outputs the value to the decoder 1240 .

Specifically, the parity deinterleaver 1234 is an element corresponding to the parity interleaver 121 provided in the transmitting apparatus 100 and may perform the interleaving operation of the parity interleaver 121 inversely. That is, the parity deinterleaver 1234 may deinterleave the LLR values corresponding to the parity bits from among the LLR values output from the group deinterleaver 1233 . In this case, the parity deinterleaver 1234 may deinterleave the LLR value corresponding to the parity bits inversely to the parity interleaving method of Equation 18.

However, the parity deinterleaver 1234 may be omitted depending on the decoding method and embodiment of the decoder 1240 .

Although the deinterleaver 1230 of FIG. 18 includes three (3) or four (4) elements as shown in FIG. 19 , operations of the elements may be performed by a single element. For example, when bits each of which belongs to each of bit groups X a , X b , X c , X d constitute a single modulation symbol, the deinterleaver 1230 may deinterleave these bits to locations corresponding to their bit groups based on the received single modulation symbol.

For example, when the code rate is 6/15 and the modulation method is 16-QAM, the group deinterleaver 1233 may perform deinterleaving based on table 11.

In this case, bits each of which belongs to each of bit groups X 55 , X 15 , X 112 , X 122 may constitute a single modulation symbol. Since one bit in each of the bit groups X 55 , X 15 , X 112 , X 122 constitutes a single modulation symbol, the deinterleaver 1230 may map bits onto decoding initial values corresponding to the bit groups X 55 , X 15 , X 112 , X 122 based on the received single modulation symbol.

The decoder 1240 may perform LDPC decoding by using the output value of the deinterleaver 1230 . To achieve this, the decoder 1240 may include an LDPC decoder (not shown) to perform the LDPC decoding.

Specifically, the decoder 1240 is an element corresponding to the encoder 110 of the transmitting apparatus 100 and may correct an error by performing the LDPC decoding by using the LLR value output from the deinterleaver 1230 .

For example, the decoder 1240 may perform the LDPC decoding in an iterative decoding method based on a sum-product algorithm. The sum-product algorithm is one example of a message passing algorithm, and the message passing algorithm refers to an algorithm which exchanges messages (e.g., LLR value) through an edge on a bipartite graph, calculates an output message from messages input to variable nodes or check nodes, and updates.

The decoder 1240 may use a parity check matrix when performing the LDPC decoding. In this case, the parity check matrix used in the decoding may have the same configuration as that of the parity check matrix used in the encoding of the encoder 110 , and this has been described above with reference to FIGS. 2 to 4 .

In addition, information on the parity check matrix and information on the code rate, etc. which are used in the LDPC decoding may be pre-stored in the receiving apparatus 1200 or may be provided by the transmitting apparatus 100 .

FIG. 21 is a flowchart to illustrate an interleaving method of a transmitting apparatus according to an exemplary embodiment.

First, an LDPC codeword is generated by LDPC encoding based on a parity check matrix (S 1410 ), and the LDPC codeword is interleaved (S 1420 ).

Then, the interleaved LDPC codeword is mapped onto a modulation symbol (S 1430 ). In this case, a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword may be mapped onto a predetermined bit in the modulation symbol.

Each of the plurality of bit groups may be formed of M number of bits, and M may be a common divisor of N ldpc and K ldpc and may be determined to satisfy Q ldpc =(N ldpc −K ldpc )/M. Herein, Q ldpc is a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N ldpc is a length of the LDPC codeword, and K ldpc is a length of information word bits of the LDPC codeword.

Operation S 1420 may include interleaving parity bits of the LDPC codeword, dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging the order of the plurality of bit groups in bit group wise, and interleaving the plurality of bit groups the order of which is rearranged.

The order of the plurality of bit groups may be rearranged in bit group wise based on the above-described Equation 21 presented above.

As described above, π(j) in Equation 21 may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

For example, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 6/15, π(j) may be defined as in table 11.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 10/15, π(j) may be defined as in table 14.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, π(j) may be defined as in table 15.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, π(j) may be defined as in table 17.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 8/15, π(j) may be defined as in table 18.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, π(j) may be defined as in table 21.

The interleaving the plurality of bit groups may include: writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

In addition, the interleaving the plurality of bit groups may include: serially write, in the plurality of columns, at least some bit group which is writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit group is written in the plurality of columns in bit group wise.

A non-transitory computer readable medium, which stores a program for performing the interleaving methods according to various exemplary embodiments in sequence, may be provided.

The non-transitory computer readable medium refers to a medium that stores data semi-permanently rather than storing data for a very short time, such as a register, a cache, and a memory, and is readable by an apparatus. Specifically, the above-described various applications or programs may be stored in a non-transitory computer readable medium such as a compact disc (CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal serial bus (USB), a memory card, and a read only memory (ROM), and may be provided.

At least one of the components, elements or units represented by a block as illustrated in FIGS. 1 , 5 , 15 , 18 and 19 may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an exemplary embodiment. For example, at least one of these components, elements or units may use a direct circuit structure, such as a memory, processing, logic, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions. Also, at least one of these components, elements or units may further include a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Further, although a bus is not illustrated in the above block diagrams, communication between the components, elements or units may be performed through the bus. Functional aspects of the above exemplary embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.

The foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present inventive concept. The exemplary embodiments can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the inventive concept, and many alternatives, modifications, and variations will be apparent to those skilled in the art.