A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Description

82 parts

›CROSS-REFERENCE

This application is a continuation of co-pending U.S. application Ser. No. 17/240,597, filed Apr. 26, 2021, which is a continuation of U.S. application Ser. No. 16/818,111, filed on Mar. 13, 2020, now U.S. Pat. No. 11,004,512, which is a continuation of U.S. application Ser. No. 16/653,435, filed on Oct. 15, 2019, now U.S. Pat. No. 10,622,069, which is a continuation of U.S. application Ser. No. 16/441,396, filed on Jun. 14, 2019, now U.S. Pat. No. 10,497,443, which is a continuation of U.S. application Ser. No. 16/239,945, filed on Jan. 4, 2019, now U.S. Pat. No. 10,388,378, which is a continuation of U.S. application Ser. No. 16/003,350, filed on Jun. 8, 2018, now U.S. Pat. No. 10,204,684, which is a continuation of U.S. application Ser. No. 15/654,606, filed on Jul. 19, 2017, now U.S. Pat. No. 10,008,266, which is a continuation of U.S. application Ser. No. 15/436,641, filed on Feb. 17, 2017, now U.S. Pat. No. 9,747,983, which is a continuation of U.S. application Ser. No. 15/237,441, filed on Aug. 15, 2016, now U.S. Pat. No. 9,614,080, which is a continuation application of U.S. application Ser. No. 14/834,695, filed on Aug. 25, 2015, now U.S. Pat. No. 9,455,262, which is a divisional application of U.S. application Ser. No. 13/577,282, having a filing or 371(c) date of Oct. 5, 2012, now U.S. Pat. No. 9,153,309, which claims the benefit under 35 USC 371(c) of PCT Application No. PCT/US2011/023947, which claims the benefit of U.S. Provisional Application No. 61/302,129, filed Feb. 7, 2010, and U.S. Provisional Application No. 61/425,820, filed Dec. 22, 2010 and U.S. Provisional Application No. 61/309,589, filed Mar. 2, 2010, and U.S. application Ser. No. 12/897,538, filed Oct. 4, 2010, now U.S. Pat. No. 8,264,875, and U.S. application Ser. No. 12/897,516, filed Oct. 4, 2010, now U.S. Pat. No. 8,547,756, and U.S. application Ser. No. 12/797,334, filed Jun. 9, 2010, now U.S. Pat. No. 8,130,547, and U.S. application Ser. No. 12/797,320, filed Jun. 9, 2010, now U.S. Pat. No. 8,130,548, and U.S. application Ser. No. 12/897,528, filed Oct. 4, 2010, now U.S. Pat. No. 8,514,622, which applications and patents are each hereby incorporated herein, in their entireties, by reference thereto and to which applications we claim priority under 35 U.S.C. Sections 120, 371 and 119, respectively.

This application also hereby incorporates, in its entirety by reference thereto, application Ser. No. 12/797,320, filed on Jun. 9, 2010, titled “Semiconductor Memory Having Electrically Floating Body Transistor”, application Ser. No. 12/797,334 filed on Jun. 9, 2010, titled “Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor”, application Ser. No. 12/897,528, titled “Compact Semiconductor Device Having Reduced Number of Contacts, Methods of Operating and Method of Making”, application Ser. No. 12/897,516, titled “Semiconductor Memory Device Having An Electrically Floating Body Transistor”, application Ser. No. 12/897,538, titled “Semiconductor Memory Device Having An Electrically Floating Body Transistor”.

›FIELD OF THE INVENTION

The present invention relates to semiconductor memory technology. More specifically, the present invention relates to a semiconductor memory device having an electrically floating body transistor and a semiconductor memory device having both volatile and non-volatile functionality.

›BACKGROUND OF THE INVENTION

Semiconductor memory devices are used extensively to store data. Static and Dynamic Random Access Memory (SRAM and DRAM, respectively) are widely used in many applications. SRAM typically consists of six transistors and hence has a large cell size. However, unlike DRAM, it does not require periodic refresh operations to maintain its memory state. Conventional DRAM cells consist of a one-transistor and one-capacitor (1T/1C) structure. As the 1T/1C memory cell feature is being scaled, difficulties arise due to the necessity of maintaining the capacitance value.

DRAM based on the electrically floating body effect has been proposed (see for example “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002). Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. However, unlike SRAM, such DRAM memory cell still requires refresh operation, since the stored charge leaks over time.

A conventional 1T/1C DRAM refresh operation involves first reading the state of the memory cell, followed by re-writing the memory cell with the same data. Thus this read-then-write refresh requires two operations: read and write. The memory cell cannot be accessed while being refreshed. An “automatic refresh” method”, which does not require first reading the memory cell state, has been described in Fazan et al., U.S. Pat. No. 7,170,807. However, such operation still interrupts access to the memory cells being refreshed.

In addition, the charge in a floating body DRAM memory cell decreases over repeated read operations. This reduction in floating body charge is due to charge pumping, where the floating body charge is attracted to the surface and trapped at the interface (see for example “Principles of Transient Charge Pumping on Partially Depleted SOI MOSFETs”, S. Okhonin, et al., pp. 279-281, IEEE Electron Device Letters, vol. 23, no. 5, May 2002).

Thus there is a continuing need for semiconductor memory devices and methods of operating such devices such that the states of the memory cells of the semiconductor memory device are maintained without interrupting the memory cell access.

There is also a need for semiconductor memory devices and methods of operating the same such that the states of the memory cells are maintained upon repeated read operations.

Non-volatile memory devices, such as flash erasable programmable read only memory (Flash EPROM) devices, retain stored data even in the absence of power supplied thereto. Unfortunately, non-volatile memory devices typically operate more slowly than volatile memory devices.

Flash memory device typically employs a floating gate polysilicon as the non-volatile data storage. This introduces additional process steps from the standard complementary metal-oxide-semiconductor (CMOS) process. US 2010/0172184 “Asymmetric Single Poly NMOS Non-volatile Memory Cell” to Roizin et al. (“Roizin”), describes a method of forming a single poly non-volatile memory device. Similar to many non-volatile memory devices, it operates more slowly than volatile memory devices. In addition, non-volatile memory devices can only perform limited number of cycles, often referred to as endurance cycle limitation.

Accordingly, it would be desirable to provide a universal type memory device that includes the advantages of both volatile and non-volatile memory devices, i.e., fast operation on par with volatile memories, while having the ability to retain stored data when power is discontinued to the memory device. It would further be desirable to provide such a universal type memory device having a size that is not prohibitively larger than comparable volatile or non-volatile devices and which has comparable storage capacity to the same.

The present invention meets the above needs and more as described in detail below.

›SUMMARY OF THE INVENTION · 1 of 6

In one aspect of the present invention, a method of maintaining a state of a memory cell without interrupting access to the memory cell is provided, including: applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

In at least one embodiment, the applying comprises applying the back bias to a terminal of the cell that is not used for address selection of the cell.

In at least one embodiment, the back bias is applied as a constant positive voltage bias.

In at least one embodiment, the back bias is applied as a periodic pulse of positive voltage.

In at least one embodiment, a maximum potential that can be stored in the floating body is increased by the application of back bias to the cell, resulting in a relatively larger memory window.

In at least one embodiment, the application of back bias performs a holding operation on the cell, and the method further comprises simultaneously performing a read operation on the cell at the same time that the holding operation is being performed.

In at least one embodiment, the cell is a multi-level cell, wherein the floating body is configured to indicate more than one state by storing multi-bits, and the method further includes monitoring cell current of the cell to determine a state of the cell.

In another aspect of the present invention, a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells is provided, wherein each memory cell has a floating body region for storing data; the method including: performing a holding operation on at least all of the cells not aligned in a row or column of a selected cell; and accessing the selected cell and performing a read or write operation on the selected cell while performing the hold operation on the at least all of the cells not aligned in a row or column of the selected cell.

In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells and the performing a read or write operation comprises performing a read operation on the selected cell.

In at least one embodiment, the holding operation is performed by applying back bias to a terminal not used for memory address selection.

In at least one embodiment, the terminal is segmented to allow independent control of the applied back bias to a selected portion of the memory array.

In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell, and the performing a read or write operation comprises performing a write “0” operation on the selected cell, wherein a write “0” operation is also performed on all of the cells sharing a common source line terminal with the selected cell during the performing a write“0” operation.

In at least one embodiment, an individual bit write “0” operation is performed, wherein the performing a holding operation comprises performing the holding operation on all of the cells except for the selected cell, while the performing a read or write operation comprises performing a write “0” operation on the selected cell.

In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multi-level write operation on the selected cell, wherein the multi-level write operation includes: ramping a voltage applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in current through the selected cell; and removing the ramped voltage applied once the change in cell current reaches a predetermined value.

In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multi-level write operation on the selected cell, wherein the multi-level write operation includes: ramping a current applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in voltage across a bit line and a source line of the selected cell; and removing the ramped current applied once the change in cell voltage reaches a predetermined value.

In at least one embodiment, the multi-level write operation permits bit-level selection of a bit portion of memory of the selected cell.

In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a single-level or multi-level write operation on the selected cell, wherein the single-level and each level of the multi-level write operation includes: ramping a voltage applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in current toward an addressable terminal of the selected cell; and verifying a state of the write operation using a reference memory cell.

In at least one embodiment, the method further includes configuring a state of the reference memory cell using a write-then-verify operation, prior to performing the write operation.

›SUMMARY OF THE INVENTION · 2 of 6

In at least one embodiment, configuring a state of the reference memory cell comprises configuring the state upon power up of the memory array.

In another aspect of the present invention, a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells is provided, wherein each memory cell has a floating body region for storing data; and wherein the method includes: refreshing a state of at least one of the memory cells; and accessing at least one other of the memory cells, wherein access of the at least one other of the memory cells in not interrupted by the refreshing, and wherein the refreshing is performed without alternating read and write operations.

In at least one embodiment, at least one of the memory cells is a multi-level memory cell.

In another aspect of the present invention, a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells is provided, wherein each memory cell has a floating body region for storing data; and wherein the method includes: accessing a selected memory cell from the memory cells; and performing a simultaneous write and verify operation on the selected memory cell without performing an alternating write and read operation.

In at least one embodiment, the selected memory cell is a multi-level memory cell.

In at least one embodiment, a verification portion of the write and verify operation is performed by sensing a current change in the column direction of the array in a column that the selected cell is connected to.

In at least one embodiment, a verification portion of the write and verify operation is performed by sensing a current change in the row direction of the array in a row that the selected cell is connected to.

In at least one embodiment, a write portion of the write and verify operation employs use of a drain or gate voltage ramp.

In at least one embodiment, a write portion of the write and verify operation employs use of a drain current ramp.

In one aspect of the present invention, an integrated circuit is provided that includes a link or string of semiconductor memory cells, wherein each memory cell comprises a floating body region for storing data; and the link or string comprises at least one contact configured to electrically connect the memory cells to at least one control line, wherein the number of contacts is the same as or less than the number of the memory cells.

In at least one embodiment, the number of contacts is less than the number of memory cells.

In at least one embodiment, the semiconductor memory cells are connected in series and form the string.

In at least one embodiment, the semiconductor memory cells are connected in parallel and form the link.

In at least one embodiment, the integrated circuit is fabricated on a silicon-on-insulator (SOI) substrate.

In at least one embodiment, the integrated circuit is fabricated on a bulk silicon substrate.

In at least one embodiment, the number of contacts is two, and the number of semiconductor memory cells is greater than two.

In at least one embodiment, the memory cells further comprise first and second conductive regions interfacing with the floating body region.

In at least one embodiment, the first and second conductive regions are shared by adjacent ones of the memory cells for each the memory cell having the adjacent memory cells.

In at least one embodiment, each memory cell further comprises first, second, and third conductive regions interfacing with the floating body region.

In at least one embodiment, each memory cell further comprises a gate insulated from the floating body region.

In at least one embodiment, at least one of the memory cells is a contactless memory cell.

In at least one embodiment, a majority of the memory cells are contactless memory cells.

In at least one embodiment, the memory cells store multi-bit data.

In another aspect of the present invention, an integrated circuit is provided that includes a plurality of contactless semiconductor memory cells, each semiconductor memory cell including: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating body region; and an insulating region insulating the gate from the floating body region.

In at least one embodiment, the contactless memory cells are connected in series.

In at least one embodiment, the contactless memory cells are connected in parallel.

In at least one embodiment, the integrated circuit comprises at least one semiconductor memory cell having at least one contact, a total number of the contacts being less than a total number of memory cells that includes a total number of the memory cells having at least one contact and a total number of the contactless memory cells.

In another aspect of the present invention, an integrated circuit is provided that includes: a plurality of semiconductor memory cells connected in series, each semiconductor memory cell comprising: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating body region; and an insulating region insulating the gate and the floating body region.

In at least one embodiment, at least one of the semiconductor memory cells is a contactless semiconductor memory cell.

In at least one embodiment, the at least one contactless semiconductor memory cell comprises a third conductive region interfacing with the floating body region.

In another aspect of the present invention, an integrated circuit is provided that includes a plurality of semiconductor memory cells connected in parallel, each semiconductor memory cell comprising: a floating body region for storing data; a conductive region interfacing with the floating body region; a gate above a surface of the floating body region; and an insulating region insulating the gate from the floating substrate region; wherein at least one of the semiconductor memory cells is a contactless semiconductor memory cell.

›SUMMARY OF THE INVENTION · 3 of 6

In at least one embodiment, a majority of the semiconductor memory cells are contactless semiconductor memory cells.

In at least one embodiment, the integrated circuit comprises a number of contacts, the number being less than or equal to a number of the memory cells.

In at least one embodiment, the memory cells each further comprise a second conductive region interfacing with the floating body region.

In at least one embodiment, the memory cells each further comprise second and third conductive regions interfacing with the floating body region.

In another aspect of the present invention, an integrated circuit is provided that includes a plurality of contactless semiconductor memory cells connected in parallel, each semiconductor memory cell comprising: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating region; and an insulating region insulating the gate and the floating body region.

In another aspect of the present invention, an integrated circuit is provided that includes: a memory string or link comprising a set of contactless semiconductor memory cells; and a first contact contacting a first additional semiconductor memory cell; wherein the contactless semiconductor memory cells are accessible via the first contact.

In at least one embodiment, the integrated circuit further includes a second contact contacting a second additional semiconductor memory cell; wherein the contactless semiconductor memory cells are accessible via the second contact.

In at least one embodiment, the contactless semiconductor memory cells and the additional semiconductor memory cell are connected in series.

In at least one embodiment, the memory string or link comprises a first memory string or link and the set comprises a first set, the integrated circuit further comprising: a second memory string or link comprising a second set of contactless semiconductor memory cells; and a second contact contacting a second additional semiconductor memory cell; wherein the second set of contactless semiconductor memory cells are accessible via the second contact.

In at least one embodiment, the memory string or link comprises a first memory string and the set comprises a first set, the integrated circuit further comprising: a second memory string comprising a second set of contactless semiconductor memory cells; a third contact contacting a third additional semiconductor memory cell; and a fourth contact contacting a fourth additional semiconductor memory cell; wherein the second set of contactless semiconductor memory cells are accessible via the third and fourth contacts; wherein the first set of contactless semiconductor memory cells, the first additional semiconductor memory cell and the second additional semiconductor memory cell are connected in series, and wherein the second set of contactless semiconductor memory cells, the third additional semiconductor memory cell and the fourth additional semiconductor memory cell are connected in series in the second string.

In at least one embodiment, the integrated circuit further includes a first terminal connected to the first contact and the third contact; a second terminal connected to the second contact; and a third terminal connected to the fourth contact.

In at least one embodiment, the semiconductor memory cells comprise substantially planar semiconductor memory cells.

In at least one embodiment, the semiconductor memory cells comprise fin-type, three-dimensional semiconductor memory cells.

In at least one embodiment, the first set of contactless semiconductor memory cells are aligned side-by side of the second set of contactless semiconductor memory cells; the first string comprises a first set of insulation portions that insulate adjacent memory cells in the first string, and a second set of insulation portions that insulate the memory cells in the first string from adjacent memory cells in the second string; and the second string comprises a third set of insulation portions that insulate adjacent memory cells in the second string, and a fourth set of insulation portions that insulate the memory cells in the second string from adjacent memory cells in the first string.

In at least one embodiment, the first and second contacts are located at first and second ends of the memory string.

In at least one embodiment, each semiconductor memory cell comprises: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating region; an insulating region insulating the gate from the floating body region; and a word line terminal electrically connected to the gate.

In another aspect of the present invention an integrated circuit includes a plurality of floating body memory cells which are linked either in series or in parallel. The connections between the memory cells are made to reduce the number of contacts for the overall circuit. Because several memory cells are connected either in series or in parallel, a compact memory array is provided.

These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the integrated circuits, strings, links memory cells and methods as more fully described below.

In one aspect of the present invention, a semiconductor memory cell includes: a substrate having a first conductivity type; a substrate terminal connected to the substrate; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; one of a bit line terminal and a source line terminal connected to the first region; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; the other of the bit line terminal and the source line terminal connected to the second region; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, wherein the first and second storage locations are each configured to receive transfer of data stored by the volatile memory; and a control gate positioned above the trapping layer.

›SUMMARY OF THE INVENTION · 4 of 6

In at least one embodiment, the surface comprises a top surface, the cell further comprising a buried layer at a bottom portion of the substrate, the buried layer having the second conductivity type; and a buried well terminal connected to the buried layer.

In at least one embodiment, the floating body is completely bounded by the top surface, the first and second regions and the buried layer.

In at least one embodiment, the first conductivity type is “p” type and the second conductivity type is “n” type.

In at least one embodiment, the semiconductor memory cell further comprises insulating layers bounding the side surfaces of the substrate.

In at least one embodiment, the cell functions as a multi-level cell.

In at least one embodiment, at least one of the first and second storage locations is configured so that more than one bit of data can be stored in the at least one of the first and second storage locations, respectively.

In at least one embodiment, the floating body is configured so that more than one bit of data can be stored therein.

In another aspect of the present invention, a method of operating a memory cell device having a plurality of memory cells each having a floating body for storing data as volatile memory, and a trapping layer having first and second storage locations for storing data as non-volatile memory is provided, including: operating the memory cell as a volatile memory cell when power is supplied to the memory cell; upon discontinuation of power to the memory cell, resetting non-volatile memory of the memory cell to a predetermined state; and performing a shadowing operation wherein content of the volatile memory cell is loaded into the non-volatile memory.

In at least one embodiment, the method further includes shutting down the memory cell device, wherein the memory cell device, upon the shutting down, operates as a flash, erasable, programmable read-only memory.

In at least one embodiment, the method further includes restoring power to the memory cell, wherein upon the restoring power, carrying out a restore process wherein content of the non-volatile memory is loaded into the volatile memory.

In another aspect of the present invention, a method of operating a memory cell device includes: providing a memory cell device having a plurality of memory cells, each the memory cell having a floating body for storing data as volatile memory and a trapping layer for storing data as non-volatile memory; and operating at least one of the memory cells as a volatile memory cell, independently of the non-volatile memory of the respective memory cell.

In at least one embodiment, the operating comprises applying a voltage to a region at a surface of the cell adjacent to a non-volatile storage location of the non-volatile memory.

In at least one embodiment, the applying a voltage comprises applying a positive voltage and the floating body of the cell has a p-type conductivity type.

In at least one embodiment, the operating comprises operating the volatile memory to perform at least one of a reading operation, a writing operation, and or a holding operation.

In at least one embodiment, the method further includes performing a reset operation to initialize a state of the non-volatile memory.

In at least one embodiment, the method further includes performing a shadowing operation to load a content of the volatile memory into the non-volatile memory.

In another aspect of the present invention, a semiconductor memory cell is provided that includes a floating body region for storing data as volatile memory; and a trapping layer for storing data as non-volatile memory; wherein the data stored as volatile memory and the data stored as non-volatile memory are independent of one another, as the floating body region can be operated independently of the trapping layer and the trapping layer can be operated independently of the floating body region.

In at least one embodiment, the floating body region has a first conductivity type and is bounded by a buried layer have a second conductivity type different from the first conductivity type.

In at least one embodiment, the first conductivity type is “p” type and the second conductivity type is “n” type.

In at least one embodiment, the floating body region is bounded by a buried insulator.

In at least one embodiment, the floating body region is formed in a substrate, the cell further comprises insulating layers bounding side surfaces of the substrate.

In at least one embodiment, the cell functions as a multi-level cell.

In at least one embodiment, the trapping layer comprises first and second storage locations, the first and second storage locations each being configured to store data independently of the other, as non-volatile memory.

In one aspect of the present invention, a single polysilicon floating gate semiconductor memory cell is provided that includes: a substrate; a floating body region exposed at a surface of the substrate and configured to store volatile memory; a single polysilicon floating gate configured to store nonvolatile data; an insulating region insulating the floating body region from the single polysilicon floating gate; and first and second regions exposed at the surface at locations other than where the floating body region is exposed; wherein the floating gate is configured to receive transfer of data stored by the volatile memory.

In at least one embodiment, the first and second regions are asymmetric, wherein a first area defines an area over which the first region is exposed at the surface and a second area defines an area over which the second region is exposed at the surface, and wherein the first area is unequal to the second area.

In at least one embodiment, one of the first and second regions at the surface has a higher coupling to the floating gate relative to coupling of the other of the first and second regions to the floating gate.

In at least one embodiment, the cell includes a buried layer at a bottom portion of the substrate, the buried layer having a conductivity type that is different from a conductivity type of the floating body region.

›SUMMARY OF THE INVENTION · 5 of 6

In at least one embodiment, the floating body is bounded by the surface, the first and second regions and the buried layer.

In at least one embodiment, insulating layers bound side surfaces of the substrate.

In at least one embodiment, a buried insulator layer is buried in a bottom portion of the substrate

In at least one embodiment, the floating body is bounded by the surface, the first and second regions and the buried insulator layer.

In at least one embodiment, the floating gate overlies an area of the floating body exposed at the surface, and a gap is located between the area overlaid and one of the first and second regions.

In at least one embodiment, a select gate is positioned adjacent to the single polysilicon floating gate.

In at least one embodiment, the select gate overlaps the floating gate.

In another aspect of the present invention, a semiconductor memory cell is provided that includes: a substrate; a floating body region configured to store volatile memory; a stacked gate nonvolatile memory comprising a floating gate adjacent the substrate and a control gate adjacent the floating gate such that the floating gate is positioned between the control gate and the substrate; and a select gate positioned adjacent the substrate and the floating gate.

In at least one embodiment, the floating body is exposed at a surface of the substrate, and the cell further includes: first and second regions each exposed at the surface at locations other than where the floating body region is exposed; wherein the first and second regions are asymmetric, wherein a first area defines an area over which the first region is exposed at the surface and a second area defines an area over which the second region is exposed at the surface, and wherein the first area is unequal to the second area.

In at least one embodiment, a buried layer is buried in a bottom portion of the substrate, the buried layer having a conductivity type different from a conductivity type of the floating body region.

In at least one embodiment, the floating body is bounded by the surface, the first and second regions and the buried layer.

In at least one embodiment, insulating layers bound side surfaces of the substrate.

In at least one embodiment, a buried insulator layer is buried in a bottom portion of the substrate.

In at least one embodiment, the floating body is bounded by the surface, the first and second regions and the buried insulator layer.

In another aspect of the present invention, a single polysilicon floating gate semiconductor memory cell is provided that includes: a substrate; a floating body region for storing data as volatile memory, and a single polysilicon floating gate for storing data as non-volatile memory; wherein the floating body region stores the data stored as volatile memory independently of the data stored as non-volatile memory, and the single polysilicon floating gate stores the data stored as volatile memory independently of the data stored as volatile memory.

In at least one embodiment, the floating body region has a first conductivity type and is bounded by a buried layer having a second conductivity type different from the first conductivity type.

In at least one embodiment, the floating body region is bounded a buried insulator.

In at least one embodiment, the first conductivity type is “p” type and the second conductivity type is “n” type.

In at least one embodiment, insulating layers bound side surfaces of the substrate.

In another aspect of the present invention, a method of operating a memory cell device having a plurality of memory cells each having a floating body for storing data as volatile memory, and a floating gate for storing data as non-volatile memory is provided, including: operating the memory cell as a volatile memory cell when power is supplied to the memory cell; upon discontinuation of power to the memory cell, resetting non-volatile memory of the memory cell to a predetermined state; and performing a shadowing operation wherein content of the volatile memory cell is loaded into the non-volatile memory.

In another aspect of the present invention, a method of operating a memory cell device includes: providing a memory cell device having a plurality of memory cells each having a floating body for storing data as volatile memory, a floating gate for storing data as non-volatile memory, and a control gate; and operating the memory cell as a volatile memory cell independent of the non-volatile memory data.

In at least one embodiment, the method further includes applying a voltage to the control gate to invert a channel region underneath the floating gate, regardless of charge stored in the floating gate.

In at least one embodiment, the method further includes applying a positive voltage to a region of the substrate coupled to the floating gate, and wherein the floating body has a “p” type conductivity type.

In at least one embodiment, the operation the memory cell as a volatile memory comprises performing at least one of reading, writing, and holding operations.

›SUMMARY OF THE INVENTION · 6 of 6

In at least one embodiment, the method further includes performing a reset operation to initialize a state of the non-volatile memory.

In at least one embodiment, the method further includes performing a shadowing operation to load content of the volatile memory into the non-volatile memory.

These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the methods, devices and arrays as more fully described below.

›BRIEF DESCRIPTION OF THE DRAWINGS · 1 of 7

FIG. 1 is a schematic illustration of a memory cell according to an embodiment of the present invention.

FIG. 2 schematically illustrates multiple cells joined in an array to make a memory device according to an embodiment of the present invention.

FIG. 3 schematically illustrates n-p-n bipolar devices that are inherently formed in a memory cell according to an embodiment of the present invention.

FIG. 4 A illustrates segmenting of substrate terminals in an array according to an embodiment of the present invention.

FIG. 4 B schematically illustrates multiplexers used to determine the biases applied to segmented substrate terminals according to an embodiment of the present invention.

FIG. 4 C schematically illustrates use of a voltage generator circuitries to input positive bias to the multiplexers according to an embodiment of the present invention.

FIG. 5 graphically illustrates that the maximum charge stored in a floating body of a memory cell can be increased by applying a positive bias to the substrate terminal according to an embodiment of the present invention.

FIG. 6 A graphs floating body potential as a function of floating body current and substrate potential according to an embodiment of the present invention.

FIG. 6 B graphs floating body potential as a function of floating body current and buried well potential according to an embodiment of the present invention.

FIG. 7 shows bias conditions for a selected memory cell and unselected memory cells in a memory array according to an embodiment of the present invention.

FIG. 8 A illustrates an unselected memory cell sharing the same row as a selected memory cell during a read operation of the selected memory cell according to an embodiment of the present invention.

FIG. 8 B illustrates the states of the n-p-n bipolar devices of the unselected memory cell of FIG. 8 A during the read operation of the selected memory cell according to the embodiment of FIG. 8 A .

FIG. 8 C illustrates an unselected memory cell sharing the same column as a selected memory cell during a read operation of the selected memory cell according to the embodiment of FIG. 8 A .

FIG. 8 D illustrates the states of the n-p-n bipolar devices of the unselected memory cell of FIG. 8 C during the read operation of the selected memory cell according to the embodiment of FIG. 8 A .

FIG. 8 E illustrates an unselected memory cell that shares neither the same row nor the same column as a selected memory cell during a read operation of the selected memory cell according to the embodiment of FIG. 8 A .

FIG. 8 F illustrates the states of the n-p-n bipolar devices of the unselected memory cell of FIG. 8 E during the read operation of the selected memory cell according to the embodiment of FIG. 8 A .

FIG. 9 is a schematic illustration of a write “0” operation to a memory cell according to an embodiment of the present invention.

FIG. 10 shows an example of bias conditions for a selected memory cell and unselected memory cells during a write “0” operation in a memory array according to an embodiment of the present invention.

FIG. 11 A illustrates an example of bias conditions on unselected memory cells during a write “0” operation according to an embodiment of the present invention.

FIG. 11 B shows an equivalent circuit diagram for the cell of FIG. 11 A illustrating the intrinsic n-p-n bipolar devices.

FIG. 12 shows bias conditions for selected and unselected memory cells of a memory array during a write “0” operation according to an embodiment of the present invention.

FIG. 13 A illustrates an example of bias conditions on a selected memory cell during a write “0” operation according to an embodiment of the present invention.

FIG. 13 B shows an equivalent circuit diagram for the cell of FIG. 13 A illustrating the intrinsic n-p-n bipolar devices.

FIG. 13 C illustrates an example of bias conditions on unselected memory cells sharing the same row as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment of FIG. 13 A .

FIG. 13 D shows an equivalent circuit diagram for the cell of FIG. 13 C illustrating the intrinsic n-p-n bipolar devices.

FIG. 13 E illustrates an example of bias conditions on unselected memory cells sharing the same column as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment of FIG. 13 A .

FIG. 13 F shows an equivalent circuit diagram for the cell of FIG. 13 E illustrating the intrinsic n-p-n bipolar devices.

FIG. 13 G illustrates an example of bias conditions on unselected memory cells that share neither the same row nor the same column as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment of FIG. 13 A .

FIG. 13 H shows an equivalent circuit diagram for the cell of FIG. 13 G illustrating the intrinsic n-p-n bipolar devices.

FIG. 14 illustrates an example of bias conditions of a selected memory cell and unselected memory cells in an array under a band-to-band tunneling write “1” operation of the selected cell according to an embodiment of the present invention.

FIG. 15 A illustrates an example of bias conditions on the selected memory cell of FIG. 14 .

FIG. 15 B shows an equivalent circuit diagram for the cell of FIG. 15 A illustrating the intrinsic n-p-n bipolar devices.

FIG. 15 C illustrates an example of bias conditions on unselected memory cells sharing the same row as a selected memory cell in an array during a write “1” operation of the selected memory cell, according to the embodiment of FIG. 15 A .

FIG. 15 D shows an equivalent circuit diagram for the cell of FIG. 15 C illustrating the intrinsic n-p-n bipolar devices.

FIG. 15 E illustrates an example of bias conditions on unselected memory cells sharing the same column as a selected memory cell in an array during a write “1” operation of the selected memory cell, according to the embodiment of FIG. 15 A .

FIG. 15 F shows an equivalent circuit diagram for the cell of FIG. 15 E illustrating the intrinsic n-p-n bipolar devices.

›BRIEF DESCRIPTION OF THE DRAWINGS · 2 of 7

FIG. 15 G illustrates an example of bias conditions on unselected memory cells that share neither the same row nor the same column as a selected memory cell in an array during a write “1” operation of the selected memory cell, according to the embodiment of FIG. 15 A .

FIG. 15 H shows an equivalent circuit diagram for the cell of FIG. 15 G illustrating the intrinsic n-p-n bipolar devices.

FIG. 16 A shows a reference generator circuit which serves to generate the initial cumulative cell current of the memory cells sharing the same source line being written, according to an embodiment of the present invention.

FIG. 16 B shows a reference generator circuit which serves to generate the initial cumulative cell current of the memory cells sharing the same source line being written, according to another embodiment of the present invention.

FIG. 16 C shows a reference generator circuit which serves to generate the initial cumulative cell current of the memory cells sharing the same source line being written, according to another embodiment of the present invention.

FIG. 17 graphically illustrates that the potential of the floating body of a memory cell will increase over time as bias conditions are applied that will result in hole injection to the floating body, according to an embodiment of the present invention.

FIG. 18 A schematically illustrates reference generator circuitry and read circuitry connected to a memory array according to an embodiment of the present invention.

FIG. 18 B shows a schematic of a voltage sensing circuitry configured to measure the voltage across the source line and the bit line terminals of a memory cell according to an embodiment of the present invention.

FIG. 19 illustrates bias conditions on a selected cell and unselected cells of an array during a read operation on the selected cell according to an embodiment of the present invention.

FIG. 20 illustrates bias conditions on a selected cell and unselected cells of an array during a write “0” operation on the selected cell according to an embodiment of the present invention.

FIG. 21 illustrates bias conditions on a selected cell and unselected cells of an array during a write “0” operation on the selected cell according to another embodiment of the present invention.

FIG. 22 illustrates bias conditions on a selected cell and unselected cells of an array during a band-to-band tunneling write “1” operation on the selected cell according to another embodiment of the present invention.

FIG. 23 A is a schematic illustration of a memory cell according to another embodiment of the present invention.

FIG. 23 B is a schematic illustration of a memory cell according to another embodiment of the present invention showing contacts to the buried well and substrate regions.

FIG. 24 schematically illustrates an array of memory cells of the type illustrated in FIGS. 23 A- 23 B .

FIG. 25 schematically illustrates n-p-n bipolar devices inherent in the cell of FIGS. 23 A- 23 B .

FIG. 26 illustrates an example of bias conditions on an array during performance of a read operation on a selected cell according to an embodiment of the present invention.

FIG. 27 illustrates bias conditions on a selected cell and unselected cells of an array during a write “0” operation on the selected cell according to an embodiment of the present invention.

FIG. 28 A illustrates an example of bias conditions on the selected memory cell of FIG. 27 .

FIG. 28 B shows an equivalent circuit diagram for the cell of FIG. 28 A illustrating the intrinsic n-p-n bipolar devices.

FIG. 28 C illustrates an example of bias conditions on unselected memory cells sharing the same row as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment of FIG. 27 .

FIG. 28 D shows an equivalent circuit diagram for the cell of FIG. 28 C illustrating the intrinsic n-p-n bipolar devices.

FIG. 28 E illustrates an example of bias conditions on unselected memory cells sharing the same column as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment of FIG. 27 .

FIG. 28 F shows an equivalent circuit diagram for the cell of FIG. 28 E illustrating the intrinsic n-p-n bipolar devices.

FIG. 28 G illustrates an example of bias conditions on unselected memory cells that share neither the same row nor the same column as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment of FIG. 27 .

FIG. 28 H shows an equivalent circuit diagram for the cell of FIG. 28 G illustrating the intrinsic n-p-n bipolar devices.

FIG. 29 illustrates an example of bias conditions applied to a selected memory cell under a band-to-band tunneling write “1” operation according to an embodiment of the present invention.

FIG. 30 is a schematic illustration of a memory cell according to another embodiment of the present invention.

FIG. 31 is a schematic illustration of a memory cell according to another embodiment of the present invention.

FIG. 32 is a schematic illustration of a memory cell according to another embodiment of the present invention.

FIG. 33 is a schematic illustration of a memory cell according to another embodiment of the present invention.

FIG. 34 is a top view, schematic illustration of a memory cell of FIGS. 30 and 32 .

FIGS. 35 A through 35 E illustrate an array and details of a first exemplary memory cell according to the present invention.

FIGS. 36 A through 36 U illustrate a method of manufacturing a memory cell according to the present invention.

FIGS. 37 A through 37 C illustrate a method of maintaining the state of a memory cell according to the present invention.

FIGS. 38 A through 38 D illustrate methods of maintaining the state of the data stored in an array of memory cells according to the present invention.

FIG. 39 is a graph of the floating body voltage in a memory cell according to the present invention.

FIG. 40 is a graph of current-voltage curves of a memory cell according to the present invention.

›BRIEF DESCRIPTION OF THE DRAWINGS · 3 of 7

FIG. 41 illustrates a read operation performed on an array of memory cells according to the present invention.

FIGS. 42 A through 42 H illustrate the operation of four representative memory cells of the array of FIG. 41 .

FIGS. 43 A and 43 B illustrates the operation of selected memory cells according to the present invention during a first type of write logic-0 operation.

FIG. 44 illustrates an array of memory cells according to the present invention during the first type of write logic-0 operation of FIG. 43 .

FIGS. 45 A- 45 B illustrate the operation of unselected memory cells according to the present invention of the array of FIG. 46 during a second type of write logic-0 operation.

FIG. 46 illustrates an array of memory cells according to the present invention during a second type of write logic-0 operation.

FIG. 47 illustrates an array of memory cells according to the present invention during a third type of write logic-0 operation.

FIGS. 48 A through 48 H illustrate the operation of four representative memory cells of the array of FIG. 47 during the third type of logic operation.

FIG. 49 illustrates an array of memory cells according to the present invention during a first type of write logic-1 operation.

FIGS. 50 A through 50 H illustrate the operation of four representative memory cells of the array of FIG. 15 during the first type of write logic-1 operation.

FIG. 51 illustrates an array of memory cells according to the present invention during a second type of write logic-1 operation.

FIGS. 52 A through 52 H illustrate the operation of four representative memory cells of the array of FIG. 51 during the second type of write logic-1 operation.

FIGS. 53 A through 53 E illustrate a second exemplary memory cell according to the present invention.

FIGS. 54 A through 54 H illustrate performing operations on an array of the memory cell of FIGS. 53 A through 53 E .

FIGS. 55 A through 55 F illustrate multilevel operations on a memory cell according to the present invention.

FIG. 56 illustrates an alternate memory cell according to the present invention.

FIG. 57 illustrates a top view of the memory cell of FIG. 56 .

FIG. 58 A illustrates another alternate memory cell according to the present invention.

FIG. 58 B illustrates an array of the memory cell of FIG. 58 A .

FIGS. 59 A through 59 F illustrate a third exemplary memory cell according to the present invention.

FIGS. 60 A through 60 F illustrate an alternate physical embodiment of the memory cell of FIGS. 59 A through 59 F .

FIG. 61 A illustrates an array of the memory cell of the embodiments of FIGS. 59 A through 59 F and FIGS. 60 A through 60 F .

FIG. 61 B illustrates a circuit schematic of an individual cell of the embodiments of FIGS. 59 A through 59 F and FIGS. 60 A through 60 F .

FIG. 62 illustrates a hold operation performed on the array of FIG. 61 A .

FIG. 63 illustrates a read operation performed on the array of FIG. 61 A .

FIGS. 64 A through 64 P illustrate the operation of eight representative memory cells of the array of FIG. 63 .

FIG. 65 illustrates a two row write logic-0 operation on the memory array of FIG. 61 A .

FIGS. 66 A and 66 B illustrate the operation of unselected memory cells in

FIG. 65 .

FIG. 67 illustrates a single column write logic-0 operation on the memory array of FIG. 61 A .

FIG. 68 illustrates a single memory cell write logic-0 operation on the memory array of FIG. 61 A .

FIGS. 69 A through 69 P illustrate the operation of eight representative memory cells of the array of FIG. 68 .

FIG. 70 illustrates a single memory cell write logic-1 operation on the memory array of FIG. 61 A .

FIGS. 71 A through 71 P illustrate the operation of eight representative memory cells of the array of FIG. 70 .

FIG. 72 illustrates an alternate single memory cell write logic-1 operation on the memory array of FIG. 61 A .

FIGS. 73 A through 73 B illustrates a possible write disturb condition resulting from the single memory cell write logic-1 operation of FIG. 72 .

FIG. 74 illustrates another alternate single memory cell write logic-1 operation on the memory array of FIG. 61 A .

FIGS. 75 A and 75 B illustrates additional alternate methods of manufacturing a memory cell according to the present invention.

FIGS. 76 A through 76 AA illustrate a method of manufacturing the memory cell of FIG. 75 B .

FIGS. 77 A through 77 F illustrate a fourth exemplary memory cell according to the present invention.

FIGS. 78 A and 78 B illustrate different holding operations on a memory array of the memory cells of FIGS. 77 A through 77 F .

FIGS. 79 and 80 A through 80 H illustrate a read operation on a memory array of the memory cells of FIGS. 77 A through 77 F .

FIG. 81 illustrates a single memory cell write logic-0 operation on the memory array of FIG. 77 F .

FIGS. 82 A through 82 B illustrate the operation of the unselected memory cells of the array of FIG. 81 .

FIG. 83 illustrates a single memory cell write logic-0 operation on the memory array of FIG. 77 F .

FIGS. 84 A through 84 H illustrate the operation of four representative memory cells of the array of FIG. 83 .

FIGS. 85 A through 85 F illustrate a fifth exemplary memory cell according to the present invention.

FIG. 86 illustrates the hold operation when using memory cells of the present invention in SCR mode.

FIG. 87 illustrates the single cell read operation when using memory cells of the present invention in SCR mode.

FIG. 88 illustrates the single cell write logic-1 operation when using memory cells of the present invention in SCR mode.

FIG. 89 illustrates the single cell write logic-0 operation when using memory cells of the present invention in SCR mode.

FIGS. 90 A through 90 C illustrate standard MOSFET transistors of the prior art.

FIG. 91 schematically illustrates a memory cell in accordance with an embodiment of the present invention.

FIG. 92 A schematically illustrates a memory array having a plurality of memory cells according to an embodiment of the present invention.

FIG. 92 B schematically illustrates a memory array having a plurality of memory cells, with read circuitry connected thereto that can be used to determine data states, according to an embodiment of the present invention

›BRIEF DESCRIPTION OF THE DRAWINGS · 4 of 7

FIG. 93 shows exemplary bias conditions for reading a selected memory cell, as wells as bias conditions of unselected memory cells in a memory array according to an embodiment of the present invention.

FIG. 94 A shows exemplary bias conditions for reading a selected memory cell according to an embodiment of the present invention.

FIGS. 94 B- 94 D illustrate bias conditions on unselected memory cells during the exemplary read operation described with regard to FIG. 93 , according to an embodiment of the present invention.

FIG. 95 schematically illustrates and example of a write “0” operation of a cell according to an embodiment of the present invention.

FIGS. 96 A- 96 B show an example of bias conditions of selected and unselected memory cells during a write “0” operation according to an embodiment of the present invention.

FIG. 97 illustrates bias conditions for cells in an array during a write “0” operation in which all memory cells sharing the same BL terminal are written into state “0” according to an embodiment of the present invention.

FIG. 98 illustrates bias conditions for selected and unselected memory cells of a memory array for a write “0” operation according to an alternative embodiment of the present invention.

FIG. 99 A illustrates bias conditions of the selected memory cell under the write “0” operation described with regard to the example of FIG. 98 .

FIGS. 99 B- 99 D illustrate examples of bias conditions on the unselected memory cells during write “0” operations described with regard to the example shown in FIG. 98 .

FIGS. 100 and 101 A illustrate an example of the bias conditions of a selected memory cell under a write “1” operation using band-to-band tunneling according to an embodiment of the present invention.

FIGS. 101 B- 101 D show examples of bias conditions of the unselected memory cells during write “1” operations of the type described with regard to FIG. 100 .

FIG. 102 schematically illustrates bias conditions on memory cells during a write “1” operation using impact ionization according to and embodiment of the present invention.

FIGS. 103 A- 103 D and 104 illustrate an example of the bias conditions of the selected memory cell 750 under a write “1” operation using an impact ionization write “1” operation according to an embodiment of the present invention.

FIG. 105 illustrates a prior art arrangement in which adjacent memory cells share common contacts.

FIG. 106 A shows a cross-sectional schematic illustration of a memory string according to an embodiment of the present invention.

FIG. 106 B shows a top view schematic illustration of a memory cell array including two strings of memory cells between the SL terminal and BL terminal according to an embodiment of the present invention.

FIG. 107 shows an equivalent circuit representation of the memory array of FIG. 106 B .

FIGS. 108 and 109 A- 109 B illustrate bias conditions during a read operation according to an embodiment of the present invention.

FIGS. 110 - 111 illustrate bias conditions during a write “0” operation according to an embodiment of the present invention.

FIGS. 112 A- 112 B illustrate bias conditions during a write “0” operation that allows for individual bit writing according to an embodiment of the present invention.

FIGS. 113 A- 113 B illustrate bias conditions during a band-to-band tunneling write “1” operation according to an embodiment of the present invention.

FIGS. 114 A- 114 B illustrate bias conditions during an impact ionization write “1” operation according to an embodiment of the present invention.

FIG. 115 A schematically illustrates a fin-type, three-dimensional memory cell according to an embodiment of the present invention.

FIG. 115 B schematically illustrates a fin-type, three-dimensional memory cell according to another embodiment of the present invention.

FIG. 116 A shows an energy band diagram of the intrinsic n-p-n bipolar device of the cell of FIG. 23 when the floating body region is positively charged and a positive bias voltage is applied to the buried well region according to an embodiment of the present invention.

FIG. 116 B shows an energy band diagram of the intrinsic n-p-n bipolar device of the cell of FIG. 23 when the floating body region 24 is neutrally charged and a bias voltage is applied to the buried well region according to an embodiment of the present invention.

FIG. 117 schematically illustrates bias conditions on memory cells during a read operation of a selected memory cell according to an embodiment of the present invention.

FIG. 118 schematically illustrates bias conditions on memory cells during a write “0” operation according to an embodiment of the present invention.

FIG. 119 schematically illustrates bias conditions on memory cells during a write “0” operation according to another embodiment of the present invention.

FIG. 120 A schematically illustrates an example of bias conditions of a selected memory cell under a band-to-band tunneling write “1” operation according to an embodiment of the present invention.

FIG. 120 B shows bias conditions of selected and unselected memory cells 150 during an impact ionization write “1” operation according to an embodiment of the present invention.

FIG. 121 A shows a cross-sectional schematic illustration of a memory string according to an embodiment of the present invention.

FIG. 121 B shows a top view schematic illustration of a memory cell array including two strings of memory cells between the SL terminal and BL terminal according to an embodiment of the present invention.

FIG. 121 C shows an equivalent circuit representation of a memory array that includes strings shown in FIG. 121 B as well as additional strings, in accordance with an embodiment of the present invention.

FIG. 122 shows bias conditions on a memory string during a read operation according to an embodiment of the present invention.

FIG. 123 A illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a read operation according to an embodiment of the present invention.

›BRIEF DESCRIPTION OF THE DRAWINGS · 5 of 7

FIG. 123 B illustrates the array of FIG. 123 A with read circuitry attached to measure or sense the current flow from the BL terminal to the SL terminal in regard to the selected cell, according to an embodiment of the present invention.

FIG. 124 shows bias conditions on a memory string during a write “0” operation according to an embodiment of the present invention.

FIG. 125 illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a write “0” operation according to an embodiment of the present invention.

FIG. 126 shows bias conditions on a memory string during a write “0” operation that allows for individual bit writing according to an embodiment of the present invention.

FIG. 127 illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a write “0” operation that allows for individual bit writing according to an embodiment of the present invention.

FIG. 128 shows bias conditions on a memory string during a band-to-band tunneling write “1” operation according to an embodiment of the present invention.

FIG. 129 illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a band-to-band tunneling write “1” operation according to an embodiment of the present invention.

FIG. 130 A shows bias conditions on a memory string during an impact ionization write “1” operation according to an embodiment of the present invention.

FIG. 130 B illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during an impact ionization write “1” operation according to an embodiment of the present invention.

FIG. 131 A schematically illustrates a top view of two strings of memory cells in a memory array according to an embodiment of the present invention.

FIG. 131 B is a cross-sectional view of a string from the array illustrated in FIG. 131 A .

FIGS. 132 A- 132 U illustrates various stages during manufacture of a memory array according to an embodiment of the present invention.

FIG. 133 schematically illustrates a link of memory cells connected in parallel according to an embodiment of the present invention.

FIG. 134 A schematically illustrates a top view of a memory cell of the link of FIG. 133 .

FIG. 134 B is a sectional view of the memory cell of FIG. 48 A taken along line I-I′ of FIG. 134 A .

FIG. 134 C is a sectional view of the memory cell of FIG. 48 A taken along line II-II′ of FIG. 134 A .

FIG. 135 shows an equivalent circuit representation of a memory array that includes the link of FIG. 133 , according to an embodiment of the present invention.

FIG. 136 is a schematic illustration of an equivalent circuit of a memory array of links in which a read operation is being performed on a selected memory cell of one of the links according to an embodiment of the present invention.

FIG. 137 schematically illustrates the selected memory cell of the array represented in FIG. 135 and bias conditions thereon during the read operation.

FIG. 138 is a schematic illustration of an equivalent circuit of a memory array in which a write “0” operation is being performed on a selected link of the array according to an embodiment of the present invention.

FIG. 139 schematically illustrates a memory cell of the link represented in FIG. 138 that is having a write “0” operation performed thereon according to an embodiment of the present invention.

FIG. 140 is a schematic illustration of an equivalent circuit of a memory array in which a write “0” operation is being performed according to an alternative embodiment of the present invention.

FIG. 141 schematically illustrates a memory cell of the array represented in FIG. 140 that is having a write “0” operation performed thereon according to the alternative embodiment described with regard to FIG. 140 .

FIG. 142 is a schematic illustration of an equivalent circuit of a memory array in which a write “1” operation is being performed by impact ionization according to an embodiment of the present invention.

FIG. 143 schematically illustrates a selected memory cell of the array of FIG. 142 on which the write “1” operation is being performed, and the bias conditions thereon.

FIG. 144 schematically illustrates a link according to another embodiment of the present invention.

FIG. 145 A schematically illustrates a top view of a memory cell of the memory array of FIG. 144 .

FIG. 145 B is a sectional view of the memory cell of FIG. 145 A taken along line I-I′ of FIG. 145 A .

FIG. 145 C is a sectional view of the memory cell of FIG. 145 A taken along line II-II′ of FIG. 145 A .

FIG. 146 shows an equivalent circuit representation of a memory array of links, including the link of FIG. 144 .

FIG. 147 is a schematic illustration of an equivalent circuit of a memory array in which a read operation is being performed on a selected memory cell according to an embodiment of the present invention.

FIG. 148 schematically illustrates the selected memory cell of the array represented in FIG. 147 and bias conditions thereon during the read operation.

FIG. 149 is a schematic illustration of an equivalent circuit of a memory array in which a write “0” operation is being performed according to an embodiment of the present invention.

FIG. 150 schematically illustrates a memory cell of the array represented in FIG. 149 that is having a write “0” operation performed thereon according to an embodiment of the present invention.

FIG. 151 is a schematic illustration of an equivalent circuit of a memory array in which a write “0” operation is being performed according to an alternative embodiment of the present invention that allows for individual bit writing.

FIG. 152 schematically illustrates a selected memory cell of the array represented in FIG. 151 that is being written to by the write “0” operation according to the alternative embodiment described with regard to FIG. 151 .

›BRIEF DESCRIPTION OF THE DRAWINGS · 6 of 7

FIG. 153 is a schematic illustration of an equivalent circuit of a memory array in which a write “1” operation is being performed by impact ionization according to an embodiment of the present invention.

FIG. 154 schematically illustrates a selected memory cell of the array of FIG. 153 on which the write “1” operation is being performed, and the bias conditions thereon.

FIG. 155 is a schematic illustration of an equivalent circuit of a memory array in which a write “1” operation is being performed by impact ionization according to an embodiment of the present invention.

FIG. 156 schematically illustrates a selected memory cell of the array of FIG. 155 on which the write “1” operation is being performed, and the bias conditions thereon.

FIG. 157 shows a memory array where adjacent regions are connected a common BL terminal through a conductive region according to an alternative embodiment of the present invention.

FIG. 158 A shows a memory array according to another embodiment of the present invention.

FIG. 158 B shows, in isolation, a memory cell from the memory array of FIG. 158 A .

FIGS. 158 C and 158 D show sectional views of the memory cell of FIG. 158 B taken along lines I-I′ and II-II′ of FIG. 158 B , respectively.

FIG. 159 is an equivalent circuit representation of a memory array of the type shown in FIG. 158 A according to an embodiment of the present invention.

FIG. 160 A shows an equivalent circuit representation of the memory cell of FIGS. 158 B- 158 D according to an embodiment of the present invention.

FIG. 160 B shows an energy band diagram of the intrinsic n-p-n bipolar device of FIG. 160 A when the floating body region is positively charged and a positive bias voltage is applied to the buried well region, according to an embodiment of the present invention.

FIG. 160 C shows an energy band diagram of the intrinsic n-p-n bipolar device 30 of FIG. 160 A when the floating body region is neutrally charged and a bias voltage is applied to the buried well region, according to an embodiment of the present invention.

FIG. 161 is a schematic illustration of a memory array in which a read operation is being performed on a selected memory cell according to an embodiment of the present invention.

FIG. 162 is a schematic illustration of the selected memory cell in FIG. 161 that is being read, and bias conditions thereon during the read operation.

FIG. 163 is a schematic illustration of a memory array in which a write “0” operation is being performed according to an embodiment of the present invention.

FIG. 164 schematically illustrates a memory cell of the array represented in FIG. 163 that is having a write “0” operation performed thereon according to an embodiment of the present invention.

FIG. 165 is a schematic illustration of a memory array in which a write “0” operation is being performed according to an alternative embodiment of the present invention.

FIG. 166 schematically illustrates a memory cell of the array represented in FIG. 165 that is having a write “0” operation performed thereon according to the alternative embodiment described with regard to FIG. 165 .

FIG. 167 is a schematic illustration of a memory array in which a write “1” operation is being performed by band-to-band tunneling according to an embodiment of the present invention.

FIG. 168 schematically illustrates a selected memory cell of the array of FIG. 167 on which the write “1” operation is being performed, and the bias conditions thereon.

FIG. 169 is a schematic illustration of a memory array in which a write “1” operation is being performed by impact ionization according to an embodiment of the present invention.

FIG. 170 schematically illustrates a selected memory cell of the array of FIG. 169 on which the write “1” operation is being performed, and the bias conditions thereon.

FIG. 171 is a flow chart illustrating the operation of a memory cell according to an embodiment of the present invention.

FIG. 172 is a flow chart illustrating operation of a memory cell according to another embodiment of the present invention.

FIG. 173 A is a cross-section, schematic illustration of a memory cell according to an embodiment of the present invention.

FIG. 173 B shows an exemplary array of memory cells arranged in rows and columns according to an embodiment of the present invention.

FIG. 173 C shows an array architecture of a memory cell device according to another embodiment of the present invention.

FIG. 174 illustrates an operating condition for a write state “1” operation that can be carried out on a memory cell according to an embodiment of the present invention.

FIG. 175 illustrates an operating condition for a write state “0” operation that can be carried out on a memory cell according to an embodiment of the present invention.

FIG. 176 illustrates a read operation that can be carried out on a memory cell according to an embodiment of the present invention

FIG. 177 illustrates a holding or refresh operation that can be carried out on a memory cell according to an embodiment of the present invention

FIGS. 178 A- 178 B illustrate shadowing operations that can be carried out according to an embodiment of the present invention.

FIGS. 179 A- 179 B illustrate restore operations that can be carried out according to an embodiment of the present invention.

FIG. 180 illustrates resetting the trapping layer(s) of a memory cell to a predetermined state, according to an embodiment of the present invention.

FIG. 181 A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 181 B shows an array architecture of a memory cell device according to an embodiment of the present invention.

FIGS. 182 - 183 illustrate cross-sectional schematic illustrations of fin-type semiconductor memory cell devices according to embodiments of the present invention

FIG. 184 illustrates a top view of a fin-type semiconductor memory cell device according to the embodiment shown in FIG. 182 .

FIG. 185 A illustrates states of a bi-level memory cell.

›BRIEF DESCRIPTION OF THE DRAWINGS · 7 of 7

FIG. 185 B illustrates states of a multi-level memory cell.

FIGS. 186 A through 186 E illustrate an array and details of a first exemplary memory cell according to the present invention.

FIG. 187 is a flowchart illustrating operation of a memory device according to the present invention.

FIG. 188 illustrates a holding operation performed on an array of memory cells according to the present invention.

FIGS. 189 A and 189 B illustrate the energy band diagram of a memory device according to the present invention during holding operation.

FIGS. 190 A and 190 B illustrate read operations performed on an array of memory cells according to the present invention.

FIGS. 191 A and 191 B illustrate write logic-0 operations performed on an array of memory cells according to the present invention.

FIGS. 192 A and 192 B illustrate write logic-1 operations performed on an array of memory cells according to the present invention.

FIGS. 193 A through 193 C illustrate a shadowing operation performed on an array of memory cells according to the present invention.

FIGS. 194 A through 194 C illustrate a restore operation performed on an array of memory cells according to the present invention.

FIG. 195 illustrates a reset operation performed on an array of memory cells according to the present invention.

FIGS. 196 A through 196 R illustrate a method of manufacturing a memory cell according to the present invention.

FIGS. 197 A through 197 R illustrate an alternative method of manufacturing a memory cell according to the present invention.

FIG. 198 illustrates a cross-sectional view of an alternative memory device according to the present invention.

FIGS. 199 A and 199 B illustrate a shadowing operation performed on an array of memory cells according to the present invention.

FIGS. 200 A through 200 C illustrate a restore operation performed on an array of memory cells according to the present invention.

FIG. 201 illustrates a reset operation performed on an array of memory cells according to the present invention.

FIGS. 202 A and 202 B illustrate cross-sectional views of alternative memory devices according to the present invention.

FIG. 203 illustrates an equivalent circuit representation of memory devices shown in FIGS. 202 A and 202 B .

FIG. 204 illustrates an exemplary array of memory devices according to the present invention.

FIG. 205 illustrates a holding operation performed on an array of memory cells according to the present invention.

FIG. 206 illustrates a read operation performed on an array of memory cells according to the present invention.

FIGS. 207 A through 207 C illustrate write logic-0 operations performed on an array of memory cells according to the present invention.

FIGS. 208 A and 208 B illustrate write logic-1 operations performed on an array of memory cells according to the present invention.

FIGS. 209 , 210 A through 210 B illustrate a shadowing operation performed on an array of memory cells according to the present invention.

FIGS. 211 , 212 A through 212 B illustrate a restore operation performed on an array of memory cells according to the present invention.

FIGS. 213 A and 213 B illustrate reset operations performed on an array of memory cells according to the present invention.

FIGS. 214 and 215 A- 215 B illustrate cross-sectional views of alternative memory devices according to the present invention.

FIG. 216 illustrates an equivalent circuit representation of memory devices shown in FIGS. 215 A- 215 B .

FIG. 217 illustrates an exemplary array of memory devices according to the present invention.

FIG. 218 illustrates a holding operation performed on an array of memory cells according to the present invention.

FIG. 219 illustrates a read operation performed on an array of memory cells according to the present invention.

FIGS. 220 A, 220 B, and 221 illustrate write logic-0 operations performed on an array of memory cells according to the present invention.

FIGS. 222 A and 222 B illustrate write logic-1 operations performed on an array of memory cells according to the present invention.

FIGS. 223 A and 223 B illustrate a shadowing operation performed on an array of memory cells according to the present invention.

FIG. 224 illustrates a restore operation performed on an array of memory cells according to the present invention.

FIGS. 225 A and 225 B illustrate reset operations performed on an array of memory cells according to the present invention.

FIG. 226 is a flowchart illustrating an alternative operation of a memory device according to the present invention.

FIG. 227 illustrates a read operation performed on an array of memory cells according to the present invention.

FIG. 228 illustrates a write logic-1 operation performed on an array of memory cells according to the present invention.

FIGS. 229 A through 229 C illustrate cross sectional views of alternative memory devices according to the present invention, fabricated on silicon-on-insulator (SOI) substrate.

FIGS. 230 A through 230 E illustrate cross-sectional views and top view of alternative memory devices according to the present invention, comprising of fin structures.

›DETAILED DESCRIPTION OF THE INVENTION

Before the present systems, devices and methods are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.

It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a cell” includes a plurality of such cells and reference to “the terminal” includes reference to one or more terminals and equivalents thereof known to those skilled in the art, and so forth.

The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.

›Definitions

A “holding operation”, “standby operation” or “holding/standby operation”, as used herein, refers to a process of sustaining a state of a memory cell by maintaining the stored charge. Maintenance of the stored charge may be facilitated by applying a back bias to the cell in a manner described herein.

A “a multi-level write operation” refers to a process that includes an ability to write more than more than two different states into a memory cell to store more than one bit per cell.

A “write-then-verify” “write and verify” or “alternating write and verify” algorithm or operation refers to a process where alternating write and read operations to a memory cell are employed to verify whether a desired memory state of the memory cell has been achieved during the write operation.

A “read verify operation” refers to a process where a read operation is performed to verify whether a desired memory state of a memory cell has been achieved.

A “read while programming” operation refers to a process where simultaneous write and read operations can be performed to write a memory cell state.

A “back bias terminal” refers to a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor. A back bias terminal is also commonly referred to as a “back gate terminal”. Herein, the back bias terminal refers to the substrate terminal or the buried well terminal, depending upon the embodiment being described.

The term “back bias” refers to a voltage applied to a back bias terminal.

A “memory cell” as used herein, refers to a semiconductor memory cell comprising an electrically floating body as the data storage element.

A “contactless memory cell” as used herein, refers to a memory cell which does not have a contact (or contacts) forming a direct connection(s) to a control line (or control lines). Contactless memory cells are typically connected in series when formed in a string or in parallel when formed in a link.

A “memory string” or “string” as used herein, refers to a set of interconnected memory cells connected in series, where conductive regions at the surfaces of adjacent memory cells are shared or electrically connected. In a series connection, the same current flows through each of the memory cells.

A “link” as used herein, refers to a set of interconnected memory cells connected in parallel, where conductive regions at the surfaces of adjacent memory cells are electrically connected. In a parallel connection, the voltage drop across each of the memory cells is the same.

A “memory array” or “memory cell array” as used herein, refers to a plurality of memory cells typically arranged in rows and columns. The plurality of memory cells may further be connected in strings or links within the memory array.

The terms “shadowing” “shadowing operation” and “shadowing process” refer to a process of copying the contents of volatile memory to non-volatile memory.

“Restore”, “restore operation”, or “restore process”, as used herein, refers to a process of copying the contents of non-volatile memory to volatile memory.

“Reset”, “reset operation”, or “reset process”, as used herein, refers to a process of setting non-volatile memory to a predetermined state.

“Permanent data” as used herein, is referred to data that typically will not be changed during the operation of a system employing a memory cell device as described herein, and thus can be stored indefinitely in non-volatile memory. Examples of such “permanent data” include, but are not limited to program files, application files, music files, video files, operating systems, etc.

The term “single polysilicon” flash memory refers to a non-volatile memory cell that has only one polysilicon gate, for example where the polysilicon is a floating gate used to store non-volatile data. As a result, single polysilicon flash memory is compatible with typical complementary metal oxide semiconductor (CMOS) processes. The polysilicon materials can be deposited and formed in conjunction with the gates of logic transistors.

The term “stacked gate” flash memory refers to a non-volatile memory cell that has multiple polysilicon layers/gates, for example where a second polysilicon gate (e.g., a control gate) is stacked above a polysilicon floating gate used to store the non-volatile data (see for example FIG. 4.6 on p. 197 in “Nonvolatile Semiconductor Memory Technology”, W. D. Brown and J. E. Brewer “Brown”), which is hereby incorporated herein, in its entirety, by reference thereto. Such stacked gate memory cells typically require dual (or more) polysilicon layer processing, where the first polysilicon layer (e.g. floating gate) is deposited and formed, followed by the formation of a second polysilicon (e.g. control gate) layer.

›DETAILED DESCRIPTION · 1 of 64

Referring now to FIG. 1 , a memory cell 50 according to an embodiment of the present invention is shown. The cell 50 includes a substrate 12 of a first conductivity type, such as n-type conductivity type, for example. Substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. The substrate 12 has a surface 14 . A first region 16 having a first conductivity type, such as n-type, for example, is provided in substrate 12 and which is exposed at surface 14 . A second region 18 having the first conductivity type is also provided in substrate 12 , which is exposed at surface 14 and which is spaced apart from the first region 16 . First and second regions 16 and 18 are formed by an implantation process formed on the material making up substrate 12 , according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process can be used to form first and second regions 16 and 18 .

A floating body region 24 having a second conductivity type different from the first conductivity type, such as p-type conductivity type when the first conductivity type is n-type conductivity type, is bounded by surface 14 , first and second regions 16 , 18 , insulating layers 26 , and substrate 12 . The floating body region 24 can be formed by an implantation process formed on the material making up substrate 12 , or can be grown epitaxially. Insulating layers 26 (e.g. shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulating layers 26 insulate cell 50 from neighboring cells 50 when multiple cells 50 are joined in an array 80 to make a memory device as illustrated in FIG. 2 . A gate 60 is positioned in between the regions 16 and 18 , and above the surface 14 . The gate 60 is insulated from surface 14 by an insulating layer 62 . Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Cell 50 further includes word line (WL) terminal 70 electrically connected to gate 60 , source line (SL) terminal 72 electrically connected to one of regions 16 and 18 (connected to 16 as shown, but could, alternatively, be connected to 18 ), bit line (BL) terminal 74 electrically connected to the other of regions 16 and 18 (connected to 18 as shown, but could, alternatively, be connected to 16 when 72 is connected to 18 ), and substrate terminal 78 electrically connected to substrate 12 . Alternatively, contact to substrate region 12 could be made through a region having a first conductivity type, which is electrically connected to substrate region 12 (not shown).

In another embodiment, the memory cell 50 has a p-type conductivity type as the first conductivity type and n-type conductivity type as the second conductivity type, as noted above.

The operation of a memory cell 50 has been described for example in “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-cost eDRAM Applications”, R. Ranica, et al., pp. 38-41, Tech. Digest, Symposium on VLSI Technology, 2005, which is hereby incorporated herein, in its entirety, by reference thereto. The memory cell states are represented by the charge in the floating body 24 . If cell 50 has holes stored in the floating body region 24 , then the memory cell 50 will have a lower threshold voltage (gate voltage where transistor is turned on) compared to when cell 50 does not store holes in floating body region 24 .

The positive charge stored in the floating body region 24 will decrease over time due to the p-n diode leakage formed by floating body 24 and regions 16 , 18 , and substrate 12 and due to charge recombination. A unique capability of the invention is the ability to perform the holding operation in parallel to all memory cells 50 of the array 80 . The holding operation can be performed by applying a positive back bias to the substrate terminal 78 while grounding terminal 72 and/or terminal 74 . The positive back bias applied to the substrate terminal will maintain the state of the memory cells 50 that it is connected to. The holding operation is relatively independent of the voltage applied to terminal 70 . As shown in FIG. 3 , inherent in the memory cell 50 are n-p-n bipolar devices 30 a and 30 b formed by substrate region 12 , floating body 24 , and SL and BL regions 16 , 18 . If floating body 24 is positively charged (i.e. in a state “1”), the bipolar transistor 30 a formed by SL region 16 , floating body 24 , and substrate region 12 and bipolar transistor 30 b formed by BL region 18 , floating body 24 , and substrate region 12 will be turned on.

A fraction of the bipolar transistor current will then flow into floating region 24 (usually referred to as the base current) and maintain the state “1” data. The efficiency of the holding operation can be enhanced by designing the bipolar device formed by substrate 12 , floating region 24 , and regions 16 , 18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of substrate terminal 78 to the base current flowing into the floating region 24 .

For memory cells in state “0” data, the bipolar devices 30 a , 30 b will not be turned on, and consequently no base hole current will flow into floating region 24 . Therefore, memory cells in state “0” will remain in state “0”.

As can be seen, the holding operation can be performed in mass, parallel manner as the substrate terminal 78 (e.g., 78 a , 78 b , . . . , 78 n ) is typically shared by all the cells 50 in the memory array 80 . The substrate terminal 78 can also be segmented to allow independent control of the applied bias on the selected portion of the memory array as shown in FIG. 4 A , where substrate terminal 78 a , 78 b is shown segmented from substrate terminal 78 m , 78 n , for example. Also, because substrate terminal 78 is not used for memory address selection, no memory cell access interruption occurs due to the holding operation.

›DETAILED DESCRIPTION · 2 of 64

In another embodiment, a periodic pulse of positive voltage can be applied to substrate terminal 78 , as opposed to applying a constant positive bias, in order to reduce the power consumption of the memory cell 50 . The state of the memory cell 50 can be maintained by refreshing the charge stored in floating body 24 during the period over which the positive voltage pulse is applied to the back bias terminal (i.e., substrate terminal 78 ). FIG. 4 B further shows multiplexers 40 that determine the bias applied to substrate terminal 78 where the control signal could be the clock signal 42 or as will be described later, determined by different operating modes. The positive input signals could be the power supply voltage Vcc ( FIG. 4 B ) or a different positive bias could be generated by voltage generator circuitry 44 (see FIG. 4 C ).

The holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floating body 24 . Without the holding/standby operation, the maximum potential that can be stored in the floating body 24 is limited to the flat band voltage V FB as the junction leakage current to regions 16 and 18 increases exponentially at floating body potential greater than V FB . However, by applying a positive voltage to substrate terminal 78 , the bipolar action results in a hole current flowing into the floating body 24 , compensating for the junction leakage current between floating body 24 and regions 16 and 18 . As a result, the maximum charge V MC stored in floating body 24 can be increased by applying a positive bias to the substrate terminal 78 as shown in FIG. 5 . The increase in the maximum charge stored in the floating body 24 results in a larger memory window.

The holding/standby operation can also be used for multi-bit operations in memory cell 50 . To increase the memory density without increasing the area occupied by the memory cell 50 , a multi-level operation is typically used. This is done by dividing the overall memory window into different levels. In floating body memory, the different memory states are represented by different charges in the floating body 24 , as described for example in “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 and U.S. Pat. No. 7,542,345 “Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same”, each of which is hereby incorporated herein, in its entirety, by reference thereto. However, since the state with zero charge in the floating body 24 is the most stable state, the floating body 24 will, over time, lose its charge until it reaches the most stable state. In multi-level operations, the difference of charge representing different states is smaller than that for a single-level operation. As a result, a multi-level memory cell is more sensitive to charge loss, as less charge loss is required to change states.

FIG. 6 shows the floating body 24 relative net current for different floating body 24 potentials as a function of the voltage applied to substrate terminal 78 with BL, SL, and WL terminals 72 , 74 , and 70 , grounded. When zero voltage is applied to substrate terminal 78 , no bipolar current is flowing into the floating body 24 and as a result, the stored charge will leak over time. When a positive voltage is applied to substrate terminal 78 , hole current will flow into floating body 24 and balance the junction leakage current to regions 16 and 18 . The junction leakage current is determined by the potential difference between the floating body 24 and regions 16 and 18 , while the bipolar current flowing into floating body 24 is determined by both the substrate terminal 78 potential and the floating body 24 potential. As indicated in FIG. 6 , for different floating body potentials, at a certain substrate terminal 78 potential V HOLD , the current flowing into floating body 24 is balanced by the junction leakage between floating body 24 and regions 16 and 18 . The different floating body 24 potentials represent different charges used to represent different states of memory cell 50 . This shows that different memory states can be maintained by using the holding/standby operation described here.

An example of the bias condition for the holding operation is hereby provided: zero voltage is applied to BL terminal 74 , zero voltage is applied to SL terminal 72 , zero or negative voltage is applied to WL terminal 70 , and a positive voltage is applied to the substrate terminal 78 . In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 74 , about 0.0 volts is applied to terminal 70 , and about +1.2 volts is applied to terminal 78 . However, these voltage levels may vary.

The charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 50 . If cell 50 is in a state “1” having holes in the floating body region 24 , then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current, compared to if cell 50 is in a state “0” having no holes in floating body region 24 . A sensing circuit/read circuitry 90 typically connected to BL terminal 74 of memory array 80 (e.g., see read circuitry 90 in FIG. 18 A ) can then be used to determine the data state of the memory cell. Examples of the read operation is described in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, and Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003 and U.S. Pat. No. 7,301,803 “Bipolar reading technique for a memory cell having an electrically floating body transistor”, both of which are hereby incorporated herein, in their entireties, by reference thereto. An example of a sensing circuit is described in “An 18.5 ns 128 Mb SOI DRAM with a Floating body Cell”, Ohsawa et al., pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005, which is hereby incorporated herein, in its entirety, by reference thereto.

›DETAILED DESCRIPTION · 3 of 64

The read operation can be performed by applying the following bias condition: a positive voltage is applied to the substrate terminal 78 , zero voltage is applied to SL terminal 72 , a positive voltage is applied to the selected BL terminal 74 , and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70 . The unselected BL terminals will remain at zero voltage and the unselected WL terminals will remain at zero or negative voltage. In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72 , about +0.4 volts is applied to the selected terminal 74 , about +1.2 volts is applied to the selected terminal 70 , and about +1.2 volts is applied to terminal 78 . The unselected terminals 74 remain at 0.0 volts and the unselected terminals 70 remain at 0.0 volts. FIG. 7 shows the bias conditions for the selected memory cell 50 a and unselected memory cells 50 b , 50 c , and 50 d in memory array 80 . However, these voltage levels may vary.

The unselected memory cells 50 during read operations are shown in FIGS. 8 A, 8 C and 8 E , with illustration of the states of the n-p-n bipolar devices 30 a , 30 b inherent in the cells 50 of FIGS. 8 A, 8 C and 8 E in FIGS. 8 B, 8 D and 8 F , respectively. The bias conditions for memory cells 50 sharing the same row (e.g. memory cell 50 b ) and those sharing the same column (e.g. memory cell 50 c ) as the selected memory cell 50 a are shown in FIGS. 8 A- 8 B and FIGS. 8 C- 8 D , respectively, while the bias condition for memory cells 50 not sharing the same row or the same column as the selected memory cell 50 (e.g. memory cell 50 d ) is shown in FIGS. 8 E- 8 F .

For memory cells 50 sharing the same row as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts ( FIGS. 8 A- 8 B ). As can be seen, these cells will be at holding mode, with memory cells in state “1” and will maintain the charge in floating body 24 because the intrinsic n-p-n bipolar devices 30 a , 30 b will generate hole current to replenish the charge in floating body 24 ; while memory cells 50 in state “0” will remain in the neutral state.

For memory cells 50 sharing the same column as the selected memory cell, a positive voltage is applied to the BL terminal 74 ( FIGS. 8 C- 8 D ). However, the n-p-n bipolar device 30 a formed by substrate 12 , floating body 24 , and region 16 will still maintain the state of the floating body 24 as the SL terminal 72 connected to region 16 is grounded.

For memory cells 50 not sharing the same row or the same column as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts ( FIGS. 8 E- 8 F ). As can be seen, these cells will be at holding mode, where memory cells in state “1” will maintain the charge in floating body 24 because the intrinsic n-p-n bipolar devices 30 a , 30 b will generate holes current to replenish the charge in floating body 24 ; while memory cells in state “0” will remain in the neutral state.

From the above description, it can be seen that the holding operation does not interrupt the read operation of the memory cells 50 . At the same time, the unselected memory cells 50 during a read operation will remain in a holding operation.

Write operations of memory cell 50 are now described. A write “0” operation of the cell 50 is described with reference to FIG. 9 . To write “0” to cell 50 , a negative bias is applied to SL terminal 72 , zero or negative voltage is applied to WL terminal 70 , and zero or positive voltage is applied to substrate terminal 78 . The SL terminal 72 for the unselected cells will remain grounded. Under these conditions, the p-n junction between 24 and 16 is forward-biased, evacuating any holes from the floating body 24 . In one particular non-limiting embodiment, about −2.0 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 70 , and about +1.2 volts is applied to terminal 78 . However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.

FIG. 10 shows an example of bias conditions for the selected and unselected memory cells 50 during a write “0” operation in memory array 80 . For the selected memory cells, the negative bias applied to SL terminal 72 causes large potential difference between floating body 24 and region 16 . Even for memory cells having a positively charged floating body 24 , the hole current generated by the intrinsic n-p-n bipolar devices 30 a , 30 b will not be sufficient to compensate for the forward bias current of p-n diode formed by floating body 24 and junction 16 .

An example of bias conditions and an equivalent circuit diagram illustrating the intrinsic n-p-n bipolar devices 30 a , 30 b of unselected memory cells 50 during write “0” operations are illustrated in FIGS. 11 A- 11 B . Since the write “0” operation only involves applying a negative voltage to the SL terminal 72 , the bias conditions for all the unselected cells are the same. As can be seen, the unselected memory cells will be in a holding operation, with both BL and SL terminals at about 0.0 volts. The positive back bias applied to the substrate terminal 78 employed for the holding operation does not interrupt the write “0” operation of the selected memory cells. Furthermore, the unselected memory cells remain in the holding operation.

The write “0” operation referred to above has a drawback in that all memory cells 50 sharing the same SL terminal will be written to simultaneously and as a result, this does not allow individual bit writing, i.e., writing to a single cell 50 memory bit. To write multiple data to different memory cells 50 , write “0” is first performed on all the memory cells, followed by write “1” operations on a selected bit or selected bits.

An alternative write “0” operation that allows for individual bit writing can be performed by applying a positive voltage to WL terminal 70 , a negative voltage to BL terminal 74 , zero or positive voltage to SL terminal 72 , and zero or positive voltage to substrate terminal 78 . Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70 . As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74 , the p-n junction between 24 and 18 is forward-biased, evacuating any holes from the floating body 24 . To reduce undesired write “0” disturb to other memory cells 50 in the memory array 80 , the applied potential can be optimized as follows: if the floating body 24 potential of state “1” is referred to as V FB1 , then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V FB1 /2 while −V FB1 /2 is applied to BL terminal 74 . A positive voltage can be applied to SL terminal 72 to further reduce the undesired write “0” disturb on other memory cells 50 in the memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74 .

›DETAILED DESCRIPTION · 4 of 64

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 50 a : a potential of about 0.0 volts is applied to terminal 72 , a potential of about −0.2 volts is applied to terminal 74 , a potential of about +0.5 volts is applied to terminal 70 , and about +1.2 volts is applied to terminal 78 ; while about 0.0 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 74 , about 0.0 volts is applied to terminal 70 , and about +1.2 volts is applied to terminal 78 of the unselected memory cells. FIG. 12 shows the bias conditions for the selected and unselected memory cells in memory array 80 . However, these voltage levels may vary.

The bias conditions of the selected memory cell 50 a under write “0” operation are further elaborated and are shown in FIGS. 13 A- 13 B . As discussed, the potential difference between floating body 24 and junction 18 (connected to BL terminal 74 ) is now increased, resulting in a higher forward bias current than the base hole current generated by the n-p-n bipolar devices 30 a , 30 b formed by substrate 12 , floating body 24 , and regions 16 and 18 . The net result is that holes will be evacuated from floating body 24 .

The unselected memory cells 50 during write “0” operations are shown in FIGS. 13 C- 13 H . The bias conditions for memory cells sharing the same row (e.g. memory cell 50 b ) are illustrated in FIGS. 13 C- 13 D , and the bias conditions for memory cells sharing the same column (e.g. memory cell 50 c ) as the selected memory cell 50 a are shown in FIGS. 13 E- 13 F , while the bias conditions for memory cells not sharing the same row or the same column (e.g. memory cell 50 d ) as the selected memory cell 50 are shown in FIGS. 13 G- 13 H .

For memory cells sharing the same row as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts ( FIGS. 13 C and 13 D ). The floating body 24 potential of these cells will also increase due to capacitive coupling from the WL terminal 70 . For memory cells in state “1”, the increase in the floating body 24 potential is not sustainable as the forward bias current of the p-n diodes formed by floating body 24 and junctions 16 and 18 is greater than the base hole current generated by the n-p-n bipolar device 30 formed by substrate 12 , floating body 24 , and junctions 16 and 18 . As a result, the floating body 24 potential will return to the initial state “1” equilibrium potential. For memory cells in state “0”, if the increase in floating body 24 potential is sufficiently high (i.e., at least V FB /3, see below), then both n-p-n bipolar devices 30 a and 30 b are turned on, and as a result the floating body 24 reaches a new equilibrium potential, between that of state “0” and state “1”. Therefore, the WL potential needs to be optimized so that the n-p-n bipolar devices 30 a , 30 b will not be turned on or that the base hole current is low enough that it does not result in an increase of the floating body 24 potential over the time during which the write operation is carried out (write operation time). It has been determined by the present inventor that a floating body 24 potential increase of V FB /3 is low enough to suppress the floating body 24 potential increase.

Accordingly, with careful design concerning the voltage applied to WL terminal 70 , the states of the unselected memory cells sharing the same WL terminal (i.e. the same row) as the selected memory cells will be maintained.

For memory cells sharing the same column as the selected memory cell, a negative voltage is applied to the BL terminal 74 (see FIGS. 13 E and 13 F ), resulting in an increase in the potential difference between floating body 24 and region 18 connected to BL terminal 74 . As a result a higher forward bias current between floating body 24 and junction 18 occurs. For memory cells in state “0”, the potential difference between floating body 24 and junction 18 is still sufficiently low that the p-n diode formed by floating body 24 and junction 18 is still not forward biased. Thus those memory cells will remain in state “0”. For memory cells in state “1”, junction leakage caused by forward bias current will increase. However, the hole current of the n-p-n bipolar device 30 b formed by substrate 12 , floating body 24 , and region 18 will also increase as a result of the increase in potential difference between the substrate 12 and region 18 (the collector and emitter terminals, respectively). Hence, the floating body 24 of memory cells in state “1” will also remain positively charged (i.e., in state “1”).

As to memory cells not sharing the same row or the same column as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (see FIGS. 13 G and 13 H ). These cells will thus be in a holding mode and continue a holding operation, with memory cells in state “1” maintaining the charge in floating body 24 because the intrinsic n-p-n bipolar device 30 will generate hole current to replenish the charge in floating body 24 ; while memory cells in state “0” will remain in the neutral state.

Accordingly, the present invention provides for a write “0” operation that allows for bit selection. The positive bias applied to the substrate terminal 78 of the memory cells 50 is necessary to maintain the states of the unselected cells 50 , especially those sharing the same row and column as the selected cells 50 , as the bias conditions can potentially alter the states of the memory cells 50 without the intrinsic bipolar devices 30 a , 30 b (formed by substrate 12 , floating body 24 , and regions 16 , 18 , respectively) re-establishing the equilibrium condition. Also, the positive bias applied to the substrate terminal 78 employed for the holding operation does not interrupt the write “0” operation of the selected memory cell(s).

A write “1” operation can be performed on memory cell 50 through impact ionization or band-to-band tunneling mechanism, as described for example in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.

›DETAILED DESCRIPTION · 5 of 64

An example of the bias condition of the selected memory cell 50 under band-to-band tunneling write “1” operation is illustrated in FIG. 14 and FIGS. 15 A- 15 B . The negative bias applied to the WL terminal 70 and the positive bias applied to the BL terminal 74 results in hole injection to the floating body 24 of the selected memory cell 50 . The positive bias applied to the substrate terminal 78 maintains the resulting positive charge on the floating body 24 as discussed above. The unselected cells 50 remain at the holding mode, with zero or negative voltage applied to the unselected WL terminal 70 and zero voltage is applied to the unselected BL terminal 74 to maintain the holding operation (holding mode).

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 50 a : a potential of about 0.0 volts is applied to terminal 72 , a potential of about +1.2 volts is applied to terminal 74 , a potential of about −1.2 volts is applied to terminal 70 , and about +1.2 volts is applied to terminal 78 ; and the following bias conditions are applied to the unselected memory cells 50 : about 0.0 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 74 , about 0.0 volts is applied to terminal 70 , and about +1.2 volts is applied to terminal 78 . FIG. 14 shows the bias conditions for the selected and unselected memory cells in memory array 80 . However, these voltage levels may vary.

The unselected memory cells during write “1” operations are shown in FIGS. 15 C- 15 H . The bias conditions for memory cells sharing the same row (e.g. memory cell 50 b ) are shown in FIGS. 15 C- 15 D and the bias conditions for memory cells sharing the same column as the selected memory cell 50 a (e.g. memory cell 50 c ) are shown in FIGS. 15 E- 15 F . The bias conditions for memory cells 50 not sharing the same row or the same column as the selected memory cell 50 a (e.g. memory cell 50 d ) are shown in FIGS. 15 G- 15 H .

For memory cells sharing the same row as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts, with the WL terminal 70 at zero or negative voltage ( FIGS. 15 C- 15 D ). Comparing with the holding operation bias condition, it can be seen that cells sharing the same row (i.e. the same WL terminal 70 ) are in holding mode. As a result, the states of these memory cells will remain unchanged.

For memory cells sharing the same column as the selected memory cell, a positive voltage is applied to the BL terminal 74 . As a result, the bipolar device 30 b formed by substrate 12 , floating body 24 , and region 18 connected to BL terminal 74 will be turned off because of the small voltage difference between the substrate terminal 78 and BL terminal 74 (the collector and emitter terminals, respectively). However, the bipolar device 30 a formed by substrate 12 , floating body 24 , and region 16 connected to SL terminal 72 will still generate base hole current for memory cells in state “1” having positive charge in floating body 24 . Memory cells in state “0” will remain in state “0” as this bipolar device 30 a (formed by substrate 12 , floating body 24 , and region 16 ) is off.

For memory cells not sharing the same row or the same column as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (see FIGS. 15 G- 15 H ). As can be seen, these cells will be in a holding operation (holding mode), where memory cells in state “1” will maintain the charge in floating body 24 because the intrinsic n-p-n bipolar devices 30 a , 30 b will generate hole current to replenish the charge in floating body 24 ; while memory cells in state “0” will remain in the neutral state.

Thus the positive bias applied to the substrate terminal 78 employed for the holding operation does not interrupt the write “1” operation of the selected memory cell(s). At the same time, the unselected memory cells during write “1” operation will remain in holding operation.

A multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to the memory cell 50 , followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to the memory cell 50 , followed by another read verification operation. This loop is repeated until the desired memory state is achieved.

For example, using band-to-band tunneling hot hole injection, a positive voltage is applied to BL terminal 74 , zero voltage is applied to SL terminal 72 , a negative voltage is applied to WL terminal 70 , and a positive voltage is applied to the substrate terminal 78 . Positive voltages of different amplitude are applied to BL terminal 74 to write different states to floating body 24 . This results in different floating body potentials 24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied to BL terminal 74 . By applying positive voltage to substrate terminal 78 , the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24 . In one particular non-limiting embodiment, the write operation is performed by applying the following bias condition: a potential of about 0.0 volts is applied to terminal 72 , a potential of about −1.2 volts is applied to terminal 70 , and about +1.2 volts is applied to terminal 78 , while the potential applied to BL terminal 74 is incrementally raised. For example, in one non-limiting embodiment 25 millivolts is initially applied to BL terminal 74 , followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e., cell current corresponding to whichever of 00, 01, 10 or 11 is desired is achieved), then the multi write operation is commenced. If the desired state is not achieved, then the voltage applied to BL terminal 74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary. The write operation is followed by a read operation to verify the memory state.

›DETAILED DESCRIPTION · 6 of 64

The write-then-verify algorithm is inherently slow since it requires multiple write and read operations. The present invention provides a multi-level write operation that can be performed without alternate write and read operations. This is accomplished by ramping the voltage applied to BL terminal 74 , while applying zero voltage to SL terminal 72 , a positive voltage to WL terminal 70 , and a positive voltage to substrate terminal 78 of the selected memory cells. The unselected memory cells will remain in holding mode, with zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74 . These bias conditions will result in a hole injection to the floating body 24 through impact ionization mechanism. The state of the memory cell 50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 ( FIGS. 16 A- 16 C ) coupled to the source line 72 . The cell current measured in the source line direction is a cumulative cell current of all memory cells 50 which share the same source line 72 (see FIGS. 16 A- 16 C ). As a result, only one memory cell 50 sharing the same source line 72 can be written. This ensures that the change in the cumulative cell current is a result of the write operation on the selected memory cell 50 .

As shown in FIG. 17 , the potential of the floating body 24 increases over time as these bias conditions result in hole injection to floating body 24 through an impact ionization mechanism. Once the change in cell current reaches the desired level associated with a state of the memory cell 50 , the voltage applied to BL terminal 74 can be removed. By applying a positive voltage (back bias) to substrate terminal 78 , the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24 . In this manner, the multi-level write operation can be performed without alternate write and read operations.

FIGS. 16 A- 16 C also show a reference generator circuit 92 , which serves to generate the initial cumulative cell current of the memory cells 50 sharing the same source line 72 being written. For example, the cumulative charge of the initial state for all memory cells 50 sharing the same source line 72 can be stored in a capacitor 94 (see FIG. 16 B ). Transistor 96 is turned on when charge is to be written into or read from capacitor 94 . Alternatively, a reference cell 50 R ( FIG. 16 C ) similar to a memory cell 50 can also be used to store the initial state. Using a similar principle, a write operation is performed on the reference cell 50 R using the cumulative cell current from the source line 72 . Transistor 96 is turned on when a write operation is to be performed on the reference cell 50 R. A positive bias is also applied to the substrate of the reference cell to maintain its state. The size of the reference cell 50 R needs to be configured such that it is able to store the maximum cumulative charge of all the memory cells 50 , i.e. when all of the memory cells 50 sharing the same source line 72 are positively charged.

In a similar manner, a multi-level write operation using an impact ionization mechanism can be performed by ramping the write current applied to BL terminal 74 instead of ramping the BL terminal 74 voltage.

In yet another embodiment, a multi-level write operation can be performed through a band-to-band tunneling mechanism by ramping the voltage applied to BL terminal 74 , while applying zero voltage to SL terminal 72 , a negative voltage to WL terminal 70 , and zero or positive voltage to substrate terminal 78 of the selected memory cells 50 . The unselected memory cells 50 will remain in holding mode, with zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74 . Optionally, multiple BL terminals 74 can be simultaneously selected to write multiple cells in parallel. The potential of the floating body 24 of the selected memory cell(s) 50 will increase as a result of the band-to-band tunneling mechanism. The state of the selected memory cell(s) 50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 coupled to the source line. Once the change in the cell current reaches the desired level associated with a state of the memory cell, the voltage applied to BL terminal 74 can be removed. If positive voltage is applied to substrate terminal 78 , the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24 . In this manner, the multi-level write operation can be performed without alternate write and read operations.

Similarly, the multi-level write operation using band-to-band tunneling mechanism can also be performed by ramping the write current applied to BL terminal 74 instead of ramping the voltage applied to BL terminal 74 .

In another embodiment, a read while programming operation can be performed by monitoring the change in cell current in the bit line direction through a reading circuitry 90 coupled to the bit line 74 as shown in FIG. 18 A . Reference cells 50 R representing different memory states are used to verify the state of the write operation The reference cells 50 R can be configured through a write-then-verify operation for example when the memory device is first powered up.

In the voltage ramp operation, the resulting cell current of the memory cell 50 being written is compared to the reference cell 50 R current by means of the read circuitry 90 . During this read while programming operation, the reference cell 50 R is also being biased at the same bias conditions applied to the selected memory cell 50 during the write operation. Therefore, the write operation needs to be ceased after the desired memory state is achieved to prevent altering the state of the reference cell 50 R. For the current ramp operation, the voltage at the bit line 74 can be sensed instead of the cell current. The bit line voltage can be sensed for example using a voltage sensing circuitry (see FIG. 18 B ) as described in “VLSI Design of Non-Volatile Memories”, Campardo G. et al., 2005, which is hereby incorporated herein, in its entirety, by reference thereto.

›DETAILED DESCRIPTION · 7 of 64

An example of a multi-level write operation without alternate read and write operations, using a read while programming operation/scheme in the bit line direction is given, where two bits are stored per memory cell 50 , requiring four states to be storable in each memory cell 50 . With increasing charge in the floating body 24 , the four states are referred to as states “00”, “01”, “10”, and “11”. To program a memory cell 50 to a state “01”, the reference cell 50 R corresponding to state “01” is activated. Subsequently, the bias conditions described above are applied both to the selected memory cell 50 and to the “01” reference cell 50 R: zero voltage is applied to the source line terminal 72 , a positive voltage is applied to the substrate terminal 78 , a positive voltage is applied to the WL terminal 70 (for the impact ionization mechanism), while the BL terminal 74 is being ramped up, starting from zero voltage. Starting the ramp voltage from a low voltage (i.e. zero volts) ensures that the state of the reference cell 50 R does not change.

The voltage applied to the BL terminal 74 is then increased.

Consequently, holes are injected into the floating body 24 of the selected cell 50 and subsequently the cell current of the selected cell 50 increases. Once the cell current of the selected cell 50 reaches that of the “01” reference cell, the write operation is stopped by removing the positive voltage applied to the BL terminal 74 and WL terminal 70 .

As was noted above, a periodic pulse of positive voltage can be applied to substrate terminal 78 , as opposed to applying a constant positive bias, to reduce the power consumption of the memory cell 50 . The memory cell 50 operations during the period where the substrate terminal 78 is being grounded are now briefly described. During the period when the substrate terminal 78 is grounded, the memory cells 50 connected to a ground substrate terminal 78 are no longer in holding mode. Therefore the period during which the substrate terminal is grounded must be shorter than the charge retention time period of the floating body, to prevent the state of the floating body from changing when the substrate terminal is grounded. The charge lifetime (i.e., charge retention time period) of the floating body 24 without use of a holding mode has been shown to be on the order of milliseconds, for example, see “A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond”, Ban et al., pp. 92-92, Symposium on VLSI Technology, 2008, which is hereby incorporated herein, in its entirety, by reference thereto. The state of the memory cell 50 can be maintained by refreshing the charge stored in floating body 24 during the period over which the positive voltage pulse is applied to the back bias terminal (i.e., substrate terminal 78 ).

A read operation can be performed by applying the following bias conditions: zero voltage is applied to the substrate terminal 78 , zero voltage is applied to SL terminal 72 , a positive voltage is applied to the selected BL terminal 74 , and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70 . The unselected BL terminals 74 will remain at zero voltage and the unselected WL terminals 70 will remain at zero or negative voltage. If the substrate terminals 78 are segmented (as for example shown in FIGS. 4 A- 4 C ), a positive voltage can be applied to the unselected substrate terminals 78 . In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72 , about +0.4 volts is applied to the selected terminal 74 , about +1.2 volts is applied to the selected terminal 70 , and about 0.0 volts is applied to terminal 78 . The unselected terminals 74 remain at 0.0 volts and the unselected terminals 70 remain at 0.0 volts. The unselected terminals 78 (in the case where the substrate terminals 78 are segmented as in FIGS. 4 A and 4 B ) can remain at +1.2 volts (see FIG. 19 ). Because the read operation is carried out over a time period on the order of nanoseconds, it is of a much shorter duration than the charge lifetime (charge retention time period) of the floating body 24 unassisted by a holding operation. Accordingly, the performance of a read operation does not affect the states of the memory cells connected to the terminal 78 as it is momentarily (on the order of nanoseconds) grounded.

A write “0” operation of the cell 50 can be performed by applying the following bias conditions: a negative bias is applied to SL terminal 72 , zero or negative voltage is applied to WL terminal 70 , and zero voltage is applied to substrate terminal 78 . The SL terminal 72 for the unselected cells will remain grounded. If the substrate terminals 78 are segmented (as for example shown in FIGS. 4 A- 4 C ), a positive voltage can be applied to the unselected substrate terminals 78 . Under these conditions, the p-n junction between 24 and 16 is forward-biased, evacuating any holes from the floating body 24 . In one particular non-limiting embodiment, about −2.0 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 70 , and about 0.0 volts is applied to terminal 78 . The unselected terminals 78 (in the case where the substrate terminals 78 are segmented as in FIGS. 4 A and 4 B ) can remain at +1.2 volts. With the substrate terminal 78 being grounded, there is no bipolar hole current flowing to the floating body 24 . As a result, the write “0” operation will also require less time. Because the write “0” operation is brief, occurring over a time period on the order of nanoseconds, it is of much shorter duration than the charge retention time period of the floating body 24 , unassisted by a holding operation. Accordingly, the write “0” operation does not affect the states of the unselected memory cells 50 connected to the terminal 78 being momentarily grounded to perform the write “0” operation. The bias conditions applied to the memory array 80 are shown in FIG. 20 . However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.

›DETAILED DESCRIPTION · 8 of 64

An example of the bias conditions for an alternative write “0” operation which allows for individual bit write is shown in FIG. 21 . The following conditions are applied to selected memory cell 50 : a positive voltage to WL terminal 70 , a negative voltage to BL terminal 74 , zero or positive voltage to SL terminal 72 , and zero voltage to substrate terminal 78 . Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70 . As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74 , the p-n junction between 24 and 18 is forward-biased, evacuating any holes from the floating body 24 . To reduce undesired write “0” disturb to other memory cells in the memory array sharing the same row or column as the selected memory cell, the applied potential can be optimized as follows: if the floating body 24 potential of state “1” is referred to as V FB1 , then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V FB1 /2 while −V FB1 /2 is applied to BL terminal 74 . A positive voltage can be applied to SL terminal 72 to further reduce the undesired write “0” disturb on other memory cells 50 in the memory array that do not share the same common SL terminal 72 as the selected memory cell. The unselected cells will remain at holding state, i.e. zero or negative voltage applied to WL terminal 70 , zero voltage applied to BL terminal 74 , and positive voltage applied to substrate terminal 78 (in the case the substrate terminals 78 are segmented as for example shown in FIGS. 4 A- 4 C ). Because the write “0” operation is brief, occurring over a time period on the order of nanoseconds, it is of much shorter duration than the charge retention time period of the floating body 24 , unassisted by a holding operation. Accordingly, the write “0” operation does not affect the states of the unselected memory cells 50 connected to the terminal 78 being momentarily grounded to perform the write “0” operation.

Still referring to FIG. 21 , in one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 50 a : a potential of about 0.0 volts is applied to terminal 72 a , a potential of about −0.2 volts is applied to terminal 74 a , a potential of about +0.5 volts is applied to terminal 70 a , and about 0.0 volts is applied to terminal 78 a ; while about 0.0 volts is applied to terminal 72 n and the other SL terminals not connected to the selected cell 50 a , about 0.0 volts is applied to terminal 74 n and the other BL terminals not connected to the selected cell 50 a , about 0.0 volts is applied to terminal 70 n and the other WL terminals not connected to the selected cell 50 a , and about +1.2 volts is applied to terminal 78 n and the other substrate terminals not connected to the selected cell 50 a . However, these voltage levels may vary.

An example of the bias conditions applied to the memory array 80 under a band-to-band tunneling write “1” operation to cell 50 a is shown in FIG. 22 , where a negative bias is applied to WL terminal 70 a , a positive bias is applied to BL terminal 74 a , zero voltage is applied to SL terminal 72 a , and zero voltage is applied to substrate terminal 78 a . The negative bias applied to the WL terminal 70 a and the positive bias applied to the BL terminal 74 a will result in hole injection to the floating body 24 of the selected memory cell 50 a . The unselected cells 50 will remain at the holding mode, with zero or negative voltage applied to the unselected WL terminals 70 (in this case, terminal 70 n and any other WL terminal 70 not connected to selected cell 50 a ) and zero voltage is applied to the unselected BL terminals 74 (in this case, terminals 74 b , 74 n and any other BL terminal 74 not connected to selected cell 50 a ) and positive voltage applied to unselected substrate terminals 78 (in the case the substrate terminals 78 are segmented as for example shown in FIGS. 4 A and 4 B ; and, in FIG. 22 , to terminals 78 n and any other substrate terminals 78 not connected to selected cell 50 a ).

Still referring to FIG. 22 , in one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 50 a : a potential of about 0.0 volts is applied to terminal 72 a , a potential of about +1.2 volts is applied to terminal 74 a , a potential of about −1.2 volts is applied to terminal 70 a , and about 0.0 volts is applied to terminal 78 a ; while about 0.0 volts is applied to the unselected terminals 72 (defined in the preceding paragraph), about 0.0 volts is applied to unselected terminals 74 (defined in the preceding paragraph), about 0.0 volts is applied to unselected terminals 70 (defined in the preceding paragraph), and about +1.2 volts is applied to unselected substrate terminals 78 (defined in the preceding paragraph) of the unselected memory cells. However, these voltage levels may vary.

FIG. 23 A shows another embodiment of a memory cell 150 according to the present invention. The cell 150 includes a substrate 12 of a first conductivity type, such as a p-type conductivity type, for example. Substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. The substrate 12 has a surface 14 . A first region 16 having a second conductivity type, such as n-type, for example, is provided in substrate 12 and is exposed at surface 14 . A second region 18 having the second conductivity type is also provided in substrate 12 , and is also exposed at surface 14 . Second region 18 is spaced apart from the first region 16 , as shown. First and second regions 16 and 18 may be formed by an implantation process on the material making up substrate 12 , according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process may be used to form first and second regions 16 and 18 .

›DETAILED DESCRIPTION · 9 of 64

A buried layer 22 of the second conductivity type is also provided in the substrate 12 , buried in the substrate 12 , as shown. Buried layer 22 may also be formed by an ion implantation process on the material of substrate 12 . Alternatively, buried layer 22 can be grown epitaxially. A floating body region 24 of the substrate 12 having a first conductivity type, such as a p-type conductivity type, is bounded by surface, first and second regions 16 , 18 , insulating layers 26 and buried layer 22 . Insulating layers 26 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulating layers 26 insulate cell 150 from neighboring cells 150 when multiple cells 150 are joined in an array 180 to make a memory device as illustrated in FIG. 24 . A gate 60 is positioned in between the regions 16 and 18 , and above the surface 14 . The gate 60 is insulated from surface 14 by an insulating layer 62 . Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Cell 150 further includes word line (WL) terminal 70 electrically connected to gate 60 , source line (SL) terminal 72 electrically connected to one of regions 16 and 18 (connected to 16 as shown, but could, alternatively, be connected to 18 ), bit line (BL) terminal 74 electrically connected to the other of regions 16 and 18 , buried well (BW) terminal 76 electrically connected to buried layer 22 , and substrate terminal 78 electrically connected to substrate 12 at a location beneath buried layer 22 . Contact to buried well region 22 could be made through region 20 having a second conductivity type, which is electrically connected to buried well region 22 , while contact to substrate region 12 could be made through region 28 having a first conductivity type, which is electrically connected to substrate region 12 , as shown in FIG. 23 B

In another embodiment, the memory cell 150 may be provided with p-type conductivity type as the first conductivity type and n-type conductivity type as the second conductivity type.

As shown in FIG. 25 , inherent in this embodiment of the memory cell 150 are n-p-n bipolar devices 130 a , 130 b formed by buried well region 22 , floating body 24 , and SL and BL regions 16 , 18 . The memory cell operations will be described as follows. As will be seen, the operation principles of this embodiment of the memory cell 150 will follow the descriptions above, where the bias applied on the n-type substrate terminal 78 for the above described memory cell 50 is now applied to the n-type buried well terminal 76 of cell 150 . The p-type substrate 12 of the current embodiment of the memory cell 150 will be grounded, reverse biasing the p-n junction between substrate 12 and buried well layer 22 , thereby preventing any leakage current between substrate 12 and buried well layer 22 .

A holding operation can be performed by applying a positive back bias to the BW terminal 76 while grounding terminal 72 and/or terminal 74 . If floating body 24 is positively charged (i.e. in a state “1”), the bipolar transistor formed by SL region 16 , floating body 24 , and buried well region 22 and bipolar transistor formed by BL region 18 , floating body 24 , and buried well region 22 will be turned on.

A fraction of the bipolar transistor current will then flow into floating region 24 (usually referred to as the base current) and maintain the state “1” data. The efficiency of the holding operation can be enhanced by designing the bipolar devices 130 a , 130 b formed by buried well layer 22 , floating region 24 , and regions 16 / 18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of BW terminal 76 to the base current flowing into the floating region 24 .

For memory cells in state “0” data, the bipolar devices 130 a , 130 b will not be turned on, and consequently no base hole current will flow into floating region 24 . Therefore, memory cells in state “0” will remain in state “0”.

The holding operation can be performed in mass, parallel manner as the BW terminal 76 (functioning as back bias terminal) is typically shared by all the cells 150 in the memory array 180 , or at least by multiple cells 150 in a segment of the array 180 . The BW terminal 76 can also be segmented to allow independent control of the applied bias on a selected portion of the memory array 180 . Also, because BW terminal 76 is not used for memory address selection, no memory cell access interruption occurs due to the holding operation.

An example of the bias conditions applied to cell 150 to carry out a holding operation includes: zero voltage is applied to BL terminal 74 , zero voltage is applied to SL terminal 72 , zero or negative voltage is applied to WL terminal 70 , a positive voltage is applied to the BW terminal 76 , and zero voltage is applied to substrate terminal 78 . In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 74 , about 0.0 volts is applied to terminal 70 , about +1.2 volts is applied to terminal 76 , and about 0.0 volts is applied to terminal 78 . However, these voltage levels may vary.

A read operation can be performed on cell 150 by applying the following bias conditions: a positive voltage is applied to the BW terminal 76 , zero voltage is applied to SL terminal 72 , a positive voltage is applied to the selected BL terminal 74 , and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70 , while zero voltage is applied to substrate terminal 78 . When cell 150 is in an array 180 of cells 150 , the unselected BL terminals 74 (e.g., 74 b , . . . , 74 n ) will remain at zero voltage and the unselected WL terminals 70 (e.g., 70 n and any other WL terminals 70 not connected to selected cell 150 a ) will remain at zero or negative voltage. In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72 , about +0.4 volts is applied to the selected terminal 74 a , about +1.2 volts is applied to the selected terminal 70 a , about +1.2 volts is applied to terminal 76 , and about 0.0 volts is applied to terminal 78 , as illustrated in FIG. 26 . The unselected terminals 74 remain at 0.0 volts and the unselected terminal 70 remain at 0.0 volts as illustrated in FIG. 26 . However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above. As a result of the bias conditions applied as described, the unselected memory cells ( 150 b , 150 c and 150 d ) will be at holding mode, maintaining the states of the respective floating bodies 24 thereof. Furthermore, the holding operation does not interrupt the read operation of the selected memory cell 150 a.

›DETAILED DESCRIPTION · 10 of 64

To write “0” to cell 150 , a negative bias is applied to SL terminal 72 , zero or negative voltage is applied to WL terminal 70 , zero or positive voltage is applied to BW terminal 76 , and zero voltage is applied to substrate terminal 78 . The SL terminal 72 for the unselected cells 150 that are not commonly connected to the selected cell 150 a will remain grounded. Under these conditions, the p-n junctions (junction between 24 and 16 and between 24 and 18 ) are forward-biased, evacuating any holes from the floating body 24 . In one particular non-limiting embodiment, about −2.0 volts is applied to terminal 72 , about −1.2 volts is applied to terminal 70 , about +1.2 volts is applied to terminal 76 , and about 0.0 volts is applied to terminal 78 . However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.

The bias conditions for all the unselected cells are the same since the write “0” operation only involves applying a negative voltage to the SL terminal 72 (thus to the entire row). As can be seen, the unselected memory cells will be in holding operation, with both BL and SL terminals at about 0.0 volts.

Thus, the holding operation does not interrupt the write “0” operation of the memory cells. Furthermore, the unselected memory cells will remain in holding operation during a write “0” operation.

An alternative write “0” operation, which, unlike the previous write “0” operation described above, allows for individual bit write, can be performed by applying a positive voltage to WL terminal 70 , a negative voltage to BL terminal 74 , zero or positive voltage to SL terminal 72 , zero or positive voltage to BW terminal 76 , and zero voltage to substrate terminal 78 . Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70 . As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74 , the p-n junction (junction between 24 and 16 ) is forward-biased, evacuating any holes from the floating body 24 . The applied bias to selected WL terminal 70 and selected BL terminal 74 can potentially affect the states of the unselected memory cells 150 sharing the same WL or BL terminal as the selected memory cell 150 . To reduce undesired write “0” disturb to other memory cells 150 in the memory array 180 , the applied potential can be optimized as follows: If the floating body 24 potential of state “1” is referred to as V FB1 , then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V FB1 /2 while −V FB1 /2 is applied to BL terminal 74 . This will minimize the floating body 24 potential change in the unselected cells 150 in state “1” sharing the same BL terminal as the selected cell 150 from V FB1 to V FB1 /2. For memory cells 150 in state “0” sharing the same WL terminal as the selected cell 150 , if the increase in floating body 24 potential is sufficiently high (i.e., at least V FB /3, see below), then both n-p-n bipolar devices 130 a and 130 b will not be turned on or so that the base hold current is low enough that it does not result in an increase of the floating body 24 potential over the time during which the write operation is carried out (write operation time). It has been determined according to the present invention that a floating body 24 potential increase of V FB /3 is low enough to suppress the floating body 24 potential increase. A positive voltage can be applied to SL terminal 72 to further reduce the undesired write “0” disturb on other memory cells 150 in the memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74 . The unselected cells 150 not sharing the same WL or BL terminal as the selected cell 150 will remain at holding state, i.e., with zero or negative voltage applied to unselected WL terminal and zero voltage applied to unselected BL terminal 74 .

In one particular non-limiting embodiment, for the selected cell 150 a potential of about 0.0 volts is applied to terminal 72 , a potential of about −0.2 volts is applied to terminal 74 , a potential of about +0.5 volts is applied to terminal 70 , about +1.2 volts is applied to terminal 76 , and about 0.0 volts is applied to terminal 78 . For the unselected cells not sharing the same WL terminal or BL terminal with the selected memory cell 50 , about 0.0 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 74 , about 0.0 volts is applied to terminal 70 , about +1.2 volts is applied to terminal 76 , and about 0.0 volts is applied to terminal 78 . FIG. 27 shows the bias conditions for the selected and unselected memory cells 150 in memory array 180 . However, these voltage levels may vary.

An example of the bias conditions applied to a selected memory cell 150 during a write “0” operation is illustrated in FIGS. 28 A- 28 B . An example of the bias conditions applied to the unselected memory cells 150 during write “0” operations are shown in FIGS. 28 C- 28 H . The bias conditions for unselected memory cells 150 sharing the same row as selected memory cell 150 a (e.g. memory cell 150 b in FIG. 27 ) are shown in FIGS. 28 C- 28 D . The bias conditions for unselected memory cells 150 sharing the same column as selected memory cell 150 a (e.g. memory cell 150 c in FIG. 27 ) are shown in FIGS. 28 E- 28 H . The bias conditions for unselected memory cells 150 not sharing the same row or the same column as the selected memory cell 150 a (e.g. memory cell 150 d in FIG. 27 ) are shown in FIGS. 28 G- 28 H .

During the write “0” operation (individual bit write “0” operation described above) in memory cell 150 , the positive back bias applied to the BW terminal 76 of the memory cells 150 is necessary to maintain the states of the unselected cells 150 , especially those sharing the same row or column as the selected cell 150 a , as the bias condition can potentially alter the states of the memory cells 150 without the intrinsic bipolar device 130 (formed by buried well region 22 , floating body 24 , and regions 16 , 18 ) re-establishing the equilibrium condition. Furthermore, the holding operation does not interrupt the write “0” operation of the memory cells 150 .

›DETAILED DESCRIPTION · 11 of 64

A write “1” operation can be performed on memory cell 150 through an impact ionization mechanism or a band-to-band tunneling mechanism, as described for example in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.

An example of bias conditions applied to selected memory cell 150 a under a band-to-band tunneling write “1” operation is further elaborated and is shown in FIG. 29 . The negative bias applied to the WL terminal 70 a and the positive bias applied to the BL terminal 74 a will result in hole injection to the floating body 24 . The positive bias applied to the BW terminal 76 a will maintain the resulting positive charge on the floating body 24 as discussed above. The unselected cells 150 will remain at the holding mode, with zero or negative voltage applied to the unselected WL terminal 70 (in FIG. 27 , 70 n and all other WL terminals 70 not connected to cell 150 a ) and zero voltage is applied to the unselected BL terminal 74 b , 74 n and all other BL terminals 74 not connected to cell 150 a ). The positive bias applied to the BW terminal 76 employed for the holding operations does not interrupt the write “1” operation of the selected memory cell(s). At the same time, the unselected memory cells 150 will remain in a holding operation during a write “1” operation on a selected memory cell 150 .

A multi-level operation can also be performed on memory cell 150 . A holding operation to maintain the multi-level states of memory cell 50 is described with reference to FIG. 6 . The relationship between the floating body 24 current for different floating body 24 potentials as a function of the BW terminal 76 potential ( FIG. 6 B ) is similar to that of floating body 24 current as a function of the substrate terminal 78 potential ( FIG. 6 A ). As indicated in FIG. 6 B , for different floating body potentials, at a certain BW terminal 76 potential V HOLD , the current flowing into floating body 24 is balanced by the junction leakage between floating body 24 and regions 16 and 18 . The different floating body 24 potentials represent different charges used to represent different states of memory cell 150 . This shows that different memory states can be maintained by using the holding/standby operation described here.

A multi-level write operation without alternate write and read operations on memory cell 150 is now described. To perform this operation, zero voltage is applied to SL terminal 72 , a positive voltage is applied to WL terminal 70 , a positive voltage (back bias) is applied to BW terminal 76 , and zero voltage is applied to substrate terminal 78 , while the voltage of BL terminal 74 is ramped up. These bias conditions will result in a hole injection to the floating body 24 through an impact ionization mechanism. The state of the memory cell 150 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 coupled to the source line 72 . The cell current measured in the source line direction (where source line current equals bit line current plus BW current and the currents are measured in the directions from buried well to source line and from bit line to source line) is a cumulative cell current of all memory cells 150 which share the same source line 72 (e.g. see FIGS. 16 A- 16 C for examples of monitoring cell current in the source line direction. The same monitoring scheme can be applied to memory array 80 as well as memory array 180 ). As a result, only one memory cell 150 sharing the same source line 72 can be written. This ensures that the change in the cumulative cell current is a result of the write operation on the selected memory cell 150 .

The applied bias conditions will result in hole injection to floating body 24 through an impact ionization mechanism. FIG. 17 shows the resulting increase of the floating body potential 24 over time. Once the change in cell current reaches the desired level associated with a state of the memory cell 150 (levels are schematically represented in FIG. 17 ), the voltage applied to BL terminal 74 can be removed. By applying a positive voltage to BW terminal 76 , the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24 . In this manner, the multi-level write operation can be performed without alternate write and read operations.

In a similar manner, the multi-level write operation using impact ionization mechanism can also be performed by ramping the write current applied to BL terminal 74 instead of ramping the BL terminal 74 voltage.

In yet another embodiment, a multi-level write operation can be performed through a band-to-band tunneling mechanism by ramping the voltage applied to BL terminal 74 , while applying zero voltage to SL terminal 72 , a negative voltage to WL terminal 70 , a positive voltage to BW terminal 76 , and zero voltage to substrate terminal 78 . The potential of the floating body 24 will increase as a result of the band-to-band tunneling mechanism. The state of the memory cell 50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 coupled to the source line 72 . Once the change in the cell current reaches the desired level associated with a state of the memory cell, the voltage applied to BL terminal 74 can be removed. If positive voltage is applied to substrate terminal 78 , the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24 . In this manner, the multi-level write operation can be performed without alternate write and read operations.

›DETAILED DESCRIPTION · 12 of 64

Similarly, a read while programming operation can be performed by monitoring the change in cell current in the bit line 74 direction (where bit line current equals SL current plus BW current) through a reading circuitry 90 coupled to the bit line 74 , for example as shown in FIG. 18 A . For the current ramp operation, the voltage at the bit line 74 can be sensed, rather than sensing the cell current. The bit line voltage can be sensed, for example, using a voltage sensing circuitry, see FIG. 18 B .

Another embodiment of memory cell 150 operations, which utilizes the silicon controlled rectifier (SCR) principle has been disclosed in U.S. patent application Ser. No. 12/533,661, filed Jul. 31, 2009, which was incorporated by reference, in its entirety, above.

FIGS. 30 and 31 show another embodiment of the memory cell 50 described in this invention. In this embodiment, cell 50 has a fin structure 52 fabricated on substrate 12 having a first conductivity type (such as n-type conductivity type) so as to extend from the surface of the substrate to form a three-dimensional structure, with fin 52 extending substantially perpendicularly to, and above the top surface of the substrate 12 . Fin structure 52 includes first and second regions 16 , 18 having the first conductivity type. The floating body region 24 is bounded by the top surface of the fin 52 , the first and second regions 16 , 18 and insulating layers 26 (insulating layers 26 can be seen in the top view of FIG. 34 ). Insulating layers 26 insulate cell 50 from neighboring cells 50 when multiple cells 50 are joined to make a memory device (array 80 ). The floating body region 24 is conductive having a second conductivity type (such as p-type conductivity type) and may be formed through an ion implantation process or may be grown epitaxially. Fin 52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.

Memory cell device 50 further includes gates 60 on two opposite sides of the floating substrate region 24 as shown in FIG. 30 . Alternatively, gates 60 can enclose three sides of the floating substrate region 24 as shown in FIG. 31 . Gates 60 are insulated from floating body 24 by insulating layers 62 . Gates 60 are positioned between the first and second regions 16 , 18 , adjacent to the floating body 24 .

Device 50 includes several terminals: word line (WL) terminal 70 , source line (SL) terminal 72 , bit line (BL) terminal 74 , and substrate terminal 78 . Terminal 70 is connected to the gate 60 . Terminal 72 is connected to first region 16 and terminal 74 is connected to second region 18 . Alternatively, terminal 72 can be connected to second region 18 and terminal 74 can be connected to first region 16 . Terminal 78 is connected to substrate 12 .

FIGS. 32 and 33 show another embodiment of memory cell 150 described in this invention. In this embodiment, cell 150 has a fin structure 52 fabricated on substrate 12 , so as to extend from the surface of the substrate to form a three-dimensional structure, with fin 52 extending substantially perpendicularly to, and above the top surface of the substrate 12 . Fin structure 52 is conductive and is built on buried well layer 22 . Region 22 may be formed by an ion implantation process on the material of substrate 12 or grown epitaxially. Buried well layer 22 insulates the floating substrate region 24 , which has a first conductivity type (such as p-type conductivity type), from the bulk substrate 12 . Fin structure 52 includes first and second regions 16 , 18 having a second conductivity type (such as n-type conductivity type). Thus, the floating body region 24 is bounded by the top surface of the fin 52 , the first and second regions 16 , 18 the buried well layer 22 , and insulating layers 26 (see FIG. 34 ). Insulating layers 26 insulate cell 150 from neighboring cells 150 when multiple cells 150 are joined to make a memory device. Fin 52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.

Memory cell device 150 further includes gates 60 on two opposite sides of the floating substrate region 24 as shown in FIG. 32 . Alternatively, gates 60 can enclose three sides of the floating substrate region 24 as shown in FIG. 33 . Gates 60 are insulated from floating body 24 by insulating layers 62 . Gates 60 are positioned between the first and second regions 16 , 18 , adjacent to the floating body 24 .

Device 150 includes several terminals: word line (WL) terminal 70 , source line (SL) terminal 72 , bit line (BL) terminal 74 , buried well (BW) terminal 76 and substrate terminal 78 . Terminal 70 is connected to the gate 60 . Terminal 72 is connected to first region 16 and terminal 74 is connected to second region 18 . Alternatively, terminal 72 can be connected to second region 18 and terminal 74 can be connected to first region 16 . Terminal 76 is connected to buried layer 22 and terminal 78 is connected to substrate 12 .

FIG. 34 illustrates the top view of the memory cells 50 / 150 shown in FIGS. 30 and 32 .

From the foregoing it can be seen that with the present invention, a semiconductor memory with electrically floating body is achieved. The present invention also provides the capability of maintaining memory states or parallel non-algorithmic periodic refresh operations. As a result, memory operations can be performed in an uninterrupted manner. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.

›DETAILED DESCRIPTION · 13 of 64

In a floating body memory, the different memory states are represented by different levels of charge in the floating body. In “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 (“Okhonin-1”) and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002) (“Ohsawa-1”), a single bit (two voltage levels) in a standard MOSFET is contemplated. Others have described using more than two voltage levels stored in the floating body of a standard MOSFET allowing for more than a single binary bit of storage in a memory cell like, for example, “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 (“Tack”) which is incorporated by reference herein in its entirely, and U.S. Pat. No. 7,542,345 “Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same” to Okhonin, et al (“Okhonin-2”). Tack describes obtaining more than two states in the floating body of a standard MOSFET built in SOI by manipulating the “back gate”—a conductive layer below the bottom oxide (BOX) of the silicon tub the MOSFET occupies. Okhonin-2 discloses attaining more than two voltage states in the floating body utilizing the intrinsic bipolar junction transistor (BJT) formed between the two source/drain regions of the standard MOSFET to generate read and write currents.

In memory design in general, sensing and amplifying the state of a memory cell is an important aspect of the design. This is true as well of floating body DRAM memories. Different aspects and approaches to performing a read operation are known in the art like, for example, the ones disclosed in “A Design of a Capacitor-less 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003 (“Yoshida”) which is incorporated by reference herein in its entirely; in U.S. Pat. No. 7,301,803 “Bipolar reading technique for a memory cell having an electrically floating body transistor” (“Okhonin-3”) which is incorporated by reference herein in its entirely; and in “An 18.5 ns 128 Mb SOI DRAM with a Floating Body Cell”, Ohsawa et al., pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005 (“Ohsawa-2”) which is incorporated by reference herein in its entirely. Both Yoshida and Okhonin-3 disclose a method of generating a read current from a standard MOSFET floating body memory cell manufactured in SOI-CMOS processes. Okhonin-3 describes using the intrinsic BJT transistor inherent in the standard MOSFET structure to generate the read current. Ohsawa-2 discloses a detailed sensing scheme for use with standard MOSFET floating body memory cells implemented in both SOI and standard bulk silicon.

Writing a logic-0 to a floating body DRAM cell known in the art is straight forward. Either the source line or the bit line is pulled low enough to forward bias the junction with the floating body removing the hole charge, if any. Writing a logic-1 typically may be accomplished using either a band-to-band tunneling method (also known as Gate Induced Drain Leakage or GIDL) or an impact ionization method

In floating body DRAM cells, writing a logic-0 is straightforward (simply forward biasing either the source or drain junction of the standard MOSFET will evacuate all of the majority carriers in the floating body writing a logic-0) while different techniques have been explored for writing a logic-1. A method of writing a logic-1 through a gate induced band-to-band tunneling mechanism, as described for example in Yoshida. The general approach in Yoshida is to apply an appropriately negative voltage to the word line (gate) terminal of the memory cell while applying an appropriately positive voltage to the bit line terminal (drain) and grounding the source line terminal (source) of the selected memory cell. The negative voltage on WL terminal and the positive voltage on BL terminal creates a strong electric field between the drain region of the MOSFET transistor and the floating body region in the proximity of the gate (hence the “gate induced” portion of GIDL) in the selected memory cell. This bends the energy bands sharply upward near the gate and drain junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current (hence the “drain leakage” portion of GIDL), while the holes are injected into floating body region 24 and become the hole charge that creates the logic-1 state. This process is well known in the art and is illustrated in Yoshida (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4).

A method of writing a logic-1 through impact ionization is described, for example, in “A New 1T DRAM Cell with Enhanced Floating Body Effect”, Lin and Chang, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, (“Lin”) which is incorporated in its entirety by reference herein. The general approach in Lin is to bias both the gate and bit line (drain) terminals of the memory cell to be written at a positive voltage while grounding the source line (source). Raising the gate to a positive voltage has the effect of raising the voltage potential of the floating body region due to capacitive coupling across the gate insulating layer. This in conjunction with the positive voltage on the drain terminal causes the intrinsic n-p-n bipolar transistor (drain (n=collector) to floating body (p=base) to source (n=emitter)) to turn on regardless of whether or not a logic-1 or logic-0 is stored in the memory cell. In particular, the voltage across the reversed biased p-n junction between the floating body (base) and the drain (collector) will cause a small current to flow across the junction. Some of the current will be in the form of hot carriers accelerated by the electric field across the junction. These hot carriers will collide with atoms in the semiconductor lattice which will generate hole-electron pairs in the vicinity of the junction. The electrons will be swept into the drain (collector) by the electric field and become bit line (collector) current, while the holes will be swept into the floating body region, becoming the hole charge that creates the logic-1 state.

›DETAILED DESCRIPTION · 14 of 64

Much of the work to date has been done on SOI, which is generally more expensive than a bulk silicon process. Some effort has been made to reduce costs of manufacturing floating body DRAMs by starting with bulk silicon. An example of a process to selectively form buried isolation region is described in “Silicon on Replacement Insulator (SRI) Floating Body Cell (FBC) Memory”, S. Kim et al., pp. 165-166, Tech Digest, Symposium on VLSI Technology, 2010, (“S_Kim”) which is incorporated in its entirety by reference herein. In S_Kim bulk silicon transistors are formed. Then the floating bodies are isolated by creating a silicon-on-replacement-insulator (SRI) structure. The layer of material under the floating body cells is selectively etched away and replaced with insulator creating an SOI type of effect. An alternate processing approach to selectively creating a gap and then filling it with an insulator is described in “A 4-bit Double SONGS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation”, Oh et al., pp. 58-59, Tech Digest, Symposium on VLSI Technology, 2006 (“Oh”) which is incorporated in its entirety by reference herein.

Most work to date has involved standard lateral MOSFETs in which the source and drain are disposed at the surface of the semiconductor where they are coupled to the metal system above the semiconductor surface. A floating body DRAM cell using a vertical MOSFET has been described in “Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application”, J. Kim et al., pp. 163-164, Symposium of VLSI Technology, 2010, (“J_Kim”) which is incorporated in its entirety by reference herein. In J_Kim, the floating body is bounded by a gate on two sides with a source region above and a buried drain region below. The drain is connected to a tap region, which allows a connection between a conductive plug at the surface to the buried drain region.

An alternate method of using a standard lateral MOSFET in a floating body DRAM cell is described in co-pending and commonly owned U.S. Patent Application Publication 2010/0034041 to Widjaja (“Widjaja”), which is incorporated in its entirety by reference herein. Widjaja describes a standard lateral MOSFET floating body DRAM cell realized in bulk silicon with a buried well and a substrate which forms a vertical silicon controlled rectifier (SCR) with a P1-N2-P3-N4 formed by the substrate, the buried well, the floating body, and the source (or drain) region of the MOSFET respectively. This structure behaves like two bipolar junction transistor (BJT) devices coupled together—one an n-p-n (N2-P3-N4) and one a p-n-p (P3-N2-P1)—which can be manipulated to control the charge on the floating body region (P3).

The construction and operation of standard MOSFET devices is well known in the art. An exemplary standard metal-oxide-semiconductor field effect transistor (MOSFET) device 100 is shown in FIG. 90 A . MOSFET device 100 consists of a substrate region of a first conductivity type 82 (shown as p-type in the figure), and first and second regions 84 and 86 of a second conductivity type (shown as n-type) on the surface 88 , along with a gate 90 , separated from the semiconductor surface region by an insulating layer 92 . Gate 90 is positioned in between the regions 84 and 86 . Insulating layers 96 can be used to separate one transistor device from other devices on the silicon substrate 82 .

As shown in FIG. 90 B , a standard MOSFET device 100 A may also consist of a well region 94 A of a first conductivity type (shown as p-type in the figure) in a substrate region 82 A of a second conductivity type (shown as n-type in the figure), with first and second regions 84 A and 86 A of a second conductivity type on the surface 88 A. In addition, a gate 90 A, separated from the surface region 88 A by an insulating layer 92 A, is also present in between the first and second regions 84 A and 86 A. Insulating layers 96 A can be used to separate one transistor device from other devices in the well region 94 A. MOSFET devices 100 and 100 A are both constructed in bulk silicon CMOS technology.

As shown in FIG. 90 C , a standard MOSFET device 100 B is shown constructed out of silicon-on-insulator technology. MOSFET device 100 B consists of a tub region of a first conductivity type 82 B (shown as p-type in the figure), and first and second regions 84 B and 86 B of a second conductivity type (shown as n-type) on the surface 88 B, along with a gate 90 B, separated from the semiconductor surface region by an insulating layer 92 B. Gate 90 B is positioned in between the regions 84 B and 86 B. The tub region 82 B is isolated from other devices on the sides by insulating layers 96 B and on the bottom by insulating layer 83 B. Optionally, there may be a conductive layer affixed to the bottom of insulating layer 83 B (not shown) which may be used as a “back gate” by coupling through the insulating layer 83 B to the tub region 82 B.

The transistors 100 , 100 A, and 100 B are all called n-channel transistors because when turned on by applying an appropriate voltage to the gates 90 , 90 A and 90 B respectively, the p-material under the gates is inverted to behave like n-type conductivity type for as long as the gate voltage is applied. This allows conduction between the two n-type regions 84 and 86 in MOSFET 100 , 84 A and 86 A in MOSFET 100 A and 84 B and 86 B in MOSFET 100 B. As is well known in the art, the conductivity types of all the regions may be reversed (i.e., the first conductivity type regions become n-type and the second conductivity type regions become p-type) to produce p-channel transistors. In general, n-channel transistors are be preferred for use in memory cells (of all types and technologies) because of the greater mobility of the majority carrier electrons (as opposed to the majority carrier holes in p-channel transistors) allowing more read current for the same sized transistor, but p-channel transistors may be used as a matter of design choice.

›DETAILED DESCRIPTION · 15 of 64

The invention below describes a semiconductor memory device having an electrically floating body that utilizes a back bias region to further reduce the memory device size. One or more bits of binary information may be stored in a single memory cell. Methods of construction and of operation of the semiconductor device are also provided.

This disclosure uses the standard convention that p-type and n-type semiconductor “diffusion” layers or regions (regardless of how formed during manufacture) such as transistor source, drain or source/drain regions, floating bodies, buried layers, wells, and the semiconductor substrate as well as related insulating regions between the diffusion regions (like, for example, silicon dioxide whether disposed in shallow trenches or otherwise) are typically considered to be “beneath” or “below” the semiconductor surface—and the drawing figures are generally consistent with this convention by placing the diffusion regions at the bottom of the drawing figures. The convention also has various “interconnect” layers such as transistor gates (whether constructed of metal, p-type or n-type polysilicon or some other material), metal conductors in one or more layers, contacts between diffusion regions at the semiconductor surface and a metal layer, contacts between the transistor gates and a metal layer, vias between two metal layers, and the various insulators between them (including gate insulating layers between the gates and a diffusion at the semiconductor surface) are considered to be “above” the semiconductor surface—and the drawing figures are generally consistent with this convention placing these features, when present, near the top of the figures. One exception worth noting is that gates may in some embodiments be constructed in whole or in part beneath the semiconductor surface. Another exception is that some insulators may be partially disposed both above and below the surface. Other exceptions are possible. Persons of ordinary skill in the art will appreciate that the convention is used for ease of discussion with regards to the standard way of drawing and discussing semiconductor structures in the literature, and that a physical semiconductor in use in an application may be deployed at any angle or orientation without affecting its physical or electrical properties thereby.

The exemplary embodiments disclosed herein have at most one surface contact from the semiconductor region below the semiconductor surface to the interconnect region above the semiconductor surface within the boundary of the memory cell itself. This is in contrast to one-transistor (1T) floating body cell (FBC) DRAMs of the prior art which have two contacts—one for the source region and one for the drain region of the transistor. While some 1T FBC DRAM cells of the prior art can share the two contacts with adjacent cells resulting in an average of one contact per cell, some embodiments of the present invention can also share its contact with an adjacent cell averaging half a contact per cell.

The advantage of the present invention is in the elimination of one of the source/drain regions at the surface of the semiconductor region thereby eliminating the need to contact it at the surface. Compare, for example, FIG. 90 B illustrating a prior art MOSFET with FIG. 35 C illustrating an analogous cross section of one embodiment of the present invention. In any processing technology, the structure of FIG. 35 C is inherently smaller than the structure of FIG. 90 B . In some embodiments of the present invention, the gate terminal is removed as well further reducing the size of the memory cell. Compare, for example, the analogous cross sections of the structures in FIGS. 77 C and 85 C to the prior art MOSFET of FIG. 90 B . This new class of memory cell is referred to as a “Half Transistor Memory Cell” as a convenient shorthand for identical, similar or analogous structures. A structure identical, similar or analogous to the structure of FIG. 35 C is referred to as a “Gated Half Transistor Memory Cell.” A structure identical, similar or analogous to the structures of FIGS. 77 C and 85 C is referred to as a “Gateless Half Transistor Memory Cell.” The vertical arrangement of the diffusion regions beneath the semiconductor surface common to all half transistor memory cells—specifically a bit line region at the surface of the semiconductor (allowing coupling to a bit line disposed above the semiconductor surface), a floating body region (for storing majority charge carriers, the quantity of majority carriers determining the logical state of the data stored in memory cell), and a source line region (completely beneath the semiconductor surface within the boundary of the memory cell allowing coupling to a source line running beneath the semiconductor surface, typically running beneath and coupling to a plurality of memory cells), wherein the bit line region, the floating body, and the source line region form a vertical bipolar junction transistor that is used operatively and constructed deliberately by design for use in a floating body DRAM memory cell application—is referred to as a “Half Transistor.”

Persons of ordinary skill in the art will appreciate that the following embodiments and methods are exemplary only for the purpose of illustrating the inventive principles of the invention. Many other embodiments are possible and such alternate embodiments and methods will readily suggest themselves to such skilled persons after reading this disclosure and examining the accompanying drawing. Thus the disclosed embodiments are exemplary only and the present invention is not to be limited in any way except by the appended claims.

Drawing figures in this specification, particularly diagrams illustrating semiconductor structures, are drawn to facilitate understanding through clarity of presentation and are not drawn to scale. In the semiconductor structures illustrated, there are two different conductivity types: p-type where the majority charge carriers are positively charged holes that typically migrate along the semiconductor valence band in the presence of an electric field, and n-type where the majority charge carriers are negatively charged electrons that typically migrate along the conduction band in the presence of an electric field. Dopants are typically introduced into an intrinsic semiconductor (where the quantity of holes and electrons are equal and the ability to conduct electric current is low: much better than in an insulator, but far worse than in a region doped to be conductive—hence the “semi-” in “semiconductor”) to create one of the conductivity types.

›DETAILED DESCRIPTION · 16 of 64

When dopant atoms capable of accepting another electron (known and “acceptors”) are introduced into the semiconductor lattice, the “hole” where an electron can be accepted becomes a positive charge carrier. When many such atoms are introduced, the conductivity type becomes p-type and the holes resulting from the electrons being “accepted” are the majority charge carriers. Similarly, when dopant atoms capable of donating another electron (known and “donors”) are introduced into the semiconductor lattice, the donated electron becomes a negative charge carrier. When many such atoms are introduced, the conductivity type becomes n-type and the “donated” electrons are the majority charge carriers.

As is well known in the art, the quantities of dopant atoms used can vary widely over orders of magnitude of final concentration as a matter of design choice. However it is the nature of the majority carries and not their quantity that determines if the material is p-type or n-type. Sometimes in the art, heavily, medium, and lightly doped p-type material is designated p+, p and p− respectively while heavily, medium, and lightly doped n-type material is designated n+, n and n− respectively. Unfortunately, there are no precise definitions of when a “+” or a “−” is an appropriate qualifier, so to avoid overcomplicating the disclosure the simple designations p-type and n-type abbreviated “p” or “n” respectively are used without qualifiers throughout this disclosure. Persons of ordinary skill in the art will appreciate that there are many considerations that contribute to the choice of doping levels in any particular embodiment as a matter of design choice.

Numerous different exemplary embodiments are presented. In many of them there are common characteristics, features, modes of operation, etc. When like reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.

FIGS. 35 A through 35 E illustrate an embodiment of a gated half transistor FBC DRAM memory cell according to the present invention. FIG. 35 A shows a top view of an embodiment of a partial memory array including memory cell 250 (shown by a dotted line) and FIG. 35 B shows memory cell 250 in isolation. FIGS. 35 C and 35 D show the memory cell 250 cross sections along the I-I′ line and II-II′ cut lines, respectively, while FIG. 35 E shows a method for electrically contacting the buried well and substrate layers beneath the cell.

Referring to FIGS. 35 C and 35 D together, the cell 250 includes a substrate 12 of a first conductivity type such as a p-type, for example. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In other embodiments, substrate 12 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIGS. 35 C and 35 D .

A buried layer 22 of a second conductivity type such as n-type, for example, is provided in the substrate 12 . Buried layer 22 may be formed by an ion implantation process on the material of substrate 12 . Alternatively, buried layer 22 can also be grown epitaxially on top of substrate 12 .

A floating body region 24 of the first conductivity type, such as p-type, for example, is bounded on top by bit line region 16 and insulating layer 62 , on the sides by insulating layers 26 and 28 , and on the bottom by buried layer 22 . Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 22 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments, as a matter of design choice.

Insulating layers 26 and 28 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 and 28 insulate cell 250 from neighboring cells 250 when multiple cells 250 are joined in an array 280 to make a memory device as illustrated in FIGS. 38 A- 38 C . Insulating layer 26 insulates both body region 24 and buried region 22 of adjacent cells (see FIG. 35 C ), while insulating layer 28 insulates neighboring body region 24 , but not the buried layer 22 , allowing the buried layer 22 to be continuous (i.e. electrically conductive) in one direction (along the II-II′ direction as shown in FIG. 35 D ). This connecting of adjacent memory cells together through buried layer 22 forming a source line beneath adjacent memory cells 250 allows the elimination of a contacted source/drain region or an adjacent contacted plug inside the memory cell required in memory cells of the prior art. As can be seen in FIGS. 35 A and 35 B , there is no contact to the buried layer 22 at the semiconductor surface inside the boundary of memory cell 250 .

A bit line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body region 24 and is exposed at surface 14 . Bit line region 16 is formed by an implantation process formed on the material making up substrate 12 , according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to form bit line region 16 .

›DETAILED DESCRIPTION · 17 of 64

A gate 60 is positioned in between the bit line region 16 and insulating layer 26 and above the floating body region 24 . The gate 60 is insulated from floating body region 24 by an insulating layer 62 . Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Cell 250 further includes word line (WL) terminal 70 electrically connected to gate 60 , bit line (BL) terminal 74 electrically connected to bit line region 16 , source line (SL) terminal 72 electrically connected to buried layer 22 , and substrate terminal 78 electrically connected to substrate 12 .

As shown in FIG. 35 E , contact between SL terminal 72 and buried layer 22 can be made through region 20 having a second conductivity type, and which is electrically connected to buried well region 22 , while contact between substrate terminal 78 and substrate region 12 can be made through region 21 having a first conductivity type, and which is electrically connected to substrate region 12 .

The SL terminal 72 connected to the buried layer region 22 serves as a back bias terminal, i.e. a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor coupled to the body or bulk of the device corresponding to region 82 in transistor 100 of FIG. 90 A or region 94 A in transistor 100 A in FIG. 90 B . In a floating body DRAM cell, a conductive coupling to the floating body would be counterproductive since it would cease to be a floating body with such a connection. In some embodiments, the p-n junction between the floating body 24 and the buried well 22 coupled to the source line terminal 72 is forward biased to be conductive by applying a negative voltage to the source line terminal 72 . In some embodiments, the SL terminal is biased to a positive voltage potential to maintain the charge in the floating body region 24 . In some embodiments, the source line terminal 72 is used in a manner similar to the source line in floating body DRAM cells of the prior art. Thus in various embodiments SL terminal 72 may be used in a manner similar to a back bias terminal, or it may be used like a source line, or it may be used for another purpose entirely. In some embodiments it may be used in two or more of these ways in different operations. Thus both the terms “source line terminal” and “back bias terminal” are used interchangeably in this specification and should be deemed equivalent.

Comparing the structure of the memory device 250 , for example, as shown in FIG. 35 C to the structure of transistor devices 100 , 100 A and 100 B in FIGS. 90 A through 90 C , it can be seen that the memory device of present invention constitutes a smaller structure relative to the MOSFET devices 100 , 100 A and 100 B, where only one region of a second conductivity type is present at the surface of the silicon substrate. Thus, memory cell 250 of the present invention provides an advantage that it consists of only one region of second conductivity at the surface (i.e. bit line region 16 as opposed to regions 84 and 86 or regions 84 A and 86 A) and hence requires only one contact per memory cell 250 (i.e. to create a connection between bit line region 16 and terminal 74 ).

Persons of ordinary skill in the art will appreciate that in FIGS. 35 A through 35 E and that the first and second conductivity types can be reversed in memory cell 250 as a matter of design choice and that the labeling of regions of the first conductivity type as p-type and the second conductivity type as p-type is illustrative only and not limiting in any way. Thus the first and second conductivity types can be p-type and n-type respectively in some embodiments of memory cell 50 and be n-type and p-type respectively in other embodiments. Further, such skilled persons will realize that the relative doping levels of the various regions of either conductivity type will also vary as a matter of design choice, and that there is no significance to the absence of notation signifying higher or lower doping levels such as p+ or p− or n+ or n− in any of the diagrams.

A method of manufacturing memory cell 250 will be described with reference to FIGS. 36 A through 36 U . These 21 figures are arranged in groups of three related views, with the first figure of each group being a top view, the second figure of each group being a vertical cross section of the top view in the first figure of the group designated I-I′, and the third figure of each group being a horizontal cross section of the top view in the first figure of the group designated II-II′. Thus FIGS. 36 A, 36 D, 36 G, 36 J, 36 M, 36 P and 36 S are a series of top views of the memory cell 50 at various stages in the manufacturing process, FIGS. 36 B, 36 E, 36 H, 36 K, 36 N, 36 Q and 36 T are their respective vertical cross sections labeled I-I′, and FIGS. 36 C, 36 F, 36 I, 36 L, 36 O, 36 R and 36 U are their respective horizontal cross sections labeled II-II′. Identical reference numbers from FIGS. 35 A through 35 E appearing in FIGS. 36 A through 36 U represent similar, identical or analogous structures as previously described in conjunction with the earlier drawing figures. Here “vertical” means running up and down the page in the top view diagram and “horizontal” means running left and right on the page in the top view diagram. In a physical embodiment of memory cell 50 , both cross sections are vertical with respect to the surface of the semiconductor device.

Turning now to FIGS. 36 A through 36 C , the first steps of the process are seen. In an exemplary 130 nanometer (nm) process a thin silicon oxide layer 102 with a thickness of about 100 A may be grown on the surface of substrate 12 . This may be followed by a deposition of about 200 A of polysilicon layer 104 . This in turn may be followed by deposition of about 1200 A silicon nitride layer 106 . Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other numbers of, thicknesses of, and combinations of protective layers 102 , 104 and 106 may be used as a matter of design choice.

›DETAILED DESCRIPTION · 18 of 64

As shown in FIGS. 36 D through 36 F , a pattern opening the areas to become trench 108 may be formed using a lithography process. Then the silicon oxide 102 , polysilicon 104 , silicon nitride 106 layers may be subsequently patterned using the lithography process and then may be etched, followed by a silicon etch process, creating trench 108 .

As shown in FIGS. 36 G through 36 I , a pattern opening the areas to become trenches 112 may be formed using a lithography process, which may be followed by etching of the silicon oxide 102 , polysilicon 104 , silicon nitride layers 106 , and a silicon trench etch process, creating trench 112 . The trench 112 is etched such that the trench depth is deeper than that of trench 108 . In an exemplary 130 nm process, the trench 108 depth may be about 1000 A and the trench 112 depth may be about 2000 A. Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other trench depths may be used as a matter of design choice.

As shown in FIGS. 36 J through 36 L , this may be followed by a silicon oxidation step, which will grow silicon oxide films in trench 108 and trench 112 which will become insulating layers 26 and 28 . In an exemplary 130 nm process, about 4000 A silicon oxide nay be grown. A chemical mechanical polishing step can then be performed to polish the resulting silicon oxide films so that the silicon oxide layer is flat relative to the silicon surface. A silicon dry etching step can then be performed so that the remaining silicon oxide layer height of insulating layers 26 and 28 may be about 300 A from the silicon surface. In other embodiments the top of insulating layers 26 and 28 may be flush with the silicon surface. The silicon nitride layer 106 and the polysilicon layer 104 may then be removed which may then be followed by a wet etch process to remove silicon oxide layer 102 (and a portion of the silicon oxide films formed in the area of former trench 108 and former trench 112 ). Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other insulating layer materials, heights, and thicknesses as well as alternate sequences of processing steps may be used as a matter of design choice.

As shown in FIGS. 36 M through 36 O , an ion implantation step may then be performed to form the buried layer region 22 of a second conductivity (e.g. n-type conductivity). The ion implantation energy is optimized such that the buried layer region 22 is formed shallower than the bottom of the insulating layer 26 and deeper than the bottom of insulating layer 28 . As a result, the insulating layer 26 isolates buried layer region 22 between adjacent cells while insulating layer 28 does not isolate buried layer region 22 between cells. This allows buried layer region 22 to be continuous in the direction of the II-II′ cross section. Buried layer 22 isolates the eventual floating body region 24 of the first conductivity type (e.g., p-type) from the substrate 12 .

As shown in FIGS. 36 P through 36 R , a silicon oxide or high-dielectric material gate insulation layer 62 may then be formed on the silicon surface (e.g. about 100 A in an exemplary 130 nm process), which may then be followed by a polysilicon or metal gate 60 deposition (e.g. about 500 A in an exemplary 130 nm process). A lithography step may then be performed to pattern the layers 62 and 60 , which may then be followed by etching of the polysilicon and silicon oxide layers. Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other gate and gate insulation materials with different thicknesses may be used a matter of design choice.

As shown in FIGS. 36 S through 36 U , another ion implantation step may then be performed to form the bit line region 16 of a second conductivity type (e.g. n-type conductivity). This may then be followed by backend process to form contact and metal layers (not shown in FIGS. 36 A through 36 U ). The gate 60 and the insulating layers 26 and 28 serve as masking layer for the implantation process such that regions of second conductivity are not formed outside bit line region 16 . In this and many subsequent figures, gate layer 60 and gate insulating layer 62 are shown flush with the edge of insulating layer 26 . In some embodiments, gate layer 60 and gate insulating layer 62 may overlap insulating layer 16 to prevent any of the implant dopant for bit line region 16 from inadvertently implanting between gate layer 60 and gate insulating layer 62 and the adjacent insulating layer 26 .

The states of memory cell 250 are represented by the charge in the floating body 24 . If cell 250 is positively charged due to holes stored in the floating body region 24 , then the memory cell will have a lower threshold voltage (the gate voltage where an ordinary MOSFET transistor is turned on—or in this case, the voltage at which an inversion layer is formed under gate insulating layer 62 ) compared to if cell 250 does not store holes in body region 24 .

The positive charge stored in the floating body region 24 will decrease over time due to the diode leakage current of the p-n junctions formed between the floating body 24 and bit line region 16 and between the floating body 24 and the buried layer 22 and due to charge recombination. A unique capability of the invention is the ability to perform the holding operation in parallel to all memory cells of the array.

As shown in FIG. 37 A , the holding operation can be performed by applying a positive back bias to buried layer 22 through the SL terminal 72 while simultaneously grounding the bit line region 16 through the BL terminal 74 and grounding the substrate 12 through substrate terminal 78 . The positive back bias applied to the buried layer region connected to the SL terminal will maintain the state of the memory cell 250 that it is connected to. The holding operation is relatively independent of the voltage applied to gate 60 through word line terminal 70 . In some embodiments of the invention, the word line terminal may be grounded. Inherent in the memory cell 250 is n-p-n bipolar device 30 formed by buried well region 22 (the collector region), floating body 24 (the base region), and bit line region 16 (the emitter region).

›DETAILED DESCRIPTION · 19 of 64

If floating body 24 is positively charged, a state corresponding to logic-1, the bipolar transistor 30 formed by bit line region 16 , floating body 24 , and buried well region 22 will be turned on due to an impact ionization mechanism like that described with reference to Lin cited above. In particular, the voltage across the reversed biased p-n junction between the floating body 24 and the buried well region 22 will cause a small current to flow across the junction. Some of the current will be in the form of hot carriers accelerated by the electric field across the junction. These hot carriers will collide with atoms in the semiconductor lattice which will generate hole-electron pairs in the vicinity of the junction. The electrons will be swept into the buried layer region 22 by the electric field, while the holes will be swept into the floating body region 24 .

The hole current flowing into the floating region 24 (usually referred to as the base current) will maintain the logic-1 state data. The efficiency of the holding operation can be enhanced by designing the bipolar device formed by buried well region 22 , floating region 24 , and bit line region 16 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of SL terminal 72 to the base current flowing into the floating region 24 .

FIG. 37 B shows the energy band diagram of the intrinsic n-p-n bipolar device 30 when the floating body region 24 is positively charged and a positive bias voltage is applied to the buried well region 22 . The dashed lines indicate the Fermi levels in the various regions of the n-p-n transistor 30 . The Fermi level is located in the band gap between the solid line 17 indicating the top of the valance band (the bottom of the band gap) and the solid line 19 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. The positive charge in the floating body region lowers the energy barrier of electron flow into the base region. Once injected into the floating body region 24 , the electrons will be swept into the buried well region 22 (connected to SL terminal 72 ) due to the positive bias applied to the buried well region 22 . As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into the SL terminal 72 while the resulting hot holes will subsequently flow into the floating body region 24 . This process restores the charge on floating body 24 and will maintain the charge stored in the floating body region 24 which will keep the n-p-n bipolar transistor 30 on for as long as a positive bias is applied to the buried well region 22 through SL terminal 72 .

If floating body 24 is neutrally charged (the voltage on floating body 24 being equal to the voltage on grounded bit line region 16 ), a state corresponding to logic-0, no current will flow through the n-p-n transistor 30 . The bipolar device 30 will remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.

FIG. 37 C shows the energy band diagram of the intrinsic n-p-n bipolar device 30 when the floating body region 24 is neutrally charged and a bias voltage is applied to the buried well region 22 . In this state the energy level of the band gap bounded by solid lines 17 A and 19 A is different in the various regions of n-p-n bipolar device 30 . Because the potential of the floating body region 24 and the bit line region 16 is equal, the Fermi levels are constant, resulting in an energy barrier between the bit line region 16 and the floating body region 24 . Solid line 23 indicates, for reference purposes, the energy barrier between the bit line region 16 and the floating body region 24 . The energy barrier prevents electron flow from the bit line region 16 (connected to BL terminal 74 ) to the floating body region 24 . Thus the n-p-n bipolar device 30 will remain off.

The difference between an impact ionization write logic-1 operation as described with reference to Lin cited above and a holding operation is that during a holding operation the gate 60 is not biased at a higher voltage than normal during a holding operation. During a write logic-1 operation, the capacitive coupling from the gate 60 to the floating body region 24 forces the n-p-n bipolar device 30 on regardless of the data stored in the cell. By contrast, without the gate boost a holding operation only generates carriers through impact ionization when a memory cell stores a logic-1 and does not generate carries through impact ionization when a memory cell stores a logic-0.

In the embodiment discussed in FIGS. 37 A through 37 C , bipolar device 30 has been an n-p-n transistor. Persons of ordinary skill in the art will readily appreciate that by reversing the first and second connectivity types and inverting the relative values of the applied voltages memory cell 50 could comprise a bipolar device 30 which is a p-n-p transistor. Thus the choice of an n-p-n transistor is an illustrative example for simplicity of explanation in FIGS. 37 A through 37 C is not limiting in any way.

FIG. 38 A shows an exemplary array 280 of memory cells 250 (four exemplary instances of memory cell 250 being labeled as 250 a , 250 b , 250 c and 250 d ) arranged in rows and columns. In many, but not all, of the figures where exemplary array 280 appears, representative memory cell 250 a will be representative of a “selected” memory cell 250 when the operation being described has one (or more in some embodiments) selected memory cells 250 . In such figures, representative memory cell 250 b will be representative of an unselected memory cell 250 sharing the same row as selected representative memory cell 250 a , representative memory cell 250 c will be representative of an unselected memory cell 250 sharing the same column as selected representative memory cell 250 a , and representative memory cell 250 d will be representative of a memory cell 250 sharing neither a row or a column with selected representative memory cell 250 a.

›DETAILED DESCRIPTION · 20 of 64

Present in FIG. 38 A are word lines 70 a through 70 n , source lines 72 a through 72 n , bit lines 74 a through 74 p , and substrate terminal 78 . Each of the word lines 70 a through 70 n is associated with a single row of memory cells 250 and is coupled to the gate 60 of each memory cell 250 in that row. Similarly, each of the source lines 72 a through 72 n is associated with a single row of memory cells 50 and is coupled to the buried well region 22 of each memory cell 50 in that row. Each of the bit lines 74 a through 74 p is associated with a single column of memory cells 50 and is coupled to the bit line region 16 of each memory cell 50 in that column. In the holding operation described in FIGS. 37 A through 37 C , there is no individually selected memory cell. Rather cells are selected in rows by the source lines 72 a through 72 n and may be selected as individual rows, as multiple rows, or as all of the rows comprising array 280 .

Substrate 12 is present at all locations under array 280 . Persons of ordinary skill in the art will appreciate that one or more substrate terminals 78 will be present in one or more locations as a matter of design choice. Such skilled persons will also appreciate that while exemplary array 280 is shown as a single continuous array in FIG. 38 A , that many other organizations and layouts are possible like, for example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, the array 280 may be broken into two or more sub-arrays, control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed around exemplary array 280 or inserted between sub-arrays of array 280 . Thus the exemplary embodiments, features, design options, etc., described are not limiting in any way.

Turning now to FIG. 38 B , array 280 previously discussed is shown along with multiplexers 40 a through 40 n and voltage waveforms 42 a through 42 n . A periodic pulse of positive voltage can be applied to the back bias terminals of memory cells 250 through SL terminal 72 as opposed to applying a constant positive bias to reduce the power consumption of the memory cell 250 . FIG. 38 B further shows multiplexers 40 a through 40 n each coupled to one of the source lines 72 a through 72 n that determine the bias voltages applied to SL terminals 72 a through 72 n , which will be determined by different operating modes. The pulsing of the voltage on the SL terminals may be controlled, for example, by applying pulses of logic signals like waveforms 42 a through 42 n to the select input of multiplexers 40 a through 40 n thereby selecting, for example, ground (0.0 volts) or a power supply voltage such as Vcc. Many other techniques may be used to pulse the voltage applied to SL terminals 72 a through 72 n like, for example, applying the waveforms 42 a through 42 n at different times, or applying them simultaneously, or coupling the select inputs of multiplexers 42 a through 42 n together and applying a single pulsed waveform to all of the multiplexers 42 a through 42 n simultaneously (not shown in the figure). Many other options will readily suggest themselves to persons of ordinary skill in the art. Thus the described exemplary embodiments are not limiting in any way.

FIG. 38 C shows another method to provide voltage pulses to SL terminals 72 a through 72 n of exemplary array 280 of memory cells 250 . The positive input signals to multiplexers 40 a through 40 n may be generated by voltage generator circuits 44 a through 44 n coupled to one input of each of the multiplexers 40 a through 40 n . Alternatively, a single voltage generator circuit may be coupled to each of the multiplexers 40 a through 40 n reducing the amount of overhead circuitry required to refresh the memory cells 250 of array 280 . Other embodiments are possible including, for example, applying the waveforms 42 a through 42 n at different times, or applying them simultaneously, or coupling the select inputs of multiplexers 42 a through 42 n together and applying a single pulsed waveform to all of the multiplexers 42 a through 42 n simultaneously (not shown in the figure).

FIG. 38 D shows a reference generator circuit suitable for use as reference generator circuits 44 a through 44 n in FIG. 38 C . The reference generator includes reference cell 53 , which consists of a modified version of Gated half transistor memory cell 250 described above with region 25 of the first conductivity type (p-type conductivity). The p-type 25 region allows for a direct sensing of the floating body region 24 potential. Region 25 is drawn separately even though it has the same conductivity type as floating body region 24 because it may be doped differently to facilitate contacting it. The reference cell 53 for example can be configured to be in state logic-1 where the potential of the floating body region 24 is positive, for example at +0.5V. The potential sensed through the p-type region is then compared with a reference value V REF , e.g. +0.5V, by operational amplifier 27 . If the potential of the floating body region 24 is less than the reference value, the voltage applied to the back bias terminal 72 (which is connected to buried region 22 of the reference cell 53 and can also be connected to buried region 22 of the Gated half transistor memory cell 250 ) is increased by operational amplifier 27 until the potential of the floating body region 24 reaches the desired reference voltage. If the potential of the floating body 24 region is higher than that of the reference value, the voltage applied to back bias terminal 72 can be reduced by operational amplifier 27 until the potential of the floating body region 24 reaches the desired reference voltage. Reference voltage V REF may be generated in many different ways like, for example, using a band gap reference, a resistor string, a digital-to-analog converter, etc. Similarly alternate voltage generators of types known in the art may be used

›DETAILED DESCRIPTION · 21 of 64

As shown in FIG. 39 , the holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floating body 24 . Without the holding/standby operation, the maximum potential that can be stored in the floating body 24 is limited to the flat band voltage V FB as the junction leakage current from floating body 24 to bit line region 16 increases exponentially at floating body potential greater than V FB . However, by applying a positive voltage to SL terminal 72 , the bipolar action results in a hole current flowing into the floating body 24 , compensating for the junction leakage current between floating body 24 and bit line region 16 . As a result, the maximum charge V MC stored in floating body 24 can be increased by applying a positive bias to the SL terminal 72 as shown in the graph in FIG. 39 . The increase in the maximum charge stored in the floating body 24 results in a larger memory window.

The holding/standby operation can also be used for multi-bit operation in memory cell 250 . To increase the memory density without increasing the area occupied by the memory cell, a multi-level operation is typically used. This is done by dividing the overall memory window into more than two different levels. In one embodiment four levels representing two binary bits of data are used, though many other schemes like, for example, using eight levels to represent three binary bits of data are possible. In a floating body memory, the different memory states are represented by different charge in the floating body 24 , as described, for example, in Tack and Oknonin-2 cited above. However, since the state with zero charge in the floating body 24 is the most stable state, the floating body 24 will over time lose its charge until it reaches the most stable state. In multi-level operation, the difference of charge representing different states is smaller than a single-level operation. As a result, a multi-level memory cell is more sensitive to charge loss.

FIG. 40 shows the floating body 24 net current for different floating body 24 potential as a function of the voltage applied to SL terminal 72 with BL, WL and substrate terminals 74 , 70 , and 78 , grounded. When zero voltage is applied to SL terminal 72 , no bipolar current is flowing into the floating body 24 and as a result, the stored charge will leak over time. When a positive voltage is applied to SL terminal 72 , hole current will flow into floating body 24 and balance the junction leakage current to bit line region 16 . The junction leakage current is determined by the potential difference between the floating body 24 and bit line region 16 , while the bipolar current flowing into floating body 24 is determined by both the SL terminal 72 potential and the floating body 24 potential. As indicated in FIG. 40 , for different floating body potentials, at a certain SL terminal 72 potential V HOLD , the current flowing into floating body 24 is balanced by the junction leakage between floating body 24 and bit line region 16 . The different floating body 24 potentials represent different charges used to represent different states of memory cell 50 . This shows that different memory states can be maintained by using the holding/standby operation described here.

In one embodiment the bias condition for the holding operation for memory cell 250 is: 0 volts is applied to BL terminal 74 , a positive voltage like, for example, +1.2 volts is applied to SL terminal 72 , 0 volts is applied to WL terminal 70 , and 0 volts is applied to the substrate terminal 78 . In another embodiment, a negative voltage may be applied to WL terminal 70 . In other embodiments, different voltages may be applied to the various terminals of memory cell 250 as a matter of design choice and the exemplary voltages described are not limiting in any way.

The read operation of the memory cell 250 and array 280 of memory cells will described in conjunction with FIGS. 41 and 42 A through 42 H . Any sensing scheme known in the art can be used with memory cell 250 . Examples include, for example, the sensing schemes disclosed in Ohsawa-1 and Ohsawa-2 cited above.

The amount of charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 250 . If memory cell 250 is in a logic-1 state having holes in the body region 24 , then the memory cell will have a higher cell current (e.g. current flowing from the BL terminal 74 to SL terminal 72 ), compared to if cell 250 is in a logic-0 state having no holes in floating body region 24 . A sensing circuit typically connected to BL terminal 74 can then be used to determine the data state of the memory cell.

A read operation may be performed by applying the following bias condition to memory cell 250 : a positive voltage is applied to the selected BL terminal 74 , and an even more positive voltage is applied to the selected WL terminal 70 , zero voltage is applied to the selected SL terminal 72 , and zero voltage is applied to the substrate terminal 78 . This has the effect of operating bipolar device 30 as a backward n-p-n transistor in a manner analogous to that described for operating bipolar device 30 for a hold operation as described in conjunction with FIGS. 37 A through 37 C . The positive voltage applied to the WL terminal 70 boosts the voltage on the floating body region 24 by means of capacitive coupling from the gate 60 to the floating body region 24 through gate insulating layer 62 . This has the effect of increasing the current in bipolar device 30 when it is on significantly more than it increases the current when it is off, thus making it easier to sense the data stored in the memory cell 250 . The optimal bias voltage to apply to WL terminal 70 will vary from embodiment to embodiment and process to process. The actual voltage applied in any given embodiment is a matter of design choice.

FIG. 41 shows array 280 of memory cells 250 during a read operation in one exemplary embodiment of the present invention. Reading a memory cell 250 in array 280 is more complicated than reading a single cell as described above, since cells are coupled together along rows by word lines 70 a through 70 n and source lines 72 a through 72 n and coupled together along columns by bit lines 74 a through 74 p . In one exemplary embodiment, about 0.0 volts is applied to the selected SL terminal 72 a , about +0.4 volts is applied to the selected bit line terminal 74 a , about +1.2 volts is applied to the selected word line terminal 70 a , and about 0.0 volts is applied to substrate terminal 78 . All the unselected bit line terminals 74 b (not shown) through 74 p have 0.0 volts applied, the unselected word line terminals 70 b (not shown) through 70 n have 0.0 volts applied, and the unselected SL terminals 72 b (not shown) have +1.2 volts applied. FIG. 41 shows the bias conditions for the selected representative memory cell 250 a and three unselected representative memory cells 250 b , 250 c , and 250 d in memory array 280 , each of which has a unique bias condition. Persons of ordinary skill in the art will appreciate that other embodiments of the invention may employ other combinations of applied bias voltages as a matter of design choice. Such skilled persons will also realize that the first and second conductivity types may be reversed and the relative bias voltages may be inverted in other embodiments.

›DETAILED DESCRIPTION · 22 of 64

FIG. 42 A also shows the bias condition of the selected representative memory cell 250 a in cross section while FIG. 42 B shows the equivalent circuit diagram illustrating the intrinsic n-p-n bipolar device 30 under the read bias conditions described above.

The three cases for unselected memory cells 250 during read operations are shown in FIGS. 42 C, 42 E, and 42 G , while illustrations of the equivalent circuit diagrams are shown in FIGS. 42 D, 42 F, and 42 H respectively. The bias conditions for memory cells 250 sharing the same row (e.g. representative memory cell 250 b ) and those sharing the same column (e.g., representative memory cell 250 c ) as the selected representative memory cell 250 a are shown in FIGS. 42 C- 42 D and FIGS. 42 E- 42 F , respectively, while the bias condition for memory cells 250 not sharing the same row nor the same column as the selected representative memory cell 250 a (e.g., representative memory cell 250 d ) is shown in FIG. 42 G- 42 H .

As shown in FIGS. 42 C and 42 D , for representative memory cell 250 b sharing the same row as the selected representative memory cell 250 a , the SL terminal 72 a is now grounded and consequently these cells will not be at the holding mode. However, because a read operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the hole charge in the floating body 24 (on the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.

As shown in FIGS. 42 E and 42 F , representative memory cell 250 c sharing the same column as the selected memory cell 250 a , a positive voltage is applied to the BL terminal 74 a . Less base current will flow into the floating body 24 due to the smaller potential difference between SL terminal 72 n and BL terminal 74 a (i.e. the emitter and collector terminals of the n-p-n bipolar device 30 ). However, because read operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (on the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.

As shown in FIGS. 42 G and 42 H , representative memory cell 250 d sharing neither the same row nor the same column as the selected representative memory cell 250 a , the SL terminal 72 n will remain positively charged and the BL terminal 74 p will remain grounded. As can be seen, these cells will be in the holding mode, where memory cells in the logic-1 state will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 and memory cells in the logic-0 state will remain in neutral state.

The read operation of the memory cell 250 and array 280 of memory cells have been described in conjunction with FIGS. 41 through 42 H . Persons of ordinary skill in the art will realize that the drawing figures are not drawn to scale, that the various voltages described are illustrative only and will vary from embodiment to embodiment, that embodiments discussed have been illustrative only, and that many more embodiments employing the inventive principles of the invention are possible. For example, the two conductivity types may be reversed and the relative voltages of the various signals may be inverted, the memory array 280 may be built as a single array or broken into sub-arrays, the accompanying control circuits may be implemented in different ways, different relative or absolute voltage values may be applied to memory cell 250 or array 280 , etc. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.

A first type of write logic-0 operation of an individual memory cell 250 is now described with reference to FIGS. 43 A and 43 B . In FIG. 43 A , a negative voltage bias is applied to the back bias terminal (i.e. SL terminal 72 ), a zero voltage bias is applied to WL terminal 70 , a zero voltage bias is applied to BL terminal 72 and substrate terminal 78 . Under these conditions, the p-n junction between floating body 24 and buried well 22 of the selected cell 250 is forward-biased, evacuating any holes from the floating body 24 . In one particular non-limiting embodiment, about −0.5 volts is applied to source line terminal 72 , about 0.0 volts is applied to word line terminal 70 , and about 0.0 volts is applied to bit line terminal 74 and substrate terminal 78 . These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.

In FIG. 43 B , an alternative embodiment of memory cell 250 is shown where substrate 12 is replaced by region 12 A of the first conductivity type (p-type in the figure) which is a well inside substrate 29 of the second conductivity type (n-type in the figure). This arrangement overcomes an undesirable side effect of the embodiment of FIG. 43 A where lowering the buried well region 22 voltage on buried well terminal 72 to approximately −0.5V to forward bias the p-n junction between buried well 22 and floating body 24 also forward biases the p-n junction between buried well 22 and substrate 12 resulting in unwanted substrate current. The embodiment of FIG. 43 B allows the well 12 A to be lowered by applying the same voltage to well terminal 78 as buried layer terminal 72 thus preventing the p-n diode between those regions to forward bias. The substrate 29 is preferably biased to 0.0V through substrate terminal 31 as shown in FIG. 43 B . These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice, Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.

FIG. 44 shows an example of bias conditions for the selected and unselected memory cells 250 during the first type of write logic-0 operation (as described in FIG. 43 A ) in memory array 280 . For the selected representative memory cells 250 a and 250 b , the negative bias applied to SL terminal 72 a causes large potential difference between floating body 24 and buried well region 22 . Because the buried well 22 is shared among multiple memory cells 250 , logic-0 will be written into all memory cells 250 including memory cells 250 a and 250 b sharing the same SL terminal 72 a simultaneously.

›DETAILED DESCRIPTION · 23 of 64

FIGS. 45 A through 45 B illustrate an example of bias conditions and an equivalent circuit diagram illustrating the intrinsic n-p-n bipolar devices 30 of unselected memory cells 250 like representative memory cells 250 c and 250 d in array 280 during the first type of logic-0 write operations. In particular representative memory cell 250 d will be discussed for clarity of presentation though the principles apply to all unselected memory cells 250 . Since the logic-0 write operation only involves a negative voltage to the selected SL terminal 72 a , the memory cells 250 coupled to the unselected SL terminals 72 b (not shown in FIG. 44 ) through 72 n are placed in a holding operation by placing a positive bias condition on SL terminals 72 b through 72 n . As can be seen in FIGS. 45 A and 45 B , the unselected memory cells will be in a holding operation, with the BL terminal at about 0.0 volts, WL terminal at zero voltage, and the unselected SL terminal positively biased.

As shown in FIG. 46 , a second type of write logic-0 operation can also be performed by applying a negative bias to the BL terminal 74 as opposed to the SL terminal 72 . In FIG. 46 , the selected memory cells 250 include representative memory cells 250 a and 250 c and all the memory cells 250 that share the selected bit line 74 a . The SL terminal 72 will be positively biased, while zero voltage is applied to the substrate terminal 78 , and zero voltage is applied to the WL terminal 70 . Under these conditions, all memory cells sharing the same BL terminal 74 will be written to the logic-0 state.

The first and second types of write logic-0 operations referred to above each has a drawback that all memory cells 250 sharing either the same SL terminal 72 (the first type—row write logic-0) or the same BL terminal 74 will (the second type—column write logic-0) be written to simultaneously and as a result, does not allow writing logic-0 to individual memory cells 250 . To write arbitrary binary data to different memory cells 250 , a write logic-0 operation is first performed on all the memory cells to be written followed by one or more write logic-1 operations on the bits that must be written to logic-1.

A third type of write logic-0 operation that allows for individual bit writing can be performed on memory cell 250 by applying a positive voltage to WL terminal 70 , a negative voltage to BL terminal 74 , zero or positive voltage to SL terminal 72 , and zero voltage to substrate terminal 78 . Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70 . As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74 , the p-n junction between 24 and bit line region 16 is forward-biased, evacuating any holes from the floating body 24 .

To reduce undesired write logic-0 disturb to other memory cells 250 in the memory array 280 , the applied potential can be optimized as follows: if the floating body 24 potential of state logic-1 is referred to as V FB1 , then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V FB1 /2 while −V FB1 /2 is applied to BL terminal 74 . Additionally, either ground or a slightly positive voltage may also be applied to the BL terminals 74 of unselected memory cells 250 that do not share the same BL terminal 74 as the selected memory cell 250 , while a negative voltage may also be applied to the WL terminals 70 of unselected memory cells 250 that do not share the same WL terminal 70 as the selected memory cell 250 .

As illustrated in FIG. 47 , the following bias conditions are applied to the selected representative memory cell 250 a in exemplary memory array 280 to perform an individual write logic-0 operation exclusively in representative memory cell 250 a : a potential of about 0.0 volts to SL terminal 72 a , a potential of about −0.2 volts to BL terminal 74 a , a potential of about +0.5 volts is applied to word line terminal 70 a , and about 0.0 volts is applied to substrate terminal 78 . In the rest of array 280 about +1.2 volts is applied to unselected SL terminals 72 (including SL terminal 72 n ), about 0.0 volts (or possibly a slightly positive voltage) is applied to unselected BL terminals 74 (including BL terminal 74 p ), and about 0.0 volts is applied to unselected WL terminal 70 (including WL terminal 70 n ). Persons of ordinary skill in the art will appreciate that the voltage levels in FIG. 47 are illustrative only and that different embodiments will have different voltage levels as a matter of design choice.

The bias conditions shown in FIG. 47 of the selected representative memory cell 250 a in memory array 280 to perform the individual bit write logic-0 operation are further illustrated in FIGS. 48 A and 48 B . As discussed above, the potential difference between floating body 24 and bit line region 16 connected to BL terminal 74 a is now increased due to the capacitive coupling from raising WL terminal 70 a from ground to +0.5V, resulting in a higher forward bias current than the base hole current generated by the n-p-n bipolar device 30 formed by buried well region 22 connected to SL terminal 72 a , floating body 24 , and bit line region 16 . The result is that holes will be evacuated from floating body 24 .

The unselected memory cells 250 in memory array 280 under the bias conditions of FIG. 47 during the individual bit write logic-0 operation are shown in FIGS. 48 C through 48 H . The bias conditions for memory cells sharing the same row (e.g. representative memory cell 250 b ) as the selected representative memory cell 250 a are illustrated in FIGS. 48 C and 48 D , and the bias conditions for memory cells sharing the same column (e.g. representative memory cell 250 c ) as the selected representative memory cell 250 a are shown in FIGS. 48 E and 48 F , and the bias conditions for memory cells sharing neither the same row nor the same column (e.g. representative memory cell 250 d ) as the selected representative memory cell 250 a are shown in FIGS. 48 G and 48 H .

›DETAILED DESCRIPTION · 24 of 64

As shown in FIGS. 48 C and 48 D , the floating body 24 potential of memory cell 250 b sharing the same row as the selected representative memory cell 250 a will increase due to capacitive coupling from WL terminal 70 by ΔV FB . For memory cells in state logic-0, the increase in the floating body 24 potential is not sustainable as the forward bias current of the p-n diodes formed by floating body 24 and junction 16 will evacuate holes from floating body 24 . As a result, the floating body 24 potential will return to the initial state logic-0 equilibrium potential. For memory cells in state logic-1, the floating body 24 potential will initially also increase by ΔV FB , which will result in holes being evacuated from floating body 24 . After the positive bias on the WL terminal 70 is removed, the floating body 24 potential will decrease by ΔV FB . If the initial floating body 24 potential of state logic-1 is referred to as V FB1 , the floating body 24 potential after the write logic-0 operation will become V FB1 −ΔV FB . Therefore, the WL potential needs to be optimized such that the decrease in floating body potential of memory cells 50 in state logic-1 is not too large during the time when the positive voltage is applied to (and subsequently removed from) WL terminal 70 a . For example, the maximum floating body potential increase due to the coupling from the WL potential cannot exceed V FB1 /2. Thus in some embodiments it may be advantageous to have a slightly positive voltage on unselected BL terminal 74 p . This means that bipolar device 30 can only evacuate holes in reverse operation (e.g., only the p-n junction between the floating body 24 and buried well 22 will be on enough to evacuate holes from the floating body region 24 ) which may minimize the reduction of holes in floating body region 24 in the logic-1 state.

As shown in FIGS. 48 E and 48 F , for representative memory cell 250 c sharing the same column as the selected representative memory cell 250 a , a negative voltage is applied to the BL terminal 74 a , resulting in an increase in the potential difference between floating body 24 and bit line region 16 connected to the BL terminal 74 a . As a result, the p-n diode formed between floating body 24 and bit line region 16 will be forward biased. For memory cells in the logic-0 state, the increase in the floating body 24 potential will not change the initial state from logic-0 as there is initially no hole stored in the floating body 24 . For memory cells in the logic-1 state, the net effect is that the floating body 24 potential after write logic-0 operation will be reduced. Therefore, the BL potential also needs to be optimized such that the decrease in floating body potential of memory cells 250 in state logic-1 is not too large during the time when the negative voltage is applied to BL terminal 74 a . For example, the −V FB1 /2 is applied to the BL terminal 74 a.

As shown in FIGS. 48 G and 48 H , memory cell 250 d sharing neither the same row nor the same column as the selected representative memory cell 250 a , these cells will be in a holding mode as positive voltage is applied to the SL terminal 72 n , zero voltage is applied to the BL terminal 74 p , and zero or negative voltage is applied to WL terminal 70 n , and zero voltage is applied to substrate terminal 78 .

Three different methods for performing a write logic-0 operation on memory cell 250 have been disclosed. Many other embodiments and component organizations are possible like, for example, reversing the first and second conductivity types while inverting the relative voltage biases applied. An exemplary array 280 has been used for illustrative purposes, but many other possibilities are possible like, for example, applying different bias voltages to the various array line terminals, employing multiple arrays, performing multiple single bit write logic-0 operations to multiple selected bits in one or more arrays or by use of decoding circuits, interdigitating bits so as to conveniently write logic-0s to a data word followed by writing logic-1s to selected ones of those bits, etc. Such embodiments will readily suggest themselves to persons of ordinary skill in the art familiar with the teachings and illustrations herein. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.

A write logic-1 operation may be performed on memory cell 250 through impact ionization as described, for example, with reference to Lin cited above, or through a band-to-band tunneling mechanism (also known as Gate Induced Drain Leakage or GIDL), as described, for example with reference to Yoshida cited above. An example of a write logic-1 operation using the GIDL method is described in conjunction with FIGS. 49 and 50 A through 50 H while an example of a write logic-1 operation using the impact ionization method is described in conjunction with FIGS. 51 and 52 A through 52 H .

In FIG. 49 an example of the bias conditions of the array 280 including selected representative memory cell 250 a during a band-to-band tunneling write logic-1 operation is shown. The negative bias applied to the WL terminal 70 a and the positive bias applied to the BL terminal 74 a results in hole injection to the floating body 24 of the selected representative memory cell 250 a . The SL terminal 72 a and the substrate terminal 78 are grounded during the write logic-1 operation.

The negative voltage on WL terminal 70 couples the voltage potential of the floating body region 24 in representative memory cell 250 a downward. This combined with the positive voltage on BL terminal 74 a creates a strong electric field between the bit line region 16 and the floating body region 24 in the proximity of gate 60 (hence the “gate induced” portion of GIDL) in selected representative memory cell 250 a . This bends the energy bands sharply upward near the gate and drain junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current (hence the “drain leakage” portion of GIDL), while the holes are injected into floating body region 24 and become the hole charge that creates the logic-1 state. This process is well known in the art and is illustrated in Yoshida (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4) cited above.

›DETAILED DESCRIPTION · 25 of 64

As shown in FIGS. 50 A through 50 B , the following bias conditions may be applied to the selected representative memory cell 250 a : a potential of about 0.0 volts is applied to SL terminal 72 a , a potential of about +1.2 volts is applied to BL terminal 74 a , a potential of about −1.2 volts is applied to WL terminal 70 a , and about 0.0 volts is applied to substrate terminal 78 .

Elsewhere in array 280 the following bias conditions are applied to the terminals for unselected memory cells 250 including representative memory cells 250 b , 250 c and 250 d : about +1.2 volts is applied to SL terminal 72 n , about 0.0 volts is applied to BL terminal 74 p , a potential of about 0.0 volts is applied to WL terminal 70 n , and about 0.0 volts is applied to substrate terminal 78 . FIG. 49 shows the bias condition for the selected and unselected memory cells in memory array 280 . However, these voltage levels may vary from embodiment to embodiment of the present invention and are exemplary only and are in no way limiting.

The unselected memory cells during write logic-1 operations are shown in FIGS. 50 C through 50 H . The bias conditions for memory cells sharing the same row (e.g. representative memory cell 250 b ) are shown in FIGS. 50 C and 50 D . The bias conditions for memory cells sharing the same column as the selected representative memory cell 250 a (e.g. representative memory cell 250 c ) are shown in FIGS. 50 E and 50 F . The bias conditions for memory cells 250 not sharing the same row nor the same column as the selected representative memory cell 250 a (e.g. representative memory cell 250 d ) are shown in FIGS. 50 G and 50 H .

As illustrated in FIGS. 50 C and 50 D , representative memory cell 250 b , sharing the same row as the selected representative memory cell 250 a , has both terminals 72 a and 74 p grounded, while about −1.2 volts is applied to WL terminal 70 a . Because SL terminal 70 a is grounded, memory cell 250 b will not be at the holding mode since there is no voltage across between the emitter and collector terminals of the n-p-n bipolar device 30 turning it off. However, because the write logic-1 operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As illustrated in FIGS. 50 E and 50 F , for representative memory cell 250 c sharing the same column as the selected memory cell, a positive voltage is applied to the BL terminal 74 n . No base current will flow into the floating body 24 because there is no potential difference between SL terminal 72 n and BL terminal 74 a (i.e. there is no voltage between the emitter and collector terminals of the n-p-n bipolar device 30 turning it off). However, because a write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As illustrated in FIGS. 50 G and 50 H , for memory cell 250 d sharing neither the same row nor the same column as the selected memory cell, the SL terminal 72 n will remain positively charged while the gate terminal 70 n and the BL terminal 74 p remain grounded. As can be seen, these cells will be at holding mode. Memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 a will generate holes current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in neutral state.

FIG. 51 shows a write logic-1 operation using the impact ionization method. In this case, both the gate 60 and bit line 16 of the memory cell 250 to be written are biased at a positive voltage. This is similar to the holding operation described earlier in conjunction with FIGS. 37 A through 38 D which also uses impact ionization to supply hole current to the floating body 24 . However in the holding operation, the n-p-n bipolar device 30 stays off when a logic-0 is stored in memory cell 250 and impact ionization current only flows when a logic-1 is stored in the cell restoring the charge level in the floating body 24 to a full logic-1 level. By contrast, in the case of a write logic-1 operation using impact ionization, the voltage on the gate terminal is positive rather than zero. The action of raising the gate 60 to a positive voltage has the effect of raising the voltage potential of the floating body region 24 due to capacitive coupling across the gate insulating layer 62 which causes the n-p-n bipolar transistor 30 to turn on regardless of whether or not a logic-1 or logic-0 is stored in memory cell 250 . This causes impact ionization current to flow charging the floating body 24 to the logic-1 state regardless of the data originally stored in the cell.

In the exemplary embodiment shown in FIG. 51 , the selected word line terminal 70 a is biased at about +1.2V while the unselected word line terminals 70 b (not shown) through 70 n are biased at about 0.0V, the selected bit line terminal 74 a is also biased at about +1.2V while the unselected bit line terminals 74 b through 74 p are biased at about 0.0V, the selected source line 72 a is biased at about 0.0V, while the unselected source line terminals 72 b (not shown) through 72 n are biased at about +1.2V, and the substrate terminal 78 is biased at about 0.0V. These voltage bias levels are exemplary only and will vary from embodiment to embodiment and are thus in no way limiting.

As shown in FIGS. 52 A through 52 B , selected representative memory cell 50 a is shown with gate 60 coupled to WL terminal 70 A biased at +1.2V, bit line region 16 coupled to BL terminal 74 a biased at +1.2V, and buried layer 22 coupled to source line terminal 72 a biased at 0.0V. In this state, impact ionization current flows into the cell from BL terminal 74 a injecting holes into the floating body region 24 writing a logic-1 state into representative memory cell 250 a.

›DETAILED DESCRIPTION · 26 of 64

As shown in FIGS. 52 C through 52 D , unselected representative memory cell 250 b , sharing a row but not a column with selected representative memory cell 250 a , is shown with gate 60 coupled to WL terminal 70 a biased at +1.2V, bit line region 16 coupled to BL terminal 74 p biased at 0.0V, and buried layer 22 coupled to source line terminal 72 a biased at 0.0V. In this state, the collector-to-emitter voltage of n-p-n bipolar device 30 is 0.0V causing the device to be off protecting the contents of representative memory cell 250 b.

As shown in FIGS. 52 E through 52 F , unselected representative memory cell 250 c , sharing a column but not a row with selected representative memory cell 250 a , is shown with gate 60 coupled to WL terminal 70 n biased at 0.0V, bit line region 16 coupled to BL terminal 74 a biased at +1.2V, and buried layer 22 coupled to source line terminal 72 n biased at +1.2V. In this state, the n-p-n bipolar device 30 will be off since there is no voltage difference between the collector and emitter terminals of n-p-n bipolar device 30 .

As shown in FIGS. 52 G through 52 H , unselected representative memory cell 250 d , sharing neither a row nor a column with selected representative memory cell 250 a , is shown with gate 60 coupled to WL terminal 70 n biased at 0.0V, bit line region 16 coupled to BL terminal 74 p biased at 0.0V, and buried layer 22 coupled to source line terminal 72 n biased at +1.2V. As can be seen, these cells will be at holding mode. Memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 a will generate holes current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in neutral state.

FIG. 53 A shows a top view of an embodiment of a partial memory array including Gated half transistor memory cell 350 according to the present invention and FIG. 53 B shows memory cell 350 in isolation. FIGS. 53 C and 53 D show the memory cell 350 cross sections along the I-I′ line and II-II′ cut lines, respectively, while FIG. 53 E shows a method of contacting the buried well and substrate layers beneath the cells. FIGS. 54 A through 54 H show memory array 380 comprised of rows and columns of memory cell 350 . The primary difference between memory cell 250 and memory cell 350 is that while insulating layers 26 isolate the buried layer 22 between memory cells in adjacent rows in memory cell 250 , in memory cell 350 the regions occupied by insulating layer 26 are replaced by insulating layer 28 . Thus memory cell 350 is surrounded by insulating layer 28 on all four sides and the buried layer 22 is continuously connected as a single “source line” amongst all of the memory cells 350 in memory array 380 . This makes for a memory array that is very similar to memory array 280 , however some operations will be different as described below in conjunction with FIGS. 54 A through 54 F . As was the case with memory cell 250 in memory cell 280 , there is no contact to the buried layer 22 within the boundary of memory cell 350 .

Referring to FIGS. 53 C and 53 D together, the cell 350 includes a substrate 12 of a first conductivity type such as a p-type, for example. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In other embodiments, substrate 12 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice. To simplify the description, the substrate 12 will is drawn as the semiconductor bulk material as it is in FIGS. 53 C and 53 D though it may also be a well in a substrate of material of the second type of conductivity.

A floating body region 24 of the first conductivity type, such as p-type, for example, is bounded on top by bit line region 16 an insulating layer 62 , on the sides by insulating layer 28 , and on the bottom by buried layer 22 . Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 22 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments, as a matter of design choice.

Insulating layers 28 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 28 insulate cell 350 from neighboring cells 350 when multiple cells 350 are joined in an array 380 to make a memory device as illustrated in FIGS. 54 A- 54 F . Insulating layer 28 insulates neighboring body regions 24 , but not the buried layer 22 , allowing the buried layer 22 to be continuous (i.e. electrically conductive) under the entire array 380 .

A gate 60 is positioned in between the bit line region 16 and insulating layer 28 and above the floating body region 24 . The gate 60 is insulated from floating body region 24 by an insulating layer 62 . Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

›DETAILED DESCRIPTION · 27 of 64

Memory cell 350 further includes word line (WL) terminal 70 electrically connected to gate 60 , bit line (BL) terminal 74 electrically connected to bit line region 16 , source line (SL) terminal 72 electrically connected to buried layer 22 , and substrate terminal 78 electrically connected to substrate 12 .

As shown in FIG. 53 E , contact between SL terminal 72 and buried layer 22 can be made through region 20 having a second conductivity type, and which is electrically connected to buried well region 22 , while contact between substrate terminal 78 and substrate region 12 can be made through region 21 having a first conductivity type, and which is electrically connected to substrate region 12 .

Comparing the structure of the memory device 350 , for example, as shown in FIG. 53 C to the structure of transistor devices 100 , 100 A and 100 B in FIGS. 90 A through 90 C , it can be seen that the memory device of present invention constitutes a smaller structure relative to the MOSFET devices 100 , 100 A and 100 B, where only one region of a second conductivity type is present at the surface of the silicon substrate. Thus, memory cell 350 of the present invention provides an advantage that it consists of only one region of second conductivity at the surface (i.e. bit line region 16 as opposed to regions 84 and 86 or regions 84 A and 86 A) and hence requires only one contact per memory cell 350 (i.e. to create a connection between bit line region 16 and terminal 74 ).

Persons of ordinary skill in the art will appreciate that in FIGS. 53 A through 53 E and that the first and second conductivity types can be reversed in memory cell 350 as a matter of design choice and that the labeling of regions of the first conductivity type as p-type and the second conductivity type as p-type is illustrative only and not limiting in any way. Thus the first and second conductivity types can be p-type and n-type respectively in some embodiments of memory cell 350 and be n-type and p-type respectively in other embodiments. Further, such skilled persons will realize that the relative doping levels of the various regions of either conductivity type will also vary as a matter of design choice and that there is no significance to the absence of notation signifying higher or lower doping levels such as p+ or p− or n+ or n− in any of the diagrams.

FIG. 54 A shows an exemplary memory array 380 of memory cells 350 (four exemplary instances of memory cell 350 being labeled as 350 a , 350 b , 350 c and 350 d ) arranged in rows and columns. In many, but not all, of the figures where exemplary memory array 380 appears, representative memory cell 350 a will be representative of a “selected” memory cell 350 when the operation being described has one (or more in some embodiments) selected memory cells 350 . In such figures, representative memory cell 350 b will be representative of an unselected memory cell 350 sharing the same row as selected representative memory cell 350 a , representative memory cell 350 c will be representative of an unselected memory cell 350 sharing the same column as selected representative memory cell 350 a , and representative memory cell 350 d will be representative of a memory cell 350 sharing neither a row or a column with selected representative memory cell 350 a.

Present in FIG. 54 A are word lines 70 a through 70 n , source line terminal 72 X, bit lines 74 a through 74 p , and substrate terminal 78 . Each of the word lines 70 a through 70 n is associated with a single row of memory cells 350 and is coupled to the gate 60 of each memory cell 350 in that row. Each of the bit lines 74 a through 74 p is associated with a single column of memory cells 350 and is coupled to the bit line region 16 of each memory cell 350 in that column. It is noteworthy that while the source line terminal 72 X is really no longer a control line terminal associated with the source line 72 of a row of memory cells 350 but a control terminal associated with all of the memory cells 350 in exemplary memory array 380 , it will still be referred to as “source line” terminal 72 X to minimize confusion since it still serves that function for each individual memory cell 350 .

Substrate 12 and buried layer 22 are both present at all locations under array 380 . Persons of ordinary skill in the art will appreciate that one or more substrate terminals 78 and one or more buried well terminals 72 will be present in one or more locations as a matter of design choice. Such skilled persons will also appreciate that while exemplary array 380 is shown as a single continuous array in FIG. 54 A , that many other organizations and layouts are possible like, for example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, the array 380 may be broken into two or more sub-arrays, control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed around exemplary array 380 or inserted between sub-arrays of array 380 . Thus the exemplary embodiments, features, design options, etc., described are not limiting in any way.

FIG. 54 B illustrates an array hold operation on exemplary memory array 380 . For all memory cells 350 in the array 380 , the hold operation is performed simultaneously by applying about +1.2V to the source line terminal 72 while applying about 0.0V to the word line terminals 70 a through 70 n , the bit line terminals 74 a through 74 p , and the substrate terminal 78 . This bias condition causes each of the memory cells 350 in the array 380 storing a logic-1 to have its intrinsic bipolar transistor 30 turned on to restore the hole charge on its floating body 24 as discussed above. Simultaneously, this bias condition causes each of the memory cells 350 in the array 380 storing a logic-0 to have its intrinsic bipolar transistor 30 turned off to retain charge neutrality in its floating body 24 as previously discussed. The voltages applied are exemplary only, may vary from embodiment to embodiment and are in no way limiting.

›DETAILED DESCRIPTION · 28 of 64

FIG. 54 C illustrates a single cell read operation of selected representative memory cell 350 a in exemplary memory array 350 . To accomplish this, the selected word line terminal 70 a is biased to approximately +1.2V while the unselected word line terminals 70 b (not shown) through 70 n are biased to about 0.0V, the selected bit line terminal 74 a is biased to approximately +0.4V while the unselected bit line terminals 74 b through 74 p are biased to about 0.0V, the source line terminal 72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.

This has the effect of operating bipolar device 30 as a backward n-p-n transistor in a manner analogous to that described for operating bipolar device 30 for a hold operation as described in conjunction with FIGS. 37 A through 37 C .

The capacitive coupling between the word line terminal 70 a and the floating body 24 of selected memory cell 350 a increase the differentiation in the read current between the logic-1 and logic-0 states as previously described. The optimal bias voltage to apply to WL terminal 70 will vary from embodiment to embodiment and process to process. The actual voltage applied in any given embodiment is a matter of design choice.

Unselected representative memory cell 350 b , which shares a row with selected representative memory cell 350 a , has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the read operation.

Unselected representative memory cell 350 c , which shares a column with selected representative memory cell 350 a , will either be off or be in a weak version of the holding operation depending on the device characteristics of the process of any particular embodiment. It also retains its logic state during the short duration of the read operation.

Unselected representative memory cell 350 d , which shares neither a row nor a column with selected representative memory cell 350 a , has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It too retains its logic state during the short duration of the read operation.

FIG. 54 D illustrates an array write logic-0 operation of all the memory cells 350 in exemplary memory array 350 . To accomplish this, all the word line terminals 70 a through 70 n are biased to approximately 0.0V, all the bit line terminals 74 a through 74 p are biased to approximately −1.2V, the source line terminal 72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.

This bias condition forward biases the p-n junction between the floating body 24 and the bit line region 16 turning on the intrinsic bipolar device 30 in each of the memory cells 350 as previously described. This evacuates all of the holes in the floating body regions 24 writing a logic-0 to all of the memory cells 350 in array 380 .

FIG. 54 E illustrates a column write logic-0 operation of one column of the memory cells 350 in exemplary memory array 350 . To accomplish this, all the word line terminals 70 a through 70 n are biased to approximately 0.0V, selected the bit line terminal 74 a is biased to approximately −1.2V while the unselected bit line terminals 74 b through 74 p are biased to about 0.0V, the source line terminal 72 is biased to about +1.2V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.

This bias condition forward biases the p-n junction between the floating body 24 and the bit line region 16 turning on the intrinsic bipolar device 30 in each of the memory cells 350 coupled to bit line 74 a , including representative memory cells 350 a and 350 c , as previously described. This evacuates all of the holes in the floating body regions 24 writing a logic-0 to all of the memory cells 350 in the selected column.

The remaining memory cells 350 in array 380 , including representative memory cells 350 b and 350 d , are in a holding operation and will retain their logic state during the write logic-0 operation.

FIG. 54 F illustrates a single cell write logic-0 operation of selected representative memory cell 350 a in exemplary memory array 350 . To accomplish this, the selected word line terminal 70 a is biased to approximately +0.5V while the unselected word line terminals 70 b (not shown) through 70 n are biased to about −1.2V, the selected bit line terminal 74 a is biased to approximately −0.2V while the unselected bit line terminals 74 b through 74 p are biased to about 0.0V, the source line terminal 72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.

This bias condition forward biases the p-n junction between the floating body 24 and the bit line region 16 turning on the intrinsic bipolar device 30 in selected representative memory cell 350 a . The capacitive coupling between the word line terminal 70 a and the floating body 24 of selected memory cell 350 a causes bipolar device 30 to turn on evacuating the holes in floating body region 24 as previously described.

Unselected representative memory cell 350 c , which shares a column with selected representative memory cell 350 a , has the voltage potential of its floating body temporarily lowered because the negative capacitive coupling between its floating body 24 its gate 60 (coupled to word line terminal 70 n ) preventing its bipolar device 30 from turning on. It also retains its logic state during the short duration of the read operation, and the voltage potential of its floating body 24 is restored to its previous level by the positive coupling between its floating body 24 its gate 60 (coupled to word line terminal 70 n ) when the word line terminal is returned to its nominal value of about 0.0V after the operation is complete.

›DETAILED DESCRIPTION · 29 of 64

FIG. 54 G illustrates a single cell write logic-1 operation using a GIDL mechanism in selected representative memory cell 350 a in exemplary memory array 350 . To accomplish this, the selected word line terminal 70 a is biased to approximately −1.2V while the unselected word line terminals 70 b (not shown) through 70 n are biased to about 0.0V, the selected bit line terminal 74 a is biased to approximately +1.2V while the unselected bit line terminals 74 b through 74 p are biased to about 0.0V, the source line terminal 72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.

This bias condition causes selected representative memory cell 350 a to conduct current due to the GIDL mechanism discussed with reference to Yoshida cited above. The combination of −1.2V on word line terminal and +1.2V on bit line terminal 74 a creates the strong electric field necessary to produce GIDL current from bit line 74 a into representative memory cell 350 a generating sufficient hole charge in its floating body 24 to place it in the logic-1 state.

Unselected representative memory cell 350 c , which shares a column with selected representative memory cell 350 a , is in the holding state. It also retains its logic state during the short duration of the write logic-1 operation.

FIG. 54 H illustrates a single cell write logic-1 operation using an impact ionization mechanism in selected representative memory cell 350 a in exemplary memory array 350 . To accomplish this, the selected word line terminal 70 a is biased to approximately +1.2V while the unselected word line terminals 70 b (not shown) through 70 n are biased to about 0.0V, the selected bit line terminal 74 a is biased to approximately +1.2V while the unselected bit line terminals 74 b through 74 p are biased to about 0.0V, the source line terminal 72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.

This bias condition causes selected representative memory cell 350 a to conduct current due to the impact ionization mechanism discussed with reference to Lin cited above. The combination of +1.2V on word line terminal and +1.2V on bit line terminal 74 a turns on the bipolar device 30 in representative memory cell 350 a regardless of its prior logic state and generating sufficient hole charge in its floating body 24 to place it in the logic-1 state.

In the previous embodiments, a single binary bit has been written to, read from, and maintained in a single memory cell 250 or 350 . While this approach makes for the simplest support circuitry, the simplest operating methods, and the largest noise margins, greater memory density may be achieved by storing two or more bits per memory cell 250 or 350 at the cost of increasing the complexity of the support circuitry and operating methods. Additionally, the noise margin is also reduced because the voltage window inside memory cell 250 or 350 is shared by more than two logic levels.

Preferably the information stored in memory cell 250 or 350 corresponds to an integer number of binary bits, meaning that the number of voltage levels stored in memory cell 50 or 350 will be equal to a power of two (e.g., 2, 4, 8, 16, etc.), though other schemes are possible within the scope of the invention. Due to the lower noise margins, it may be desirable to encode the data in memory array 80 or 380 using any error correction code (ECC) known in the art. In order to make the ECC more robust, the voltage levels inside may be encoded in a non-binary order like, for example, using a gray code to assign binary values to the voltage levels. In the case of gray coding, only one bit changes in the binary code for a single level increase or decrease in the voltage level. Thus for an example a two bit gray encoding, the lowest voltage level corresponding to the floating body region 24 voltage being neutral might be encoded as logic-00, the next higher voltage level being encoded as logic-01, the next higher voltage level after that being encoded as logic-11, and the highest voltage level corresponding to the maximum voltage level on floating body region 24 being encoded as logic-10. In an exemplary three bit gray encoding, the logic levels from lowest to highest might be ordered logic-000, logic-001, logic-011, logic-010, logic-110, logic-111, logic-101, and logic-100. Since the most likely reading error is to mistake one voltage level for one of the two immediately adjacent voltage levels, this sort of encoding ensures that a single level reading error will produce at most a single bit correction per error minimizing the number of bits needing correction for any single error in a single cell. Other encodings may be used, and this example is in no way limiting.

›DETAILED DESCRIPTION · 30 of 64

A multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to the memory cell 250 or 350 , followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to the memory cell 250 or 350 , followed by another read verification operation. This loop is repeated until the desired memory state is achieved.

For example, using band-to-band hot hole injection to write memory cell 250 or 350 , initially zero voltage is applied to BL terminal 74 , zero voltage is applied to SL terminal 72 , a negative voltage is applied to WL terminal 70 , and zero voltage is applied to the substrate terminal 78 . Then positive voltages of different amplitudes are applied to BL terminal 74 to write different states to floating body 24 . This results in different floating body potentials 24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied to BL terminal 74 . Note that memory cell 250 or 350 must be written to the lowest voltage state on floating body region 24 prior to executing this algorithm.

In one particular non-limiting embodiment, the write operation is performed by applying the following bias condition: a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about −1.2 volts is applied to WL terminal 70 , and about 0.0 volts is applied to substrate terminal 78 , while the potential applied to BL terminal 74 is incrementally raised. For example, in one non-limiting embodiment, 25 millivolts is initially applied to BL terminal 74 , followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e. cell current corresponding to whichever binary value of 00, 01, 11 or 10 is desired is achieved), then the multi-level write operation is successfully concluded. If the desired state is not achieved, then the voltage applied to BL terminal 74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary from embodiment to embodiment and the above voltage levels are exemplary only and in no way limiting. To write four levels to the memory cells, at least three different positive voltage pulses (which may comprise of different amplitudes) to the BL terminal 74 are required. The first pulse corresponds to writing the memory cell to the level associated with the binary value of 01, the second pulse corresponds to writing the memory cell to the level associated with the binary value of 11, and the third pulse corresponds to writing the memory cell to the level associated with the binary value of 10.

The write-then-verify algorithm is inherently slow since it requires multiple write and read operations. The present invention provides a multi-level write operation that can be performed without alternate write and read operations as described in FIGS. 55 A through 55 F with respect to exemplary memory array 280 . Persons of ordinary skill in the art will appreciate that the principles described will apply to all of the Half Transistor memory cells within the scope of the present invention.

As shown in FIG. 55 A , the potential of the floating body 24 increases over time as a result of hole injection to floating body 24 , for example through an impact ionization mechanism. Once the change in cell current reaches the level associated with the desired state of the selected representative memory cell 250 , the voltage applied to BL terminal 74 can be removed. In this manner, the multi-level write operation can be performed without alternate write and read operations by applying a voltage ramp of the correct duration. After the end of the pulse time, the applied voltage returns to the starting value like, for example, ground. Thus as shown in FIG. 55 A , a voltage ramp of pulse width T 1 applied to the bit line terminal 74 of memory cell 250 in the lowest (logic-00 state) potential state will increase the potential of the floating body 24 from the logic-00 level to the logic-01 level. Similarly, a voltage ramp of pulse width T 2 applied to the bit line terminal 74 of memory cell 250 in the lowest (logic-00 state) potential state will increase the potential of the floating body 24 from the logic-00 level to the logic-11 level, and a voltage ramp of pulse width T 3 applied to the bit line terminal 74 of memory cell 250 in the lowest (logic-00 state) potential state will increase the potential of the floating body 24 from the logic-00 level to the logic-10 level.

In FIG. 55 B this is accomplished in selected representative memory cell 250 a by ramping the voltage applied to BL terminal 74 a , while applying zero voltage to SL terminal 72 a , a positive voltage to WL terminal 70 , and zero voltage to substrate terminal 78 of the selected memory cells. These bias conditions will result in a hole injection to the floating body 24 through an impact ionization mechanism. The state of the memory cell 250 a can be simultaneously read for example by monitoring the change in the cell current through read circuitry 91 a coupled to the source line 72 a.

In the rest of array 280 , zero voltage is applied to the unselected WL terminals 70 b (not shown) through 70 n , zero voltage is applied to the unselected SL terminals 72 b (not shown) through 72 n , and zero voltage is applied to the unselected BL terminals 74 b through 74 p . The cell current measured in the source line direction is the total cell current of all memory cells 250 which share the same source line 72 a , but all of the unselected cells like representative memory cell 50 b are biased with zero voltage across them from their bit line region 16 to their source line region 22 and do not conduct current as long as the source line terminal 72 a is correctly biased to maintain zero volts. As a result, only one selected memory cell 50 a sharing the same source line 72 can be written at a time.

›DETAILED DESCRIPTION · 31 of 64

In FIG. 55 B , the unselected representative memory cell 250 b has zero volts between the BL terminal 74 p and the SL terminal 72 a so no current flows and the state of the data stored in them will not change. Unselected representative memory cell 250 c sharing BL terminal 74 a with selected representative memory cell 250 a has its WL terminal grounded. Thus its floating body region 24 does not get the voltage coupling boost that the floating body region 24 in selected representative memory cell 250 a gets. A positive bias is also applied to the unselected SL terminal 72 n . This condition substantially reduces the current in representative memory cell 250 c which reduces the degree of hole charge its floating body region 24 receives as the voltage applied to BL terminal 74 a is ramped up. Unselected representative memory cell 250 d , sharing neither a row nor a column with selected representative memory cell 250 a , is shown with gate 60 coupled to WL terminal 70 n biased at 0.0V, bit line region 16 coupled to BL terminal 74 p biased at 0.0V, and buried layer 22 coupled to source line terminal 72 n biased at +1.2V. As can be seen, these cells will be at holding mode. Memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 a will generate holes current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in neutral state.

FIG. 55 B also shows reference generator circuits 93 a through 93 n coupled respectively to source line terminals 72 a through 72 n and read circuits 91 a through 91 n coupled respectively to source line terminals 72 a through 72 n and coupled respectively to reference generator circuit 93 a through 93 n . Reference generator circuit 93 a serves to store the initial total cell current of selected representative memory cell 250 a and provide this value to read circuit 91 a during the write operation in real time so that the change in current can be monitored and feedback (not shown in FIG. 55 B ) can be used to shut off the voltage ramp at the appropriate time. This function can be implemented in a variety of ways.

In FIG. 55 C , for example, the cumulative charge of the initial state for selected memory cell 250 a sharing the same source line 72 a can be stored in a capacitor 97 a . Transistor 95 a is turned on when charge is to be written into or read from capacitor 94 .

Alternatively, as shown in FIG. 55 D , reference cells 250 Ra through 250 Rn similar to a memory cell 250 replace capacitors 97 a through 97 n in reference generator circuits 93 a through 93 n . The reference cells 250 Ra through 250 Rn can also be used to store the initial state of selected representative memory cell 250 a.

In another embodiment, a multi-level write operation can be performed on memory cell 250 through a band-to-band tunneling mechanism by ramping the voltage applied to BL terminal 74 , while applying zero voltage to SL terminal 72 , a negative voltage to WL terminal 70 , and zero voltage to substrate terminal 78 of the selected memory cells 250 . The unselected memory cells 250 will remain in holding mode, with zero or negative voltage applied to WL terminal 70 , zero voltage applied to BL terminal 74 , and a positive voltage applied to SL terminal 72 . Optionally, multiple BL terminals 74 can be simultaneously selected to write multiple cells in parallel. The potential of the floating body 24 of the selected memory cell(s) 250 will increase as a result of the band-to-band tunneling mechanism. The state of the selected memory cell(s) 250 can be simultaneously read for example by monitoring the change in the cell current through a read circuit 91 coupled to the source line. Once the change in the cell current reaches the desired level associated with a state of the memory cell, the voltage applied to BL terminal 74 can be removed. In this manner, the multi-level write operation can be performed without alternate write and read operations.

In another embodiment, as shown in FIG. 55 E , a read while writing operation can be performed by monitoring the change in cell current in the bit line direction through a reading circuit 99 a coupled to the bit line 74 a . In some embodiments a reading circuit 99 b through 99 p (not shown in FIG. 55 E ) may be coupled to each bit of the other bit lines 74 b through 74 p , while in other embodiments reading circuit 99 a may be shared between multiple columns using a decoding scheme (not shown).

Reference cells 250 R representing different memory states are used to verify the state of the write operation. The reference cells 250 R can be configured through a write-then-verify operation, for example, when the memory device is first powered up or during subsequent refresh periods. Thus while selected representative memory cell 250 a is being written, selected reference cell 250 R containing the desired voltage state (or a similar voltage) to be written is read and the value is used to provide feedback to read circuit so that the write operation may be terminated when the desired voltage level in selected representative memory cell 250 a is reached. In some embodiments, multiple columns of reference cells containing different reference values corresponding to the different multilevel cell write values may be present (not shown in FIG. 55 E ).

In the voltage ramp operation, the resulting cell current of the representative memory cell 250 a being written is compared to the reference cell 250 R current by means of the read circuitry 99 a . During this read while writing operation, the reference cell 250 R is also being biased at the same bias conditions applied to the selected memory cell 250 during the write operation. Therefore, the write operation needs to be ceased after the desired memory state is achieved to prevent altering the state of the reference cell 250 R.

›DETAILED DESCRIPTION · 32 of 64

As shown in FIG. 55 F , for the current ramp operation, the voltage at the bit line 74 a can be sensed instead of the cell current. In the current ramp operation, a positive bias is applied to the source line terminal 72 a and current is forced through the BL terminal 74 a . The voltage of the BL terminal 74 a will reflect the state of the memory cell 250 a . Initially, when memory cell 250 a is in logic-0 state, a large voltage drop is observed across the memory cell 250 a and the voltage of the BL terminal 74 a will be low. As the current flow through the memory cell 250 a increases, hole injection will increase, resulting memory cell 250 a to be in logic-1 state. At the conclusion of the logic-1 state write operation, the voltage drop across the memory cell 250 a will decrease and an increase in the potential of BL terminal 74 a will be observed.

With increasing charge in the floating body 24 , the four states are referred to as states “00”, “01”, “10”, and “11”. To program a memory cell 250 a to a state “01”, the reference cell 250 R corresponding to state “01” is activated. Subsequently, the bias conditions described above are applied both to the selected memory cell 250 and to the “01” reference cell 250 R: zero voltage is applied to the source line terminal 72 , zero voltage is applied to the substrate terminal 78 , a positive voltage is applied to the WL terminal 70 (for the impact ionization mechanism), while the BL terminal 74 is being ramped up, starting from zero voltage. Starting the ramp voltage from a low voltage (i.e. zero volts) ensures that the state of the reference cell 250 R does not change.

The voltage applied to the BL terminal 74 a is then increased. Consequently, holes are injected into the floating body 24 of the selected cell 50 and subsequently the cell current of the selected cell 250 increases. Once the cell current of the selected cell 250 reaches that of the “01” reference cell, the write operation is stopped by removing the positive voltage applied to the BL terminal 74 and WL terminal 70 .

Unselected representative memory cell 250 b , which shares a row with selected representative memory cell 250 a , has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the multi-level write operation.

Unselected representative memory cell 250 c , which shares a column with selected representative memory cell 250 a , is in the holding state. Less base current will flow into the floating body 24 due to the smaller potential difference between SL terminal 72 n and BL terminal 74 a (i.e. the emitter and collector terminals of the n-p-n bipolar device 30 ). It also retains its logic state during the short duration of the multi-level write operation.

Unselected representative memory cell 250 d , which shares neither a row nor a column with selected representative memory cell 250 a , is in the holding state. It too retains its logic state during the short duration of the multi-level write operation.

It is noteworthy that the holding operation for memory cell 250 in multistate mode is self-selecting. In other words, the quantity of holes injected into the floating body 24 is proportional to the quantity of holes (i.e., the charge) already present on the floating body 24 . Thus each memory cell selects its own correct degree of holding current.

FIGS. 56 and 57 show gated half transistor memory cell 250 V with FIG. 57 showing the top view of the memory cell 250 V shown in FIG. 56 . Referring now to both FIGS. 56 and 57 , reference numbers previously referred to in earlier drawing figures have the same, similar, or analogous functions as in the earlier described embodiments. Memory cell 250 V has a fin structure 52 fabricated on substrate 12 , so as to extend from the surface of the substrate to form a three-dimensional structure, with fin 52 extending substantially perpendicular to and above the top surface of the substrate 12 . Fin structure 52 is conductive and is built on buried well layer 22 which is itself built on top of substrate 12 . Alternatively, buried well 22 could be a diffusion inside substrate 12 with the rest of the fin 52 constructed above it, or buried well 22 could be a conductive layer on top of substrate 12 connected to all the other fin 52 structures in a manner similar to memory cell 350 described above. Fin 52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.

Buried well layer 22 may be formed by an ion implantation process on the material of substrate 12 which may be followed by an etch so that buried well 22 is above the portion of substrate 12 remaining after the etch. Alternatively, buried well layer 22 may be grown epitaxially above substrate 22 and the unwanted portions may then be etched away. Buried well layer 22 , which has a second conductivity type (such as n-type conductivity type), insulates the floating body region 24 , which has a first conductivity type (such as p-type conductivity type), from the bulk substrate 12 also of the first conductivity type. Fin structure 52 includes bit line region 16 having a second conductivity type (such as n-type conductivity type). Memory cell 250 V further includes gates 60 on two opposite sides of the floating substrate region 24 insulated from floating body 24 by insulating layers 62 . Gates 60 are insulated from floating body 24 by insulating layers 62 . Gates 60 are positioned between the bit line region 16 and the insulating layer 28 , adjacent to the floating body 24 .

Thus, the floating body region 24 is bounded by the top surface of the fin 52 , the facing side and bottom of bit line region 16 , top of the buried well layer 22 , and insulating layers 26 , 28 and 62 . Insulating layers 26 and 28 insulate cell 250 V from neighboring cells 250 V when multiple cells 250 V are joined to make a memory array. Insulating layer 26 insulates adjacent buried layer wells 22 , while insulating layer 28 does not. Thus the buried layer 22 is therefore continuous (i.e. electrically conductive) in one direction. In this embodiment, the surface 14 of the semiconductor is at the level of the top of the fin structure. As in other embodiments, there is no contact to the buried layer 22 at the semiconductor surface 14 inside the boundary of memory cell 250 V.

›DETAILED DESCRIPTION · 33 of 64

As shown in FIG. 58 A , an alternate fin structure 52 A can be constructed. In this embodiment, gates 60 and insulating layers 62 can enclose three sides of the floating substrate region 24 . The presence of the gate 60 on three sides allows better control of the charge in floating body region 24 .

Memory cell 250 V can be used to replace memory cell 250 in an array similar to array 280 having similar connectivity between the cells and the array control signal terminals. In such a case, the hold, read and write operations are similar to those in the lateral device embodiments described earlier for memory cell 250 in array 280 . As with the other embodiments, the first and second conductivity types can be reversed as a matter of design choice. As with the other embodiments, many other variations and combinations of elements are possible, and the examples described in no way limit the present invention.

FIG. 58 B shows an array 280 V of memory cells 250 V. Due the nature of fin structure 52 A, the most compact layout will typically be with the word lines 70 running perpendicular to the source lines 72 , instead of in parallel as in memory array 280 discussed above. This leads to the structure of array 580 where the cell 250 V is constructed using fin structure 52 A and the source lines 72 a through 72 p run parallel to the bit lines 74 a through 74 p and orthogonal to the word lines 70 a through 70 m . The operation of memory array 280 V is described in commonly assigned U.S. patent application entitled “COMPACT SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED NUMBER OF CONTACTS, METHODS OF OPERATING AND METHODS OF MAKING,” Ser. No. 12/897,528, filed on Oct. 4, 2010 and incorporated by reference above.

FIG. 59 A shows another embodiment of a gated half transistor memory cell 450 (denoted by a dotted line) according to the present invention. FIG. 59 B shows a smaller portion of FIG. 59 A comprising a single memory cell 450 with two cross section lines I-I′ and II-II′. FIG. 23 C shows the cross section designated I-I′ in FIG. 59 B . FIG. 59 D shows the cross section designated II-II′ in FIG. 59 B . Present in FIGS. 59 A through 59 F are substrate 12 , semiconductor surface 14 , bit line region 16 , buried well layer 22 , floating body region 24 , insulating layers 26 and 28 , gate 60 , gate insulator 62 , word line terminal 70 , buried well terminal 72 , bit line terminal 74 and substrate terminal 78 , all of which perform similar functions in the exemplary embodiments of memory cell 450 as they did in the exemplary embodiments of memory cell 250 described above.

Referring now to FIGS. 59 A, 59 B, 59 C and 59 D , the cell 450 includes a substrate 12 of a first conductivity type, such as a p-type conductivity type, for example. Substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. A buried layer 22 of the second conductivity type is provided in the substrate 12 . Buried layer 22 is also formed by an ion implantation process on the material of substrate 12 . Alternatively, buried layer 22 can also be grown epitaxially.

A bit line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body 24 and is exposed at surface 14 . Bit line region 16 is formed by an implantation process formed on the material making up floating body 24 , according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process could be used to form bit line region 16 .

A floating body region 24 of the substrate 12 is bounded by surface 14 , bit line region 16 , insulating layers 26 and 28 and buried layer 22 . Insulating layers 26 and 28 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulating layers 26 and 28 insulate cell 450 from neighboring cells 450 when multiple cells 450 are joined in an array 180 to make a memory device as illustrated in FIG. 61 A . Insulating layer 26 insulates both neighboring body regions 24 and buried regions 22 of adjacent cells memory cells 450 A, 450 , and 450 B, while insulating layer 28 insulates neighboring body regions 24 , but not neighboring buried layer regions 22 , allowing the buried layer 22 to be continuous (i.e. electrically conductive) in one direction in parallel with the II-II′ cut line as shown in FIGS. 59 B and 59 D . As in other embodiments, there is no contact to the buried layer 22 at the semiconductor surface 14 inside the boundary of memory cell 450 .

A gate 60 is positioned in between bit line regions 16 of neighboring cells 450 and 450 A and above the surface 14 , the floating body regions 24 , and one of the adjacent insulating layers 26 as shown in FIG. 59 C . In this arrangement, the gate terminal 70 is coupled to the gates 60 of both memory cells 450 and 450 A. The gate 60 is insulated from surface 14 by an insulating layer 62 . Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. In FIGS. 59 A, 59 B and 59 C , the gate 60 is shown above the insulating layer 26 isolating neighboring cells 450 and 450 A.

Cell 450 further includes word line (WL) terminal 70 electrically connected to gate 60 , bit line (BL) terminal 74 electrically connected to bit line region 16 , source line (SL) terminal 72 electrically connected to the buried layer 22 , and substrate terminal 78 electrically connected to substrate 12 .

As shown in FIG. 59 E , contact to buried well region 22 can be made through region 20 having a second conductivity type, and which is electrically connected to buried well region 22 and buried well terminal 72 , while contact to substrate region 12 can be made through region 28 having a first conductivity type, and which is electrically connected to substrate region 12 and substrate terminal 78 . The SL terminal 72 serves as the back bias terminal for the memory cell 450 .

›DETAILED DESCRIPTION · 34 of 64

As shown in FIG. 59 F , the buried well 22 (and subsequently SL terminal 72 ) may also be shared between two adjacent memory cells 450 and 450 B not sharing the same WL terminal 70 . In this embodiment, insulating layer 26 A is built to a similar depth as insulating layer 28 allowing this connection to be made using buried well 22 . Thus when a plurality of memory cells 450 are arranged in an array the source line terminals 72 are shared between pairs of adjacent rows of cells 450 and the word line terminals 70 are shared between pairs of adjacent rows that are offset by one row from the pairs of rows sharing source line terminal 72 . Thus each memory cell 450 shares a source line terminal with one adjacent cell (e.g., 450 B) and a word line terminal 70 with another adjacent cell (e.g., 450 A). It is worth noting that this connectivity is possible because when memory cells 450 are mirrored in alternate rows when arrayed, while memory cell 50 is not mirrored when arrayed.

FIGS. 60 A through 60 E shown an alternate embodiment of memory cell 450 where a part of the gate 60 can also be formed inside a trench adjacent to the floating body regions 24 of two adjacent memory cells 450 . The primary difference between this embodiment and the one described in FIGS. 59 A through 59 E is that the insulating layers 26 in alternate rows adjacent to the floating body regions 24 and under the gates 60 are replaced with a trench labeled 26 T in FIG. 60 C . This trench can be filled with gate insulator 62 and gate material 60 to form a “T” shaped structure. This allows gate 60 to be adjacent to floating body region 24 on two sides allowing better control of the charge in floating body region 24 in response to electrical signals applied to gate 60 through word line terminal 70 . In particular, operations where word line terminal is driven to a positive voltage potential to provide a boost to the voltage potential of the floating body 24 by means of capacitive coupling will benefit from this arrangement since the capacitance between the gate 60 and the floating body 24 will be substantially increased.

FIG. 60 A shows a top view of one such embodiment of a memory cell 450 (denoted by a dotted line) according to the present invention. FIG. 60 B shows a smaller portion of FIG. 60 A with two cross section lines I-I′ and II-II′. FIG. 60 C shows the cross section designated I-I′ in FIG. 60 B . FIG. 60 D shows the cross section designated II-II′ in FIG. 60 B . Present in FIGS. 60 A through 60 F are substrate 12 , semiconductor surface 14 , region 16 , buried well layer 22 , floating body region 24 , insulating layers 26 and 28 , gate 60 , gate insulator 62 , word line terminal 70 , buried well terminal 72 , bit line terminal 74 and substrate terminal 78 , all of which perform similar functions in this exemplary embodiment as they did in the earlier exemplary embodiments of memory cell 450 described above.

Referring now to FIGS. 60 A, 60 B, 60 C and 60 D , the cell 450 includes a substrate 12 of a first conductivity type, such as a p-type conductivity type, for example. Substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. A buried layer 22 of the second conductivity type is provided in the substrate 12 . Buried layer 22 is also formed by an ion implantation process on the material of substrate 12 . Alternatively, buried layer 22 can also be grown epitaxially.

A region 16 having a second conductivity type, such as n-type, for example, is provided in floating body 24 and is exposed at surface 14 . Region 16 is formed by an implantation process formed on the material making up floating body 24 , according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process could be used to form region 16 .

A floating body region 24 of the substrate 12 is bounded by surface 14 , region 16 , insulating layers 26 , and 28 , buried layer 22 , and trench 26 T. Insulating layers 26 and 28 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulating layers 26 and 28 combined with trench 26 T insulate cell 450 from neighboring cells 450 when multiple cells 450 are joined in an array 480 to make a memory device as illustrated in FIG. 61 A . Insulating layer 26 and trench 26 T together insulate both neighboring body regions 24 and buried regions 22 of adjacent cells memory cells 450 A, 450 , and 450 B, while insulating layer 28 insulates neighboring body regions 24 , but not neighboring buried layer regions 22 , allowing the buried layer 22 to be continuous (i.e. electrically conductive) in one direction in parallel with the II-II′ cut line as shown in FIGS. 60 B and 60 D .

A gate 60 is positioned in trench 26 T in between bit line regions 16 of neighboring cells 450 and 450 A and above the surface 14 over the floating body regions 24 forming a “T” shaped structure as shown in FIG. 60 C . In this arrangement, the gate terminal 70 is coupled to the gates 60 of both memory cells 450 and 450 A. The gate 60 is insulated from floating body regions 24 by an insulating layer 62 both on surface 14 and along the walls and bottom of trench 26 T. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. The trench 26 T could be formed through silicon etching process similar to the STI formation after the STI 26 and 28 have been formed. Instead of filling the trench 26 T with thick oxide, gate oxide 62 could be grown after the trench etch, followed by gate 60 formation.

Cell 450 further includes word line (WL) terminal 70 electrically connected to gate 60 , bit line (BL) terminal 74 electrically connected to region 16 , source line (SL) terminal 72 electrically connected to the buried layer 22 , and substrate terminal 78 electrically connected to substrate 12 .

›DETAILED DESCRIPTION · 35 of 64

As shown in FIG. 60 E , contact to buried well region 22 can be made through region 20 having a second conductivity type, and which is electrically connected to buried well region 22 and buried well terminal 72 , while contact to substrate region 12 can be made through region 28 having a first conductivity type, and which is electrically connected to substrate region 12 and substrate terminal 78 . The SL terminal 72 serves as the back bias terminal for the memory cell 450 .

As shown in FIG. 60 F , the buried well 22 (and subsequently SL terminal 72 ) may also be shared between two adjacent memory cells 450 and 450 B not sharing the same WL terminal 70 . In this embodiment, insulating layer 26 A is built to a similar depth as insulating layer 28 allowing this connection to be made using buried well 22 . Thus when a plurality of memory cells 450 are arranged in an array the source line terminals 72 are shared between pairs of adjacent rows of cells 450 and the word line terminals 70 are shared between pairs of adjacent rows that are offset by one row from the pairs of rows sharing source line terminal 72 . Thus each memory cell 450 shares a source line terminal with one adjacent cell (e.g., 450 B) and a word line terminal 70 with another adjacent cell (e.g., 450 A). It is worth noting that this connectivity is possible because when memory cells 450 are mirrored in alternate rows when arrayed, while memory cell 50 is not mirrored when arrayed.

Persons of ordinary skill in the art will appreciate that many other embodiments of the memory cell 450 other than the exemplary embodiments described in conjunction with FIGS. 59 A through 60 F are possible. For example, the first and second conductivity types may be reversed as a matter of design choice. Other physical geometries may be used like, for example, substrate 12 may be replaced by a well placed in a substrate of the second conductivity type (not shown) as a matter of design choice. Thus the embodiments shown are in no way limiting of the present invention.

FIG. 61 A shows an exemplary memory array 480 of memory cells 450 . In the exemplary array 480 an embodiment of memory cell 450 is chosen where word lines 70 a through 70 n are shared between adjacent rows of memory cells 450 and source lines 72 a through 72 n+ 1 are shared between adjacent rows of memory cells 450 offset by one row. Thus there is one more source line 72 than there are row lines 70 because the top and bottom rows do not have an adjacent row of memory cells 450 to share source lines 72 with. Because the WL terminals 70 a through 70 n and source line terminals 72 a through 72 n+ 1 can be shared between neighboring memory cells, a smaller memory array 480 may be realized since the effective size of memory cell 450 is reduced due the shared features. Alternatively, the memory array 480 of memory cells 450 can be arranged with one more word line 70 than there are source lines 72 with the top and bottom rows each not sharing word line 70 with adjacent rows.

As shown in FIG. 61 B , the circuit schematic for an individual memory cell 450 is identical to that for memory cell 250 as shown in FIG. 37 A , the main differences between memory cells 250 and 450 being the physical construction, relative orientation, and the sharing of control lines. Thus the operating principles of memory cell 450 will follow the principles of the previously described memory cell 250 . The memory cell operations will be described, realizing that the WL and SL terminals are now shared between neighboring memory cells. Persons of ordinary skill in the art will realize the operation of the embodiments of memory cell 450 which share word lines 70 but have separate source lines 72 can be handled identically by manipulating the non-shared source lines 72 identically or by manipulating them in an analogous manner to other rows in the memory array as a matter of design choice.

As illustrated in FIG. 62 , the holding operation for memory cell 450 can be performed in a similar manner to that for memory cell 250 by applying a positive bias to the back bias terminal (i.e. SL terminal 72 coupled to buried well region 22 ) while grounding bit line terminal 74 coupled to bit line region 16 and substrate terminal 78 coupled to substrate 12 . As previously described, the holding operation is relatively independent of the voltage applied to terminal 70 which is preferably grounded in some embodiments. Inherent in the memory cell 450 is n-p-n bipolar device 30 formed by buried well region 22 , floating body 24 , and bit line region 16 .

If floating body 24 is positively charged (i.e. in a logic-1 state), the bipolar transistor 30 formed by bit line region 16 , floating body 24 , and buried well region 22 will be turned on as discussed above in conjunction with FIGS. 37 A through 37 C above. A fraction of the bipolar transistor current will then flow into floating body region 24 (usually referred to as the base current) and maintain the logic-1 data. The efficiency of the holding operation can be enhanced by designing the bipolar device formed by buried well region 22 , floating region 24 , and bit line region 16 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of SL terminal 72 to the base current flowing into the floating region 24 .

For memory cells in the logic-0 state, the bipolar device will not be turned on, and consequently no base hole current will flow into floating body region 24 as discussed above in conjunction with FIGS. 37 A through 37 C above. Therefore, memory cells in state logic-0 will remain in state logic-0.

A periodic pulse of positive voltage can be applied to the SL terminal 72 as opposed to applying a constant positive bias to reduce the power consumption of the memory cell 450 in a manner analogous to that described in conjunction with FIGS. 38 A through 38 D above.

As illustrated in FIG. 62 , an example of the bias condition for a two row holding operation is applied to exemplary memory array 480 . In one particular non-limiting embodiment, about +1.2 volts is applied to SL terminal 72 b , about 0.0 volts is applied to the other source line terminals 72 a and 72 c (not shown) through 72 n+ 1, about 0.0 volts is applied to BL terminals 74 a through 74 p , about 0.0 volts is applied to WL terminals 70 a through 70 n , and about 0.0 volts is applied to substrate terminals 78 a through 78 n+ 1. This will place representative memory cells 450 a , 450 c , 450 d , and 450 f into a holding state. These voltage levels are exemplary only may vary substantially as a matter of design choice and processing technology node and are in no way limiting.

›DETAILED DESCRIPTION · 36 of 64

As illustrated in FIGS. 63 and 64 A through 64 P , the charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 450 . If cell 450 is in a state logic-1 having holes in the body region 24 , then the memory cell will have a higher cell current, compared to if cell 450 is in a state logic-0 having no holes in body region 24 . A sensing circuit typically connected to BL terminal 74 of memory array 480 can then be used to determine the data state of the memory cell. Examples of the read operation are described with reference to Yoshida, Ohsawa-1, and Ohsawa-2 discussed above.

The read operation can be performed by applying the following bias condition to memory cell 450 : a positive voltage is applied to the selected BL terminal 74 , and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70 , zero voltage is applied to the selected SL terminal 72 , and zero voltage is applied to the substrate terminal 78 . The unselected BL terminals will remain at zero voltage, the unselected WL terminals will remain at zero voltage, and the unselected SL terminals will remain at positive voltage.

The bias conditions for an exemplary embodiment for a read operation for the exemplary memory array 480 are shown in FIG. 63 , while the bias conditions during a read operation for selected representative memory cell 450 a are further illustrated in FIGS. 64 A through 64 B and the bias conditions during a read operation for the seven cases illustrated by unselected representative memory cells 450 b through 450 h during read operations are further shown in FIGS. 64 C through 64 P . In particular, the bias conditions for unselected representative memory cell 450 b sharing the same WL terminal 70 a and BL terminal 74 a but not the same SL terminal 72 as the selected representative memory cell 450 a are shown in FIGS. 64 C through 64 D . The bias conditions for unselected representative memory cell 450 c sharing the same SL terminal 72 b and BL terminal 74 a but not the same WL terminal 70 as the selected representative memory cell 450 a are shown in FIGS. 64 E through 64 F . The bias conditions for unselected representative memory cell 450 d sharing the same WL terminal 70 a and SL terminal 72 b but not the same BL terminal 74 as the selected representative memory cell 450 a are shown in FIGS. 64 G through 64 H . FIGS. 64 I through 64 J show the bias conditions for unselected representative memory cell 450 e sharing the same WL terminal 70 a but neither the same SL terminal 72 nor BL terminal 74 as the selected representative memory cell 450 a . FIGS. 64 K through 64 L show the bias conditions for unselected representative memory cell 450 f sharing the same SL terminal 72 b but neither the same WL terminal 70 nor BL terminal 74 as the selected representative memory cell 450 a . The bias conditions for unselected representative memory cell 450 g sharing the same BL terminal 74 a as the selected representative memory cell 450 a but not the same WL terminal 70 nor SL terminal 72 is shown in FIGS. 64 M through 64 N . The bias condition for representative memory cell 450 h not sharing any control terminals as the selected representative memory cell 450 a is shown in FIGS. 64 O through 64 P .

In one particular non-limiting and exemplary embodiment illustrated in FIGS. 63 , 64 A and 64 B , the bias conditions for selected representative memory cell 450 a and are shown. In particular, about 0.0 volts is applied to the selected SL terminal 72 b , about +0.4 volts is applied to the selected bit line terminal 74 a , about +1.2 volts is applied to the selected word line terminal 70 a , and about 0.0 volts is applied to substrate terminal 78 (not shown in FIG. 64 B ).

In the remainder of exemplary array 480 , the unselected bit line terminals 74 b through 74 p remain at 0.0 volts, the unselected word line terminals 70 b through 70 n remain at 0.0 volts, and the unselected SL terminals 72 a and 72 c (not shown in FIG. 63 ) through 72 n+ 1 remain at +1.2 volts. FIGS. 64 C through 64 P show in more detail the unselected representative memory cells 450 b - 450 h in memory array 480 . It is noteworthy that these voltage levels are exemplary only may vary substantially as a matter of design choice and processing technology node, and are in no way limiting.

As shown in FIGS. 63 , 64 C and 64 D , representative memory cell 450 b sharing the same WL terminal 70 a and BL terminal 74 a but not the same SL terminal 72 as the representative selected memory cell 450 a , both the BL and SL terminal are positively biased. The potential difference between the BL and SL terminals (i.e. the emitter and collector terminals of the bipolar device 30 ) is lower compared to the memory cells in the holding mode, reducing the base current flowing to the floating body 24 . However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.

As shown in FIGS. 63 , 64 E and 64 F , representative memory cell 450 c sharing the same SL terminal 72 b and BL terminal 74 a but not the same WL terminal 70 as the selected representative memory cell 450 a , both the WL terminal 72 b and the SL terminal 72 are grounded with the BL terminal positively biased. As a result, memory cell 450 c will still be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 ; while memory cells in state logic-0 will remain in neutral state.

As shown in FIGS. 63 , 64 G and 64 H , representative memory cell 450 d sharing the same WL terminal 70 a and SL terminal 72 b but not the same BL terminal 74 as the selected representative memory cell 450 a , both the SL terminal 72 b and BL terminal 74 b are grounded with the WL terminal 70 a at +1.2V. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently representative memory cell 450 d is no longer in holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.

›DETAILED DESCRIPTION · 37 of 64

As shown in FIGS. 63 , 64 I and 64 J , representative memory cell 450 e sharing the same WL terminal 70 a but not the same SL terminal 72 nor BL terminal 74 as the selected representative memory cell 450 a , the SL terminal remains positively biased. As a result, memory cell 450 e will still be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24 ; while memory cells in state logic-0 will remain in the neutral state.

As shown in FIGS. 63 , 64 K and 64 L , representative memory cell 450 f sharing the same SL terminal 72 b but not the same WL terminal 70 nor BL terminal 74 as the selected representative memory cell 450 a , both the SL terminal 72 and BL terminal 74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cells 450 f is no longer in holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.

As shown in FIGS. 63 , 64 M and 64 N , representative memory cell 450 g sharing the same BL terminal 74 a but not the same WL terminal 70 nor SL terminal 72 as the selected representative memory cell 450 a , a positive voltage is applied to the BL terminal 74 . Less base current will flow into the floating body 24 due to the smaller potential difference between SL terminal 72 and BL terminal 74 (i.e. the emitter and collector terminals of the n-p-n bipolar device 30 ). However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.

As shown in FIGS. 63 , 64 O and 64 P , representative memory cells 450 h not sharing WL, BL, and SL terminals as the selected representative memory cell 450 a , both the SL terminal 72 will remain positively charged and the BL terminal remain grounded ( FIGS. 64 O- 64 P ). As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24 ; while memory cells in state logic-0 will remain in the neutral state.

It is noteworthy that the voltage levels described in all the different cases above are exemplary only may vary substantially from embodiment to embodiment as a matter of both design choice and processing technology node, and are in no way limiting.

A two row write logic-0 operation of the cell 450 is now described with reference to FIG. 65 . A negative bias may be applied to the back bias terminal (i.e. SL terminal 72 ), zero potential may be applied to WL terminal 70 , zero voltage may be applied to BL terminal 72 and substrate terminal 78 . The unselected SL terminal 72 will remain positively biased. Under these conditions, the p-n junction between floating body 24 and buried well 22 of the selected cell 50 is forward-biased, evacuating any holes from the floating body 24 . In one particular non-limiting embodiment, about −0.5 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 70 , and about 0.0 volts is applied to terminal 74 and 78 . However, these voltage levels may vary, while maintaining the relative relationship between the charges applied, as described above.

In FIG. 65 , the selected SL terminal 72 b is biased at about −0.5V while the unselected SL terminals 72 a , and 72 c (not shown) through 72 n+ 1 are biased at about +1.2V, the WL terminals 70 a through 70 n are biased at about 0.0V, the BL terminals 74 a through 74 p are biased at about 0.0V and the substrate terminals 78 a through 78 n+ 1 are biased at about 0.0V. In some embodiments where the substrate is really a well in another substrate (not shown), the substrate terminals may be biased at about −0.5V to avoid unwanted current from the selected SL terminal 72 b . This condition causes all of the memory cells 450 coupled to SL terminal 72 b , including the selected representative memory cells 450 a , 450 c , 450 d , and 450 f , to be written to the logic-0 state.

FIGS. 65 , 66 A and 66 B show an example of bias conditions for the selected and unselected memory cells 450 during a two row write logic-0 operation in memory array 480 . For the selected memory cells, including representative memory cells 450 a , 450 c , 450 d and 450 f , the negative bias applied to SL terminal 72 causes large potential difference between floating body 24 and buried well region 22 . This causes the hole charge in the floating body 24 to be discharged as discussed above. Because the buried well 22 is shared among multiple memory cells 50 , all memory cells 450 sharing the same SL terminal 72 will be written into state logic-0.

An example of bias conditions and an equivalent circuit diagram illustrating the intrinsic n-p-n bipolar devices 30 of unselected memory cells 450 , including representative memory cells 450 b , 450 e , 450 g and 450 h , during write logic-0 operations are illustrated in FIGS. 66 A through 66 B . Since the write logic-0 operation only involves a negative voltage to the selected SL terminal 72 , the bias conditions for all the unselected cells are the same. As can be seen, the unselected memory cells will be in a holding operation, with the BL terminal at about 0.0 volts, WL terminal at zero or negative voltage, and the unselected SL terminal positively biased.

As illustrated in FIG. 67 , a single column write logic-0 operation can be performed by applying a negative bias to the BL terminal 74 as opposed to the SL terminal 72 (as in FIGS. 65 , 66 A, and 66 B ). The SL terminal 72 will be positively biased, while zero voltage is applied to the substrate terminal 78 , and zero voltage is applied to the WL terminal 70 . Under these conditions, all memory cells sharing the same BL terminal 74 will be written into state logic-0 while all the other memory cells 450 in the array 480 will be in the holding state.

›DETAILED DESCRIPTION · 38 of 64

In FIG. 67 , selected BL terminal 74 a may be biased at about −1.2V while the unselected BL terminals 74 b through 74 p may be biased at about 0.0V, the WL terminals 70 a through 70 n may be biased at about 0.0V, the source line terminals 72 a through 27 n+ 1 may be biased at +1.2V, and the substrate terminals 78 a through 78 n+ 1 may be biased at 0.0V. This condition causes all of the memory cells 450 coupled to BL terminal 74 a , including the selected representative memory cells 450 a , 450 b , 450 c , and 450 g , to be written to the logic-0 state while the remaining memory cells 450 , including unselected representative memory cells 450 d , 450 e , 450 f , and 450 h , to be in a holding operation. These voltage levels are exemplary only may vary substantially from embodiment to embodiment as a matter of design choice and processing technology node used, and are in no way limiting.

As illustrated in FIGS. 68 and 69 A through 69 P , a single cell write logic-0 operation that allows for individual bit writing can be performed by applying a positive voltage to WL terminal 70 , a negative voltage to BL terminal 74 , zero or positive voltage to SL terminal 72 , and zero voltage to substrate terminal 78 . Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70 . As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74 , the p-n junction between floating body 24 and bit line region 16 is forward-biased, evacuating any holes from the floating body 24 . To reduce undesired write logic-0 disturb to other memory cells 450 in the memory array 480 , the applied potential can be optimized as follows: if the floating body 24 potential of state logic-1 is referred to V FB1 , then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V FB1 /2 while −V FB1 /2 is applied to BL terminal 74 .

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 450 a : a potential of about 0.0 volts to SL terminal 72 b , a potential of about −0.2 volts to BL terminal 74 a , a potential of about +0.5 volts is applied to WL terminal 70 a , and about 0.0 volts is applied to substrate terminals 78 a through 78 n+ 1; while about +1.2 volts is applied to unselected SL terminals 72 a and 72 c (not shown) through 72 n+ 1, about 0.0 volts is applied to unselected BL terminals 74 b through 74 p , and about 0.0 volts is applied to unselected WL terminals 70 b through 70 n . FIG. 68 shows the bias condition for the selected and unselected memory cells 450 in memory array 480 . However, these voltage levels are exemplary only may vary substantially from embodiment to embodiment as a matter of design choice and processing technology node used, and are in no way limiting.

The bias conditions of the selected representative memory cell 450 a under write logic-0 operation are further elaborated and are shown in FIGS. 69 A through 69 B . As discussed above, the potential difference between floating body 24 and bit line region 16 (connected to BL terminal 74 a ) is now increased, resulting in a higher forward bias current than the base hole current generated by the n-p-n bipolar devices 30 formed by buried well region 22 , floating body 24 , and bit line region 16 . The net result is that holes will be evacuated from floating body 24 .

The unselected memory cells 450 during write logic-0 operations are shown in FIGS. 69 C through 69 P : The bias conditions for memory cell 450 b sharing the same WL terminal 70 a and BL terminal 74 a but not the same SL terminal 72 as the selected memory cell 450 a are shown in FIGS. 69 C through 69 D . The bias conditions for memory cell 450 c sharing the same SL terminal 72 b and BL terminal 74 a but not the same WL terminal 70 as the selected memory cell 450 a are shown in FIGS. 69 E through 69 F . The bias conditions for memory cell 450 d sharing the same WL terminal 70 a and SL terminal 72 b but not the same BL terminal 74 as the selected memory cell 450 are shown in FIGS. 69 G through 69 H . FIGS. 69 I through 69 J show the bias conditions for memory cell 450 e sharing the same WL terminal 70 a but not the same SL terminal 72 nor BL terminal 74 as the selected memory cell 450 a . FIGS. 69 K through 69 L show the bias conditions for memory cell 450 f sharing the same SL terminal 72 b but not the same WL terminal 70 nor BL terminal 74 as the selected memory cell 450 a . The bias conditions for memory cells sharing the same BL terminal 74 a as the selected memory cell 450 a but not the same WL terminal 70 nor SL terminal 72 (e.g. memory cell 450 g ) are shown in FIGS. 69 M through 69 N , while the bias condition for memory cells not sharing the same WL, SL, and BL terminals 70 , 72 , and 74 respectively as the selected memory cell 450 a (e.g. memory cell 450 h ) is shown in FIG. 69 O through 69 P .

The floating body 24 potential of memory cells sharing the WL terminal 70 as the selected memory cell will increase due to capacitive coupling from WL terminal 70 by ΔV FB . For memory cells in state logic-0, the increase in the floating body 24 potential is not sustainable as the forward bias current of the p-n diodes formed by floating body 24 and junction 16 will evacuate holes from floating body 24 . As a result, the floating body 24 potential will return to the initial state logic-0 equilibrium potential. For memory cells in state logic-1, the floating body 24 potential will initially also increase by ΔV FB , which will result in holes being evacuated from floating body 24 . After the positive bias on the WL terminal 70 is removed, the floating body 24 potential will decrease by ΔV FB . If the initial floating body 24 potential of state logic-1 is referred to as V FB1 , the floating body 24 potential after the write logic-0 operation will become V FB1 −ΔV FB . Therefore, the WL potential needs to be optimized such that the decrease in floating body potential of memory cells 50 in state logic-1 is not too large. For example, the maximum floating body potential due to the coupling from the WL potential cannot exceed V FB1 /2.

›DETAILED DESCRIPTION · 39 of 64

As shown in FIGS. 69 C through 69 D , for unselected representative memory cell 450 b sharing the same WL terminal 70 a and BL terminal 74 a but not the same SL terminal 72 as the selected memory cell 450 a , a negative bias is applied to the BL terminal while the SL terminal is positively biased. The potential difference between the BL and SL terminals (i.e. the emitter and collector terminals of the bipolar device 30 ) is greater compared to the memory cells in the holding mode. As a result, the forward bias current of the p-n diode formed by floating body 24 and bit line region 16 is balanced by higher base current of the bipolar device 30 . As a result, memory cell 450 b will still be at holding mode. Thus, when memory cell 450 b is in state logic-1 it will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24 , and when memory cell 450 b is in state logic-0 the bipolar device 30 will remain off leaving the floating body 24 charge level in a neutral state.

As shown in FIGS. 69 E through 69 F , for unselected representative memory cell 450 c sharing the same SL terminal 72 b and BL terminal 74 A but not the same WL terminal 70 as the selected memory cell 450 a , the SL terminal 72 is now grounded with the BL terminal now negatively biased. As a result, the p-n diode formed between floating body 24 and bit line region 16 will be forward biased. For memory cells in state logic-0, the increase in the floating body 24 potential will not change the initial state logic-0 as there is initially no hole stored in the floating body 24 . For memory cells in state logic-1, the net effect is that the floating body 24 potential after write logic-0 operation will be reduced. Therefore, the BL potential also needs to be optimized such that the decrease in floating body potential of memory cells 50 in state logic-1 is not too large. For example, the −V FB1 /2 is applied to the BL terminal 74 . For memory cells in the logic-0 state, the bipolar device 30 remains off leaving the cell in the logic-0 state.

As shown in FIGS. 69 G through 69 H , for unselected representative memory cell 450 d sharing the same WL terminal 70 a and SL terminal 72 b but not the same BL terminal 74 as the selected memory cell 450 a , both the SL terminal 72 and BL terminal 74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cells 450 d is no longer in holding mode. However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.

As shown in FIGS. 69 I through 69 J , for unselected representative memory cell 450 e sharing the same WL terminal 70 a but not the same SL terminal 72 nor BL terminal 74 as the selected memory cell 450 a , the SL terminal is positively biased. As a result, memory cell 450 e will still be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in neutral state.

As shown in FIGS. 69 K through 69 L , for unselected representative memory cell 450 f sharing the same SL terminal 72 b but not the same WL terminal 70 nor BL terminal 74 as the selected memory cell 450 a , both the SL terminal 72 and BL terminal 74 are grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cells 450 f is no longer in holding mode. However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.

As shown in FIGS. 69 M through 69 N , for unselected representative memory cell 450 g sharing the same BL terminal 74 a but not the same WL terminal 70 nor SL terminal 72 , a negative bias is applied to the BL terminal while the SL terminal remains positively biased. The potential difference between the BL and SL terminals (i.e. the emitter and collector terminals of the bipolar device 30 ) is greater compared to the memory cells in the holding mode. As a result, the forward bias current of the p-n diode formed by floating body 24 and bit line region 16 is balanced by higher base current of the bipolar device 30 . As a result, memory cell 450 g will still be at holding mode. Thus memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in neutral state.

As shown in FIGS. 69 O through 69 P , for unselected representative memory cell 450 h not sharing WL, BL, and SL terminals 70 , 74 , and 72 respectively as the selected memory cell 450 a , both the SL terminal 72 will remain positively charged and the BL terminal will remain grounded. As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in neutral state.

Several different types of a write logic-0 operation have been described as examples illustrating the present invention. While exemplary voltage levels have been given, the actual voltages used in practice may vary substantially from embodiment to embodiment as a matter of design choice and processing technology node used, and are in no way limiting.

›DETAILED DESCRIPTION · 40 of 64

A write logic-1 operation can be performed on memory cell 450 by means of impact ionization as described for example with reference to Lin cited above, or by means of a band-to-band tunneling (GIDL) mechanism, as described for example with reference to Yoshida cited above.

Illustrated in FIG. 70 , is an example of the bias condition of the selected memory cell 450 a in memory array 480 under a band-to-band tunneling (GIDL) write logic-1 operation. The negative bias applied to the WL terminal 70 a and the positive bias applied to the BL terminal 74 a of the selected representative memory cell 450 a result in hole injection to the floating body 24 of the selected memory cell 450 as discussed above with reference to Yoshida. The SL terminal 72 and the substrate terminal 78 are grounded during the write logic-1 operation.

As further illustrated in FIGS. 71 A and 71 B , in one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 450 a : a potential of about 0.0 volts is applied to SL terminal 72 b , a potential of about +1.2 volts is applied to BL terminal 74 a , a potential of about −1.2 volts is applied to WL terminal 70 a , and about 0.0 volts is applied to substrate terminal 78 (not shown in FIG. 71 B ). This bias condition bends the energy bands upward in the portion of bit line region 16 near the gate 60 in selected representative memory cell 450 a creating GIDL current on the bit line (electrons) while injecting holes into the floating body 24 charging it up to a logic-1 level.

Also shown in FIG. 70 , the following bias conditions are applied to the unselected terminals: about +1.2 volts is applied to unselected SL terminals 72 a and 72 c (not shown) through 72 n+ 1, about 0.0 volts is applied to unselected BL terminals 74 b through 74 p , a potential of about 0.0 volts is applied to unselected WL terminals 70 b through 70 n+ 1, and about 0.0 volts is applied to substrate terminals 78 a through 78 n+ 1.

The unselected memory cells during write logic-1 operations are shown in FIGS. 71 C through 71 O : The bias conditions for memory cell 450 b sharing the same WL terminal 70 a and BL terminal 74 a but not the same SL terminal 72 as the selected memory cell 450 a are shown in FIGS. 71 C through 71 D . The bias conditions for memory cell 450 c sharing the same SL terminal 72 b and BL terminal 74 a but not the same WL terminal 70 as the selected memory cell 450 a are shown in FIGS. 71 E through 71 F . The bias conditions for memory cell 450 d sharing the same WL terminal 70 a and SL terminal 72 b but not the same BL terminal 74 as the selected memory cell 450 a are shown in FIGS. 71 G through 71 H . FIGS. 71 I through 71 J show the bias conditions for memory cell 450 e sharing the same WL terminal 70 a but not the same SL terminal 72 nor BL terminal 74 as the selected memory cell 450 a . FIGS. 71 K through 71 L show the bias conditions for memory cell 450 f sharing the same SL terminal 72 b but not the same WL terminal 70 nor BL terminal 74 as the selected memory cell 450 a . The bias conditions for memory cells sharing the same BL terminal 74 a as the selected memory cell 450 a but not the same WL terminal 70 nor SL terminal 72 (e.g. memory cell 450 g ) are shown in FIGS. 71 M through 71 N , while the bias condition for memory cells not sharing the WL, SL, and BL terminals 70 , 72 and 74 respectively, as the selected memory cell 450 a (e.g. memory cell 450 h ) are shown in FIG. 71 O through 71 P .

As shown in FIGS. 71 C through 71 D , for unselected representative memory cell 450 b sharing the same WL terminal 70 a and BL terminal 74 a but not the same SL terminal 72 as the selected memory cell 450 a , both BL and SL terminals are positively biased. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 b is no longer in holding mode. However, because the write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As shown in FIGS. 71 E through 71 F , for unselected representative memory cell 450 c sharing the same SL terminal 72 b and BL terminal 74 a but not the same WL terminal 70 as the selected memory cell 450 a , the SL terminal 72 is now grounded with the BL terminal now positively biased. As a result, memory cell 450 c will be in a holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 and memory cells in state logic-0 will remain in the neutral state.

As shown in FIGS. 71 G through 71 H , for unselected representative memory cell 450 d sharing the same WL terminal 70 a and SL terminal 72 b but not the same BL terminal 74 as the selected memory cell 450 a , both the SL terminal 72 and BL terminal 74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 d is not in a holding mode. However, because the write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As shown in FIGS. 71 I through 71 J , for unselected representative memory cell 450 e sharing the same WL terminal 70 a but not the same SL terminal 72 nor BL terminal 74 as the selected memory cell 450 a , the SL terminal remains positively biased. As a result, memory cell 450 e will still be in a holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24 , and while memory cells in state logic-0 will remain in a neutral state.

›DETAILED DESCRIPTION · 41 of 64

As shown in FIGS. 71 K through 71 L , for unselected representative memory cell 450 f sharing the same SL terminal 72 b but not the same WL terminal 70 nor BL terminal 74 as the selected memory cell 450 a , both the SL terminal 72 and BL terminal 74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 f is no longer in a holding mode. However, because the write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As shown in FIGS. 71 M through 71 N , for unselected representative memory cell 450 g sharing the same BL terminal 74 a but not the same WL terminal 70 nor SL terminal 72 , a positive bias is applied to the BL terminal and the SL terminal. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 g is no longer in a holding mode. However, because write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As shown in FIGS. 71 O through 71 P , for unselected representative memory cell 450 h not sharing WL, BL, and SL terminals 70 , 74 and 72 respectively as the selected memory cell, the SL terminal 72 n+ 1 will remain positively charged and the BL terminal 74 b and the WL terminal 70 n are grounded. As can be seen, memory cell 450 h will be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in the neutral state.

Illustrated in FIG. 72 , is an example of the bias condition of the selected memory cell 450 a in memory array 480 under an impact ionization write logic-1 operation. The positive bias applied to the WL terminal 70 a and the positive bias applied to the BL terminal 74 a of the selected representative memory cell 450 a results in hole injection to the floating body 24 of the selected memory cell 450 as discussed above with reference to Lin cited above. The SL terminal 72 b and the substrate terminals 78 a through 78 n+ 1 are grounded during the write logic-1 operation.

As further illustrated in FIG. 72 , in one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 450 a : a potential of about 0.0 volts is applied to SL terminal 72 b , a potential of about +1.2 volts is applied to BL terminal 74 a , a potential of about +1.2 volts is applied to WL terminal 70 a , and about 0.0 volts is applied to substrate terminals 78 a through 78 n+ 1. This bias condition causes selected representative memory cell 450 a to conduct current due to the impact ionization mechanism discussed with reference to Lin cited above. The combination of +1.2V on word line terminal and +1.2V on bit line terminal 74 a turns on the bipolar device 30 in representative memory cell 450 a regardless of its prior logic state and generating sufficient hole charge in its floating body 24 to place it in the logic-1 state.

Also shown in FIG. 72 , the following bias conditions are applied to the unselected terminals: about +1.2 volts is applied to unselected SL terminals 72 a and 72 c (not shown) through 72 n+ 1, about 0.0 volts is applied to unselected BL terminals 74 b through 74 p , a potential of about 0.0 volts is applied to unselected WL terminals 70 b through 70 n+ 1, and about 0.0 volts is applied to substrate terminals 78 a through 78 n+ 1.

For unselected representative memory cell 450 b sharing the same WL terminal 70 a and BL terminal 74 a but not the same SL terminal 72 as the selected memory cell 450 a , both BL and SL terminals are positively biased. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 b is no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

For unselected representative memory cell 450 c sharing the same SL terminal 72 b and BL terminal 74 a but not the same WL terminal 70 as the selected memory cell 450 a , the SL terminal 72 b is now grounded with the BL terminal now positively biased. As a result, memory cell 450 c will be in a holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in the neutral state.

For unselected representative memory cell 450 d sharing the same WL terminal 70 a and SL terminal 72 b but not the same BL terminal 74 as the selected memory cell 450 a , both the SL terminal 72 and BL terminal 74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 d is not in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

For unselected representative memory cell 450 e sharing the same WL terminal 70 a but not the same SL terminal 72 nor BL terminal 74 as the selected memory cell 450 a , the SL terminal remains positively biased. As a result, memory cell 450 e will still be in a holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24 , and while memory cells in state logic-0 will remain in a neutral state. There is a possible write disturb issue with memory cell 450 e in this case which will be discussed in more detail below in conjunction with FIGS. 73 A through 73 B .

›DETAILED DESCRIPTION · 42 of 64

For unselected representative memory cell 450 f sharing the same SL terminal 72 b but not the same WL terminal 70 nor BL terminal 74 as the selected memory cell 450 a , both the SL terminal 72 and BL terminal 74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 f is no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

For unselected representative memory cell 450 g sharing the same BL terminal 74 a but not the same WL terminal 70 nor SL terminal 72 , a positive bias is applied to the BL terminal 74 a and the SL terminal 72 n+ 1. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 g is no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

For unselected representative memory cell 450 h not sharing WL, BL, and SL terminals 70 , 74 and 72 respectively as the selected memory cell 450 a , the SL terminal 72 n+ 1 will remain positively charged and the BL terminal 74 b and the WL terminal 70 n are grounded. As can be seen, memory cell 450 h will be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24 ; while memory cells in state logic-0 will remain in neutral state.

FIGS. 73 A and 73 B illustrate the bias conditions of representative memory cell 450 e under the bias conditions shown in FIG. 72 . Memory cell 450 e is coupled to word line terminal 70 a biased at +1.2V, bit line terminal 74 b biased at 0.0V, and source line terminal 72 a biased at +1.2V. The concern is that the floating body region 24 of memory cell 450 e boosted by capacitive coupling from word line 70 a while having 1.2 volts of bias across it—albeit of the opposite voltage potential of selected representative memory cell 450 a . If bipolar device 30 were to turn on under these conditions, a write disturb condition (writing an unwanted logic-1 in an unselected memory cell) would occur with a logic-1 being written into unselected memory cell 450 e.

One solution to the write disturb in representative memory cell 450 e is to design memory cell 450 such that the impact ionization is less efficient at generating charge carriers when the source line terminal 72 is positively biased than it is in the case when the bit line terminal 74 is positively biased using techniques known in the art. This creates enough current to place representative memory cell 450 e in a holding mode while generating a larger current sufficient for writing a logic-1 in memory cell 450 a.

Alternatively, a different set of bias conditions may be used as illustrated in FIG. 37 which shows another example of writing logic-1 into selected memory cell 450 a in memory array 480 using impact ionization. As in FIG. 72 , the positive bias applied to the WL terminal 70 a and the positive bias applied to the BL terminal 74 a of the selected representative memory cell 450 a results in hole injection to the floating body 24 of the selected memory cell 450 as discussed above with reference to Lin cited above. The SL terminal 72 b and the substrate terminals 78 a through 78 n+ 1 are grounded during the write logic-1 operation. The difference in this write logic-1 operation are the bias conditions of the unselected bit lines 74 b through 74 p and the unselected source lines 72 a and 72 c (not shown) through 72 n+ 1.

As further illustrated in FIG. 74 , in one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 450 a : a potential of about 0.0 volts is applied to SL terminal 72 b , a potential of about +1.2 volts is applied to BL terminal 74 a , a potential of about +1.2 volts is applied to WL terminal 70 a , and about 0.0 volts is applied to substrate terminals 78 a through 78 n+ 1. This bias condition causes selected representative memory cell 450 a to conduct current due to the impact ionization mechanism discussed with reference to Lin cited above. The combination of +1.2V on word line terminal and +1.2V on bit line terminal 74 a turns on the bipolar device 30 in representative memory cell 450 a regardless of its prior logic state and generating sufficient hole charge in its floating body 24 to place it in the logic-1 state.

Also shown in FIG. 74 , the following bias conditions are applied to the unselected terminals: about +0.6 volts is applied to unselected SL terminals 72 a and 72 c (not shown) through 72 n+ 1, about +0.6 volts is applied to unselected BL terminals 74 b through 74 p , a potential of about 0.0 volts is applied to unselected WL terminals 70 b through 70 n+ 1, and about 0.0 volts is applied to substrate terminals 78 a through 78 n+ 1.

For unselected representative memory cell 450 b sharing the same WL terminal 70 a and BL terminal 74 a but not the same SL terminal 72 as the selected memory cell 450 a , both BL and SL terminals are positively biased with a larger bias applied to the BL than the SL. As a result, bipolar device 30 is on and memory cell 450 b is in a holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in the neutral state.

›DETAILED DESCRIPTION · 43 of 64

For unselected representative memory cell 450 d sharing the same WL terminal 70 a and SL terminal 72 b but not the same BL terminal 74 as the selected memory cell 450 a , the SL terminal 72 b is now grounded and the BL terminal 74 b has a slight positive bias. As a result, memory cell 450 d will be in a holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in the neutral state.

For unselected representative memory cell 450 e sharing the same WL terminal 70 a but not the same SL terminal 72 nor BL terminal 74 as the selected memory cell 450 a , the SL terminal 72 a and the BL terminal 74 b both have a slight positive bias. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 e is no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body. This also eliminates the potential write disturb condition for representative memory cell 450 e present with the bias conditions of FIGS. 35 , 36 A and 36 B .

For unselected representative memory cell 450 f sharing the same SL terminal 72 b but not the same WL terminal 70 nor BL terminal 74 as the selected memory cell 450 a , the SL terminal 72 b is grounded and BL terminal 74 b has a small positive bias. As a result, memory cell 450 f will be in a holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in the neutral state.

For unselected representative memory cell 450 g sharing the same BL terminal 74 a but not the same WL terminal 70 nor SL terminal 72 , a positive bias is applied to the BL terminal 74 a and a smaller positive bias is applied to SL terminal 72 n+ 1. As a result, memory cell 450 g will be in a holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in the neutral state.

For unselected representative memory cell 450 h not sharing WL, BL, and SL terminals 70 , 74 and 72 respectively as the selected memory cell 450 a , the SL terminal 72 n+ 1 and the BL terminal 74 b will have a slight positive bias while the WL terminal 70 n is grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cell 450 e is no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

Different structures and methods of operation have been discussed with respect to exemplary memory array 480 comprised of a plurality of memory cells 450 . Many other embodiments are possible within the scope of the invention. For example, regions of the first conductivity type may be changed from p-type to n-type and regions of the second conductivity type may be changed from n-type to p-type combined with a reversal of the polarities of the bias voltages for various operations. The bias levels themselves are exemplary only and will vary from embodiment to embodiment as a matter of design choice. Memory array 480 may be altered so that the outside rows share a source line 72 with the adjacent row and have a dedicated word line 70 . Many other embodiments will readily suggest themselves to persons skilled in the art, thus the invention is not to be limited in any way except by the appended claims.

It is noteworthy that memory cell 250 V constructed using either of the fin structures 52 and 52 A described in conjunction with FIGS. 56 through 58 B can be used to replace memory cell 450 in memory array 480 with shared word lines with or without shared source lines and will function in a manner similar to that described for memory cell 450 . Many other modifications may also made to array 450 . For example, the first and second conductivity types may be reversed in either memory cell 450 or memory cell 250 V with reversal of the relative polarities of the applied voltages. All of the voltage levels described are exemplary only and will vary from embodiment to embodiment as a matter of design choice. Thus the invention is not to be limited in any way.

FIG. 75 A shows another embodiment of the memory device 450 , in which adjacent regions 16 , which are separated by insulating layer 28 , share a common connection to BL terminal 74 through contact 64 . By sharing a common connection to the BL terminal 74 , a more compact memory cell can be obtained as only one contact is required for each two memory cells 450 .

Another embodiment of memory cell 450 is shown in FIG. 75 B , where bit line region 16 and contact 64 are now shared between two adjacent memory cells 450 . Isolation of the adjacent floating body 24 regions of a first conductivity type is achieved through both insulating region 33 and bit line region 16 of a second conductivity type.

FIGS. 76 A through 76 O describe a method of manufacturing memory cell 450 as shown in FIG. 75 B created using, in part, a replacement insulator technique like that described in S_Kim and Oh discussed above to create insulating region 33 .

A method of manufacturing memory cell 450 as shown in FIG. 75 B will be described with reference to FIGS. 76 A through 76 AA . These 27 figures are arranged in groups of three related views, with the first figure of each group being a top view, the second figure of each group being a vertical cross section of the top view in the first figure of the group designated I-I′, and the third figure of each group being a horizontal cross section of the top view in the first figure of the group designated II-II′. Thus FIGS. 76 A, 76 D, 76 G, 76 J, 76 M, 76 P, 76 S, 76 V, and 76 Y are a series of top views of the memory cell 450 at various stages in the manufacturing process, FIGS. 76 B, 76 E, 76 H, 76 K, 76 N, 76 Q, 76 T, 76 W , and 76 Z are their respective vertical cross sections labeled I-I′, and FIGS. 76 C, 76 F, 76 I, 76 L, 76 O, 76 R, 76 U, 76 X, and 76 AA are their respective horizontal cross sections labeled Identical reference numbers from earlier drawing figures appearing in FIGS. 76 A through 76 AA represent similar, identical, or analogous structures as previously described in conjunction with the earlier drawing figures. Here “vertical” means running up and down the page in the top view diagram and “horizontal” means running left and right on the page in the top view diagram. In the physical embodiment of memory cell 450 , both cross sections are “horizontal” with respect to the surface of the semiconductor device.

›DETAILED DESCRIPTION · 44 of 64

As illustrated in FIGS. 76 A through 76 C , a thin conductive region 202 (e.g. 300 A in an exemplary 130 nm process, though this will vary with embodiments in different process technologies and geometries) is grown on the surface of substrate 12 . The conductive region 202 is comprised of a different material from the materials of the substrate region 12 so that it may be selectively etched away later without simultaneous unwanted etching of substrate 12 . For example, the conductive region 202 could be made of silicon germanium (SiGe) material, while substrate 12 could be made of silicon.

As illustrated in FIGS. 76 D through 76 F , a lithography process is then performed to pattern the conductive region 202 . Subsequently, layer 202 is etched, followed by another conductive region 204 growth. As an example, the thickness of region 204 is about 500 A in an exemplary 130 nm process. Region 204 may comprise of the same materials forming substrate 12 , for example silicon. A planarization step can then be performed to ensure a planar surface. The resulting structure can be seen in FIGS. 76 D through 76 F .

As illustrated in FIGS. 76 G through 76 H , a trench formation process is then performed, which follows a similar sequence of steps as shown in FIGS. 2 A through 2 I, i.e. formation of silicon oxide 220 , polysilicon 222 , and silicon nitride 224 layers, followed by lithography patterning and etch processes. Trench 216 is etched such that the trench depth is deeper than that of trench 208 . For example, the trench 208 depth is about 1200 A, while the trench 216 depth is about 2000 A in an exemplary 130 nm process. The resulting structures are shown in FIGS. 76 G through 76 I .

As illustrated in FIGS. 76 J through 76 L , this is then followed by silicon oxidation step, which will grow silicon oxide films in trench 208 and trench 216 . For example, about 4000 A silicon oxide can be grown in an exemplary 130 nm process. A chemical mechanical polishing step can then be performed to polish the resulting silicon oxide films so that the silicon oxide layer is flat relative to the silicon surface. A silicon dry etching step can then be performed so that the remaining silicon oxide layer height is about 300 A from the silicon surface in an exemplary 130 nm process. The silicon nitride layer 224 and the polysilicon layer 222 can then be removed, followed by a wet etch process to remove silicon oxide layer 220 (and a portion of the silicon oxide films formed in the area of former trench 208 and trench 216 ). FIGS. 76 J through 76 L show the insulating layers 26 and 28 formed following these steps.

As illustrated in FIGS. 76 M through 76 O , an oxide etch is then performed to recess the oxide regions 26 and 28 (for example by about 1000 A) to expose the conductive region 202 . A wet etch process is then performed to selectively remove region 202 leaving an gap 203 under an overhanging portion of region 204 . The resulting structures following these steps are shown in FIGS. 76 M through 76 O .

As illustrated in FIGS. 76 P through 76 R , the resulting gap region 203 is then oxidized to form a buried oxide region 33 . Recessing insulating region 26 down to the surface of substrate 12 allows access for the etch of region 202 to form gap 203 and then subsequent oxide growth in gap 203 to form buried oxide region 33 . The overhanging portion of region 204 constrains the oxide growth in gap space 203 to keep the buried oxide region 33 from growing to the surface. The resulting structures are shown in FIGS. 76 P through 76 R .

As illustrated in FIGS. 76 S through 76 U , an oxide deposition of about 1000 A is then performed followed by a planarization process. This is then followed by an ion implantation step to form the buried well region 22 . The ion implantation energy is optimized such that the buried layer region 22 is formed shallower than the bottom of the insulating layer 26 . As a result, the insulating layer 26 isolates buried layer region 22 between adjacent cells. On the other hand, the buried layer region 22 is formed such that insulating layers 28 and 33 do not isolate buried layer region 22 , allowing buried layer region 22 to be continuous in the direction of II-II′ cross section line. Following these steps, the resulting structures are shown in FIGS. 76 S through 76 U .

As illustrated in FIGS. 76 V through 76 X , a silicon oxide layer (or high-dielectric materials) 62 is then formed on the silicon surface (e.g. about 100 A in an exemplary 130 nm process), followed by a polysilicon (or metal) gate 60 deposition (e.g. about 500 A in an exemplary 130 nm process). A lithography step is then performed to form the pattern for the gate and word line, followed by etching of the polysilicon and silicon oxide layers where they are not waned. The resulting structure is shown in FIGS. 76 V- 76 X .

As illustrated in FIGS. 76 Y through 76 AA , another ion implantation step is then performed to form the bit line region 16 of a second conductivity type (e.g. n-type conductivity). The gate 60 and the insulating layers 26 and 28 serve as masking layer for the implantation process such that regions of second conductivity are not formed outside bit line region 16 . This is then followed by backend process to form contact and metal layers.

FIGS. 77 A through 77 F illustrate an embodiment of a Gateless Half Transistor memory cell. Memory cell 550 according to the present invention eliminates the gate terminal present in earlier memory cells such as memory cell 250 allowing a more compact layout since some design rules like gate-to-contact-spacing no longer affect the minimum cell size.

Present in FIGS. 77 A through 77 F are substrate 12 of the first conductivity type, buried layer 22 of the second conductivity type, bit line region 16 of the second conductivity type, region of the second conductivity type 20 , region of the first conductivity type 21 , buried layer region 22 , floating body 24 of the first conductivity type, insulating regions 26 and 28 , source line terminal 72 , and substrate terminal 78 all of which perform substantially similar functions in memory cell 550 as in previously discussed embodiment memory cell 250 . The primary difference between memory cell 550 and memory cell 250 previously discussed is the absence of gate 60 and gate insulator 62 . As in other embodiments, there is no contact to the buried layer 22 at the semiconductor surface 14 inside the boundary of memory cell 550 .

›DETAILED DESCRIPTION · 45 of 64

The manufacturing of memory cell 550 is substantially similar to the manufacturing of memory cell 250 described in conjunction with FIGS. 36 A through 36 U , except that instead of a lithographic step for forming gate 60 , a different lithographic step is needed to pattern bit line region 16 for implantation or diffusion.

FIG. 77 A illustrates a top view of memory cell 550 with several near neighbors.

FIG. 77 B illustrates a top view a single memory cell 550 with vertical cut line I-I′ and horizontal cut line II-II′ for the cross sections illustrated in FIGS. 77 C and 77 D respectively.

FIG. 77 E shows how memory cell 550 may have its buried layer 22 coupled to source line terminal 72 through region 20 of the second conductivity type and its substrate 12 coupled to substrate terminal 78 through region of first conductivity type 21 .

FIG. 77 F shows exemplary memory array 580 which will be used in subsequent drawing figures to illustrate the various operations that may be performed on memory cell 550 when arranged in an array to create a memory device. Array 580 comprises in part representative memory cells 550 a , 550 b , 550 c and 550 d . In operations where a single memory cell is selected, representative memory cell 550 a will represent the selected cell while the other representative memory cells 550 b , 550 c and 550 d will represent the various cases of unselected memory cells sharing a row, sharing a column, or sharing neither a row or a column respectively with selected representative memory cell 550 a . Similarly in the case of operations performed on a single row or column, representative memory cell 550 a will always be on the selected row or column.

While the drawing figures show the first conductivity type as p-type and the second conductivity type as n-type, as with previous embodiments the conductivity types may be reversed with the first conductivity type becoming n-type and the second conductivity type becoming p-type as a matter of design choice in any particular embodiment.

The memory cell states are represented by the charge in the floating body 24 , which modulates the intrinsic n-p-n bipolar device 230 formed by buried well region 22 , floating body 24 , and BL bit line region 16 . If cell 550 has holes stored in the body region 24 , then the memory cell will have a higher bipolar current (e.g. current flowing from BL to SL terminals during read operation) compared to if cell 550 does not store holes in body region 24 .

The positive charge stored in the body region 24 will decrease over time due to the p-n diode leakage formed by floating body 24 and bit line region 16 and buried layer 22 and due to charge recombination. A unique capability of the invention is the ability to perform the holding operation in parallel to all memory cells of the array.

An entire array holding operation is illustrated in FIG. 78 A while a single row holding operation is illustrated in FIG. 78 B . The holding operation can be performed in a manner similar to the holding operation for memory cell 250 by applying a positive bias to the back bias terminal (i.e. SL terminal 72 ) while grounding terminal 74 and substrate terminal 78 . If floating body 24 is positively charged (i.e. in a state logic-1), the n-p-n bipolar transistor 230 formed by BL bit line region 16 , floating body 24 , and buried well region 22 will be turned on.

A fraction of the bipolar transistor current will then flow into floating region 24 (usually referred to as the base current) and maintain the state logic-1 data. The efficiency of the holding operation can be enhanced by designing the bipolar device formed by buried well region 22 , floating region 24 , and bit line region 16 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of SL terminal 72 to the base current flowing into the floating region 24 .

For memory cells in state logic-0 data, the bipolar device will not be turned on, and consequently no base hole current will flow into floating region 24 . Therefore, memory cells in state logic-0 will remain in state logic-0.

A periodic pulse of positive voltage can be applied to the SL terminal 72 as opposed to applying a constant positive bias to reduce the power consumption of the memory cell 550 .

An example of the bias condition for the holding operation is hereby provided: zero voltage is applied to BL terminal 74 , a positive voltage is applied to SL terminal 72 , and zero voltage is applied to the substrate terminal 78 . In one particular non-limiting embodiment, about +1.2 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 74 , and about 0.0 volts is applied to terminal 78 . However, these voltage levels may vary from embodiment to embodiment as a matter of design choice.

In the entire array holding operation of FIG. 78 A , all of the source line terminals 72 a through 72 n are biased at +1.2V, all of the bit lines 74 a through 74 p are biased to 0.0V, and all of the source terminals 78 a through 78 n are biased to 0.0V. This places all of the cells in memory array 580 in the hold state.

In the single row hold operation of FIG. 78 B , selected source line terminal 72 a is biased at +1.2V while the unselected source line terminals 72 b (not shown) through 72 n are biased at 0.0V, all of the bit lines 74 a through 74 p are biased to 0.0V, and all of the source terminals 78 a through 78 n are biased to 0.0V. This places all of the selected cells in memory array 280 in the hold state.

A single memory cell read operation is illustrated in FIGS. 79 and 80 A through 80 H . The read operation for memory cell 550 can be performed by sensing the current of the bipolar device 230 by applying the following bias condition: a positive voltage is applied to the selected BL terminal 74 , zero voltage is applied to the selected SL terminal 72 , and zero voltage is applied to the substrate terminal 78 . The positive voltage applied to the selected BL terminal is less than or equal to the positive voltage applied to the SL terminal during holding operation. The unselected BL terminals will remain at zero voltage and the unselected SL terminals will remain at positive voltage.

›DETAILED DESCRIPTION · 46 of 64

FIG. 79 shows the bias condition for the selected memory cell 550 a and unselected memory cells 550 b , 550 c , and 550 d in memory array 280 . In this particular non-limiting embodiment, about 0.0 volts is applied to the selected SL terminal 72 a while about 0.0V is applied to the unselected source line terminals 72 b (not shown) through 72 n , about +1.2 volts is applied to the selected BL terminal 74 a while 0.0V is applied to the unselected bit line terminals 74 b through 74 p , and about 0.0 volts is applied to substrate terminals 78 a through 78 n . These voltage levels are exemplary only and may vary from embodiment to embodiment.

In FIGS. 80 A and 80 B , the bias conditions for selected representative memory cell 550 a are shown. In this particular non-limiting embodiment, about 0.0 volts is applied to the selected SL terminal 72 a , about +1.2 volts is applied to the selected BL terminal 74 a , and about 0.0 volts is applied to substrate terminal 78 (not shown). This causes current to flow through intrinsic bipolar device 230 if the floating body is positively charged and no current to flow if the floating body is discharged since the bipolar device 230 is off.

The unselected memory cells during read operations are shown in FIGS. 80 C through 80 H . The bias conditions for memory cells sharing the same row (e.g. memory cell 550 b ) are shown in FIGS. 80 C and 80 D . The bias conditions for memory cells sharing the same column (e.g. memory cell 550 c ) as the selected memory cell 550 a are shown in FIGS. 80 E and 80 F . The bias conditions for memory cells sharing neither the same row nor the same column as the selected memory cell 550 a (e.g. memory cell 550 d ) are shown in FIG. 80 G- 80 H .

As illustrated in FIGS. 80 C and 80 D , for memory cell 550 b sharing the same row as the selected memory cell 550 a , the SL terminal 72 a and the BL terminal 74 p are both biased to 0.0V and consequently these cells will not be at the holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As illustrated in FIGS. 80 E and 80 F , for memory cell 550 c sharing the same column as the selected memory cell 550 a , a positive voltage is applied to the BL terminal 74 a and SL terminal 72 n . No base current will flow into the floating body 24 because there is no potential difference between SL terminal 72 and BL terminal 74 (i.e. the emitter and collector terminals of the n-p-n bipolar device 230 ). However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As illustrated in FIGS. 80 G and 80 H , for memory cell 550 d sharing neither the same row nor the same column as the selected memory cell 550 a , both the SL terminal 72 n will remain positively charged and the BL terminal 74 p remain grounded. Representative memory cell 550 d will be in the holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 230 will generate hole current to replenish the charge in floating body 24 , while memory cells in state logic-0 will remain in neutral state.

The various voltage bias levels above are exemplary only. They will vary from embodiment to embodiment as a function of both design choice and the process technology used.

FIG. 81 illustrates a single row write logic-0 operation while FIGS. 82 A and 82 B illustrate the biasing conditions and operation of unselected representative memory cell 550 c . In FIG. 81 the selected row SL terminal 72 a is biased negatively at about −0.5V while the unselected row SL terminals 72 b (not shown) through 72 n are biased at about 0.0V, all the BL terminals 74 a through 74 p are biased at 0.0V, and all the substrate terminals 78 a through 78 n are biased at 0.0V. This causes the selected cells 550 like representative memory cells 550 a and 550 b to have their bipolar devices turn on due to forward bias on the floating body 24 to buried layer 22 junction evacuating the holes from the floating body 24 .

FIGS. 82 A and 82 B show the operation of unselected representative memory cell 550 c which in this case is representative of all the memory cells 550 in memory array 280 not on the selected row. Memory cell 550 c has its SL terminal 72 n at +1.2V and its BL terminal 74 a at 0.0V which corresponds to the holding operation described above in conjunction with FIGS. 78 A and 78 B .

A write logic-0 operation can also be performed on a column basis by applying a negative bias to the BL terminal 74 as opposed to the SL terminal 72 . The SL terminal 72 will be zero or positively biased, while zero voltage is applied to the substrate terminal 78 . Under these conditions, all memory cells sharing the same BL terminal 74 will be written into state logic-0 and all the other cells will be in a holding operation.

The various voltage bias levels above are exemplary only. They will vary from embodiment to embodiment as a function of both design choice and the process technology used.

A write logic-1 operation can be performed on memory cell 550 through impact ionization as described for example with reference to Lin above.

An example of the bias condition of the selected memory cell 550 a under impact ionization write logic-1 operation is illustrated in FIG. 83 and FIGS. 84 A through 84 B . A positive bias is applied to the BL terminal 74 , while zero voltage is applied to the selected SL terminal 72 and substrate terminal 78 . The positive bias applied to the BL terminal 74 is greater than the positive voltage applied to the SL terminal 72 during holding operation. The positive bias applied to the BL terminal is large enough to turn on bipolar device 230 regardless of the initial state of the data in selected memory cell 550 a . This results in a base hole current to the floating body 24 of the selected memory cell 550 a charging it up to a logic-1 state.

›DETAILED DESCRIPTION · 47 of 64

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 550 a : a potential of about 0.0 volts is applied to selected SL terminal 72 a , a potential of about +2.0 volts is applied to selected BL terminal 74 a , and about 0.0 volts is applied to substrate terminals 78 a through 78 n . The following bias conditions are applied to the unselected terminals: about +1.2 volts is applied to SL terminals 72 b (not shown) through 72 n , and about 0.0 volts is applied to BL terminals 74 b through 74 p . FIG. 83 shows the bias condition for the selected and unselected memory cells in memory array 580 . The various voltage bias levels above are exemplary only. They will vary from embodiment to embodiment as a function of both design choice and the process technology used.

The unselected memory cells during write logic-1 operations are shown in FIGS. 84 C through 84 H . The bias conditions for memory cells sharing the same row (e.g. memory cell 550 b ) are shown in FIGS. 84 C through 84 D , the bias conditions for memory cells sharing the same column as the selected memory cell 550 a (e.g. memory cell 550 c ) are shown in FIGS. 84 E through 84 F , and the bias conditions for memory cells 550 not sharing the same row nor the same column as the selected memory cell 550 a (e.g. memory cell 550 d ) are shown in FIGS. 84 G through 84 H .

As shown in FIGS. 84 C and 84 D , for representative memory cell 550 b sharing the same row as the selected memory cell 550 a , SL terminal 72 a and BL terminal 74 p are be grounded. Bipolar device 230 will be off and the memory cell 550 b will not be at the holding mode. However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As shown in FIGS. 84 E and 84 F , for representative memory cell 550 c sharing the same column as the selected memory cell 550 a , a greater positive voltage is applied to the BL terminal 74 a and a lesser positive voltage is applied to SL terminal 72 n . Less base current will flow into the floating body 24 than in selected memory cell 550 a because of the lower potential difference between SL terminal 72 and BL terminal 74 (i.e. the emitter and collector terminals of the n-p-n bipolar device 230 ). However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

As shown in FIGS. 84 G and 84 H , for representative memory cell 550 d sharing neither the same column nor the same row as the selected memory cell 550 a , the SL terminal 72 is positively charged and the BL terminal is grounded. Representative memory cell 550 d will be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 230 will generate hole current to replenish the charge in floating body 24 and where memory cells in state logic-0 will remain in neutral state.

The various voltage bias levels above are exemplary only. They will vary from embodiment to embodiment as a function of both design choice and the process technology used. Also, the first conductivity type may be changed from p-type to n-type and the second conductivity type may be changed from n-type to p-type, and the polarities of the applied biases may be reversed. Thus the invention is not to be limited in any way except by the appended claims.

A vertical stack of alternating conductive regions of first conductivity type and second conductivity type has been described in J_Kim discussed above, where a gate is overlaid surrounding the body region 24 on two sides. By removing the gates, a more compact memory cell than that reported in J_Kim can be obtained as in memory cell 350 discussed below.

FIGS. 85 A through 85 F illustrate another embodiment of a Gateless Half Transistor memory cell. By allowing the bit line region 16 to completely cover the floating body region 24 in memory cell 650 , some design rules like minimum-diffusion-to-insulator-spacing (the space from 16 to 26 in memory cell 550 ) no longer affects the cell size. Present in FIGS. 85 A through 85 F are substrate 12 of the first conductivity type, buried layer 22 of the second conductivity type, bit line region 16 of the second conductivity type, region of the second conductivity type 20 , region of the first conductivity type 21 , floating body 24 of the first conductivity type, buried layer region 22 , insulating regions 26 and 28 , source line terminal 72 , and substrate terminal 78 all of which perform substantially similar functions in memory cell 650 as in previously discussed embodiment memory cell 550 . The primary difference between memory cell 650 and memory cell 550 previously discussed is that bit line region 16 completely covers a (now smaller) floating body region 24 allowing for a more compact memory cell. As in other embodiments, there is no contact to the buried layer 22 at the semiconductor surface 14 inside the boundary of memory cell 650 .

The manufacturing of memory cell 650 is substantially similar to the manufacturing of memory cell 250 described in conjunction with FIGS. 36 A through 36 U and memory cell 550 described in conjunction with FIGS. 77 A through 77 F above, except that bit line region 16 may be formed by an implantation process formed on the material making up substrate 12 according to any of implantation processes known and typically used in the art. Alternatively, solid state diffusion or epitaxial growth process may also be used to form bit line region 16 .

FIG. 85 A illustrates a top view of memory cell 650 with several near neighbors.

FIG. 85 B illustrates a top view a single memory cell 650 with vertical cut line I-I′ and horizontal cut line II-II′ for the cross sections illustrated in FIGS. 85 C and 85 D respectively.

›DETAILED DESCRIPTION · 48 of 64

FIG. 85 E shows how memory cell 650 may have its buried layer 22 coupled to source line terminal 72 through region 20 of the second conductivity type and its substrate 12 coupled to substrate terminal 78 through region 21 of the first conductivity type.

FIG. 87 F shows exemplary memory array 680 comprising multiple memory cells 650 when arranged in an array to create a memory device. The circuit operation of memory cell 650 is substantially identical to that of memory cell 550 and will not be discussed further.

An alternate method of operating memory cells 250 , 350 , and 450 , which utilizes the silicon controlled rectifier (SCR) principle discussed above with reference to Widjaja, is now described.

As shown in FIG. 86 , inherent in memory cells 250 , 350 and 450 is a P1-N2-P3-N4 silicon controlled rectifier (SCR) device formed by two interconnected bipolar devices 32 and 34 , with substrate 78 functioning as the P1 region, buried layer 22 functioning as the N2 region, body region 24 functioning as the P3 region and bit line region 16 functioning as the N4 region. In this example, the substrate terminal 78 functions as the anode and terminal 74 functions as the cathode, while body region 24 functions as a p-base to turn on the SCR device. If body region 24 is positively charged, the silicon controlled rectifier (SCR) device formed by the substrate, buried well, floating body, and the BL junction will be turned on and if body region 24 is neutral, the SCR device will be turned off.

The holding operation can be performed by applying the following bias: zero voltage is applied to BL terminal 74 , zero or negative voltage is applied to WL terminal 70 , and a positive voltage is applied to the substrate terminal 78 , while leaving SL terminal 72 floating. Under these conditions, if memory cell 250 is in memory/data state logic-1 with positive voltage in floating body 24 , the SCR device of memory cell 250 is turned on, thereby maintaining the state logic-1 data. Memory cells in state logic-0 will remain in blocking mode, since the voltage in floating body 24 is not substantially positive and therefore floating body 24 does not turn on the SCR device. Accordingly, current does not flow through the SCR device and these cells maintain the state logic-0 data. Those memory cells 250 that are commonly connected to substrate terminal 78 and which have a positive voltage in body region 24 will be refreshed with a logic-1 data state, while those memory cells 250 that are commonly connected to the substrate terminal 78 and which do not have a positive voltage in body region 24 will remain in blocking mode, since their SCR device will not be turned on, and therefore memory state logic-0 will be maintained in those cells. In this way, all memory cells 250 commonly connected to the substrate terminal will be maintained/refreshed to accurately hold their data states. This process occurs automatically, upon application of voltage to the substrate terminal 78 , in a parallel, non-algorithmic, efficient process. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied to terminal 74 , a voltage of about −1.0 volts is applied to terminal 70 , and about +0.8 volts is applied to terminal 78 . However, these voltage levels may vary, while maintaining the relative relationships there between.

As illustrated in FIG. 87 , a read operation can be performed by applying a positive voltage to the substrate terminal 78 , a positive voltage (lower than the positive voltage applied to the substrate terminal 78 ) to BL terminal 74 , a positive voltage to WL terminal 70 , while leaving SL terminal 72 floating. If cell 250 a is in a state logic-1 having holes in the body region 24 , the silicon controlled rectifier (SCR) device formed by the substrate, buried well, floating body, and the BL junction will be turned on and a higher cell current (flowing from the substrate terminal 78 to the BL terminal 74 ) is observed compared to when cell 250 is in a state logic-0 having no holes in body region 24 . A positive voltage is applied to WL terminal 70 a to select a row in the memory cell array 80 (e.g., see FIG. 87 ), while negative voltage is applied to WL terminals 70 b (not shown) through 70 n for any unselected rows. The negative voltage applied reduces the potential of floating body 24 through capacitive coupling in the unselected rows and turns off the SCR device of each cell 250 in each unselected row. In one particular non-limiting embodiment, about +0.8 volts is applied to substrate terminals 78 a through 78 n , about +0.5 volts is applied to terminal 70 a (for the selected row), and about +0.4 volts is applied to selected bit line terminal 74 a , about −1.0 volts is applied to unselected word line terminals 70 b (not shown) through 70 n , and about +0.8 volts is applied to unselected bit line terminals 74 b through 74 . However, these voltage levels may vary.

For memory cells sharing the same row as the selected memory cell (e.g. cell 250 b ), both the BL and substrate terminals are positively biased and the SCR is off. Consequently these cells will not be at the holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

For memory cells sharing the same column as the selected memory cell (e.g. cell 250 c ), the substrate terminal 78 remains positively biased while the BL terminal 74 is positively biased (at lower positive bias than that applied to the substrate terminal 78 ). As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 while memory cells in state logic-0 will remain in neutral state.

›DETAILED DESCRIPTION · 49 of 64

For memory cells sharing neither the same row nor the same column as the selected memory cell (e.g. cell 250 d ), both the BL and substrate terminals are positively biased and the SCR is off. Consequently these cells will not be at the holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.

The silicon controlled rectifier device of selected memory cell 250 a can be put into a state logic-1 (i.e., performing a write logic-1 operation) as described with reference to FIG. 88 . The following bias is applied to the selected terminals: zero voltage is applied to BL terminal 74 , a positive voltage is applied to WL terminal 70 , and a positive voltage is applied to the substrate terminal 78 , while SL terminal 72 is left floating. The positive voltage applied to the WL terminal 70 will increase the potential of the floating body 24 through capacitive coupling and create a feedback process that turns the SCR device on. Once the SCR device of cell 250 is in conducting mode (i.e., has been “turned on”) the SCR becomes “latched on” and the voltage applied to WL terminal 70 can be removed without affecting the “on” state of the SCR device. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied to terminal 74 , a voltage of about +0.5 volts is applied to terminal 70 , and about +0.8 volts is applied to terminal 78 . However, these voltage levels may vary, while maintaining the relative relationships between the voltages applied, as described above, e.g., the voltage applied to terminal 78 remains greater than the voltage applied to terminal 74 .

For memory cells sharing the same row as the selected memory cell (e.g. cell 250 b ), the substrate terminal 78 is positively biased. However, because the BL terminal 74 is also positively biased, there is no potential difference between the substrate and BL terminals and the SCR is off. Consequently these cells will not be at the holding mode. However, because the write logic-1 operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

For memory cells sharing the same column as the selected memory cell (e.g. cell 250 c ), the substrate terminal 78 remains positively biased while the BL terminal 74 is now grounded. As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 while memory cells in state logic-0 will remain in neutral state.

For memory cells not sharing the same row nor the same column as the selected memory cell (e.g. cell 250 d ), both the BL and substrate terminals are positively biased and the SCR is off. Consequently these cells will not be at the holding mode. However, because the write logic-1 operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

A write logic-0 operation to selected memory cell 250 a is described with reference to FIG. 89 . The silicon controlled rectifier device is set into the blocking (off) mode by applying the following bias: zero voltage is applied to BL terminal 74 a , a positive voltage is applied to WL terminal 70 a , and zero voltage is applied to the substrate terminal 78 , while leaving SL terminal 72 a floating. Under these conditions the voltage difference between anode and cathode, defined by the voltages at substrate terminal 78 and BL terminal 74 , will become too small to maintain the SCR device in conducting mode. As a result, the SCR device of cell 250 a will be turned off. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied to terminal 74 , a voltage of about +0.5 volts is applied to terminal 70 , and about 0.0 volts is applied to terminal 78 . However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.

For memory cells sharing the same row as the selected memory cell (e.g. cell 250 b ), the substrate terminal 78 is grounded and the SCR will be off. Consequently these cells will not be at the holding mode. However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

For memory cells sharing the same column as the selected memory cell (e.g. cell 250 c ), the substrate terminal 78 is positively biased while the BL terminal 74 a is now grounded. As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 while memory cells in state logic-0 will remain in neutral state.

For memory cells sharing neither the same row nor the same column as the selected memory cell (e.g. cell 250 d ), both the BL terminal 74 p and substrate terminal 78 are positively biased and the SCR is off. Consequently these cells will not be at the holding mode. However, because the write logic-0 operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.

While one illustrative embodiment and method of use of the SCR operation of memory cell 250 has been described, other embodiments and methods are possible. For example, the first and second conductivity types may be reversed so that the first conductivity type is n-type and the second conductivity is p-type making the SCR a N1-P2-N3-P4 device and reversing the polarity of applied voltages. Voltages given in the various example operations are illustrative only and will vary from embodiment to embodiment as a matter of design choice. While substrate 12 is called a substrate for continuity of terminology and simplicity of presentation, substrate 12 may alternately be a well in either another well or a true substrate in a structure similar to that described in conjunction with FIG. 43 B above. By substrate 12 being a well instead of a true substrate, manipulating the voltage level of substrate 12 as required in some SCR operations is facilitated. Many other alternative embodiments and methods are possible, thus the illustrative examples given are not limiting in any way.

›DETAILED DESCRIPTION · 50 of 64

A novel semiconductor memory with an electrically floating body memory cell is achieved. The present invention also provides the capability of maintaining memory states employing parallel non-algorithmic periodic refresh operation. As a result, memory operations can be performed in an uninterrupted manner. Many embodiments of the present invention have been described. Persons of ordinary skill in the art will appreciate that these embodiments are exemplary only to illustrate the principles of the present invention. Many other embodiments will suggest themselves to such skilled persons after reading this specification in conjunction with the attached drawing figures.

Referring now to FIG. 91 , a memory cell 750 according to an embodiment of the present invention is shown. The cell 750 is fabricated on a silicon-on-insulator (SOI) substrate 12 having a first conductivity type (such as p-type conductivity), which consists of buried oxide (BOX) layer 22 .

A first region 16 having a second conductivity type, such as n-type, for example, is provided in substrate 12 and is exposed at surface 14 . A second region 18 having the second conductivity type is also provided in substrate 12 , and is also exposed at surface 14 . Additionally, second region 18 is spaced apart from the first region 16 as shown in FIG. 1 . First and second regions 16 and 18 may be formed by an implantation process formed on the material making up substrate 12 , according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process can be used to form first and second regions 16 and 18 .

A floating body region 24 having a first conductivity type, such as p-type conductivity type, is bounded by surface 14 , first and second regions 16 , 18 , buried oxide layer 22 , and substrate 12 . The floating body region 24 can be formed by an implantation process formed on the material making up substrate 12 , or can be grown epitaxially. A gate 60 is positioned in between the regions 16 and 18 , and above the surface 14 . The gate 60 is insulated from surface 14 by an insulating layer 62 . Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Cell 750 further includes word line (WL) terminal 70 electrically connected to gate 60 , source line (SL) terminal 72 electrically connected to region 16 , bit line (BL) terminal 74 electrically connected to region 18 , and substrate terminal 78 electrically connected to substrate 12 at a location beneath insulator 22 . A memory array 780 having a plurality of memory cells 750 is schematically illustrated in FIG. 92 A .

The operation of a memory cell has been described (and also describes the operation of memory cell 750 ) for example in “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002, which is hereby incorporated herein, in its entirety, by reference thereto. The memory cell states are represented by the charge in the floating body 24 . If cell 750 has holes stored in the floating body region 24 , then the memory cell 750 will have a lower threshold voltage (gate voltage where transistor is turned on) compared to when cell 750 does not store holes in floating body region 24 .

The charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 750 . If cell 750 is in a state “1” having holes in the floating body region 24 , then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current (e.g. current flowing from BL to SL terminals), compared to if cell 750 is in a state “0” having no holes in floating body region 24 . A sensing circuit/read circuitry 90 typically connected to BL terminal 74 of memory array 780 (e.g., see read circuitry 90 in FIG. 92 B ) can then be used to determine the data state of the memory cell. Examples of such read operations are described in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003 and U.S. Pat. No. 7,301,803 “Bipolar reading technique for a memory cell having an electrically floating body transistor”, both of which are hereby incorporated herein, in their entireties, by reference thereto. An example of a sensing circuit is described in Oshawa et al., “An 18.5 ns 128 Mb SOI DRAM with a Floating body Cell”, pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005, which is hereby incorporated herein, in its entirety, by reference thereto.

A read operation can be performed by applying the following bias conditions: a positive voltage is applied to the selected BL terminal 74 , and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70 , zero voltage is applied to the selected SL terminal 72 , and zero voltage is applied to the substrate terminal 78 . The unselected BL terminals will remain at zero voltage, the unselected WL terminals will remain at zero or negative voltage, and the unselected SL terminals will remain at zero voltage.

In one particular non-limiting embodiment, about 0.0 volts is applied to the selected SL terminal 72 , about +0.4 volts is applied to the selected terminal 74 , about +1.2 volts is applied to the selected terminal 70 , and about 0.0 volts is applied to substrate terminal 78 . The unselected terminals 74 remain at 0.0 volts, the unselected terminals 70 remain at 0.0 volts, at the unselected SL terminals 72 remain at 0.0 volts. FIG. 93 shows the bias conditions for the selected memory cell 750 a and unselected memory cells 750 b , 750 c , and 750 d in memory array 780 . FIG. 94 A also shows and example of bias conditions of the selected memory cell 750 a . However, these voltage levels may vary.

›DETAILED DESCRIPTION · 51 of 64

The bias conditions on unselected memory cells during the exemplary read operation described above with regard to FIG. 93 are shown in FIGS. 94 B- 94 D . The bias conditions for memory cells sharing the same row (e.g. memory cell 750 b ) and those sharing the same column (e.g. memory cell 750 c ) as the selected memory cell 750 a are shown in FIG. 94 B and FIGS. 94 C , respectively, while the bias condition for memory cells not sharing the same row nor the same column as the selected memory cell 750 (e.g. memory cell 750 d ) is shown in FIG. 94 D .

For memory cells sharing the same row as the selected memory cell (e.g. memory cell 750 b ), the WL terminal 70 is positively biased, but because the BL terminal 74 is grounded, there is no potential difference between the BL and SL terminals and consequently these cells are turned off (see FIG. 94 B ).

For memory cells sharing the same column as the selected memory cell (e.g. memory cell 750 c ), a positive voltage is applied to the BL terminal 74 . However, since zero or negative voltage is applied to the unselected WL terminal 70 , these memory cells are also turned off (see FIG. 94 C ).

For memory cells 750 not sharing the same row nor the same column as the selected memory cell (e.g. memory cell 750 d ), both WL and BL terminals are grounded. As a result, these memory cells are turned off (see FIG. 94 D ).

An exemplary write “0” operation of the cell 750 is now described with reference to FIG. 95 . A negative bias is applied to SL terminal 72 , zero or negative potential is applied to WL terminal 70 , zero voltage is applied to BL terminal 74 and zero voltage is applied to substrate terminal 78 . The unselected SL terminal 72 remains grounded. Under these conditions, the p-n junction between floating body 24 and region 16 of the selected cell 750 is forward-biased, evacuating any holes from the floating body 24 . In one particular non-limiting embodiment, about −1.2 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 70 , and about 0.0 volts is applied to terminal 74 and 78 . However, these voltage levels may vary, while maintaining the relative relationship between the applied bias, as described above.

An example of bias conditions of the selected and unselected memory cells 750 during a write “0” operation is illustrated in FIGS. 96 A- 96 B . Because a write “0” operation only involves a negative voltage applied to the selected SL terminal 72 , the bias conditions for all the unselected cells are the same. As can be seen, the unselected memory cells will be in a holding operation, with the BL terminal at about 0.0 volts, WL terminal at zero or negative voltage, and the unselected SL terminal at about 0.0 volts.

Alternatively, a write “0” operation can be performed by applying a negative bias to the BL terminal 74 as opposed to the SL terminal 72 . The SL terminal 72 will be grounded, while zero voltage is applied to the substrate terminal 78 , and zero or negative voltage is applied to the WL terminal 70 . Under these conditions, all memory cells sharing the same BL terminal 74 will be written into state “0” as shown in FIG. 97 .

The write “0” operation referred to above with regard to FIGS. 95 - 97 has a drawback in that all memory cells 750 sharing either the same SL terminal 72 or the same BL terminal 74 will be written to simultaneously and as a result, does not allow individual bit writing, i.e. writing to a single cell 750 memory bit. To write multiple data to different memory cells 750 , write “0” is first performed on all the memory cells, followed by write “1” operations on a selected bit or selected bits.

An alternative write “0” operation that allows for individual bit writing can be performed by applying a positive voltage to WL terminal 70 , a negative voltage to BL terminal 74 , zero or positive voltage to SL terminal 72 , and zero voltage to substrate terminal 78 . Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70 . As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74 , the p-n junction between 24 and region 18 is forward-biased, evacuating any holes from the floating body 24 . To reduce undesired write “0” disturb to other memory cells 750 in the memory array 780 , the applied potential can be optimized as follows: if the floating body 24 potential of state “1” is referred to V FB1 , then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V FB1 /2 while −V FB1 /2 is applied to BL terminal 74 .

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 750 a : a potential of about 0.0 volts to SL terminal 72 , a potential of about −0.2 volts to BL terminal 74 , a potential of about +0.5 volts is applied to terminal 70 , and about 0.0 volts is applied to substrate terminal 78 ; while about 0.0 volts is applied to unselected SL terminal 72 , about 0.0 volts is applied to unselected BL terminal 74 , about 0.0 volts is applied to unselected WL terminal 70 , and about 0.0 volts is applied to unselected terminal 78 . FIG. 98 shows the bias conditions in the above-described example, for the selected and unselected memory cells in memory array 780 . However, these voltage levels may vary.

The bias conditions of the selected memory cell 750 a under the write “0” operation described with regard to FIG. 98 are further elaborated and shown in FIG. 99 A . As described, the potential difference between floating body 24 and region 18 (connected to BL terminal 74 ) is shown in FIG. 99 A as having increased, resulting in a forward bias current which evacuates holes from the floating body 24 .

Examples of bias conditions on the unselected memory cells 750 during write “0” operations described with regard to FIG. 8 are shown in FIGS. 99 B- 99 D . The bias conditions for memory cells sharing the same row (e.g. memory cell 750 b ) are illustrated in FIG. 99 B , and the bias conditions for memory cells sharing the same column (e.g. memory cell 750 c ) as the selected memory cell 750 a are shown in FIG. 99 C , while the bias conditions for memory cells not sharing the same row nor the same column (e.g. memory cell 750 d ) as the selected memory cell 750 a are shown in FIG. 99 D .

›DETAILED DESCRIPTION · 52 of 64

The floating body 24 potential of memory cells sharing the same row as the selected memory cell (see FIG. 99 B ) will increase by ΔV FB due to capacitive coupling from WL terminal 70 . For memory cells in state “0”, the increase in the floating body 24 potential is not sustainable as the forward bias current of the p-n diodes formed by floating body 24 and junctions 16 and 18 will evacuate holes from floating body 24 . As a result, the floating body 24 potential will return to the initial state “0” equilibrium potential. For memory cells in state “1”, the floating body 24 potential will initially also increase by ΔV FB , which will result in holes being evacuated from floating body 24 . After the positive bias on the WL terminal 70 is removed, the floating body 24 potential will decrease by ΔV FB . If the initial floating body 24 potential of state “1” is referred to as V FB1 , the floating body 24 potential after the write “0” operation will become V FB1 −ΔV FB . Therefore, the WL potential needs to be optimized such that the decrease in floating body potential of memory cells 750 in state “1” is not too large. For example, the maximum floating body potential due to the coupling from the WL potential cannot exceed V FB1 /2.

For memory cells sharing the same column as the selected memory cell, a negative voltage is applied to the BL terminal 74 (see FIG. 99 C ), resulting in an increase in the potential difference between floating body 24 and region 18 connected to the BL terminal 74 . As a result, the p-n diode formed between floating body 24 and junction 18 will be forward biased. For memory cells in state “0”, the increase in the floating body 24 potential will not change the initial state “0” as there is initially no hole stored in the floating body 24 . For memory cells in state “1”, the net effect is that the floating body 24 potential after write “0” operation will be reduced. Therefore, the BL potential also needs to be optimized such that the decrease in floating body potential of memory cells 750 in state “1” is not too large. For example, a potential of −V FB1 /2 can be applied to the BL terminal 74 .

As to memory cells not sharing the same row nor the same column as the selected memory cell, zero voltage is applied to the SL terminal 72 , zero voltage is applied to the BL terminal 74 , and zero or negative voltage is applied to WL terminal 70 , and zero voltage is applied to substrate terminal 78 (see FIG. 99 D ). As a result, holes will not be evacuated from floating body region 24 .

A write “1” operation can be performed on memory cell 750 through impact ionization as described, for example, in “A New 1T DRAM Cell with Enhanced Floating Body Effect”, Lin and Chang, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, which was incorporated by reference above, or band-to-band tunneling mechanism, as described for example in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.

An example of the bias conditions of the selected memory cell 750 under a write “1” operation using band-to-band tunneling is illustrated in FIGS. 100 and 101 A . The negative bias applied to the WL terminal 70 and the positive bias applied to the BL terminal 74 results in electron tunneling which results in electron flow to the BL terminal 74 , generating holes which subsequently are injected to the floating body 24 of the selected memory cell 750 . The SL terminal 72 and the substrate terminal 78 are grounded during the write “1” operation.

Examples of bias conditions of the unselected memory cells during write “1” operations of the type described above with regard to FIG. 100 are shown in FIGS. 101 B- 101 D . The bias conditions for memory cells sharing the same row (e.g. memory cell 750 b ) are shown in FIG. 101 B and the bias conditions for memory cells sharing the same column as the selected memory cell 750 a (e.g. memory cell 750 c ) are shown in FIG. 101 C . The bias conditions for memory cells 750 not sharing the same row nor the same column as the selected memory cell 750 a (e.g. memory cell 750 d ) are shown in FIG. 101 D .

For memory cells sharing the same row as the selected memory cell, both terminals 72 and 74 are grounded, while about −1.2 volts is applied to WL terminal 70 (see FIG. 101 B ). There is no hole injection into the floating body 24 of memory cell 750 b as there is not enough potential difference for band-to-band tunneling to occur.

For memory cells sharing the same column as the selected memory cell, a positive voltage is applied to the BL terminal 74 (see FIG. 101 C ). No hole injection will occur for these memory cells as the WL terminal 70 is being grounded.

For memory cells 750 not sharing the same row or the same column as the selected memory cell, both the SL terminal 72 and the BL terminal 74 remain grounded (see FIG. 101 D ). Consequently, no write operations will occur to these memory cells.

An example of the bias conditions of the selected memory cell 750 under a write “1” operation using an impact ionization write “1” operation is illustrated in FIGS. 102 and 103 A- 103 D . A positive bias is applied to the selected WL terminal 70 , zero voltage is applied to all SL terminals 72 , a positive bias applied to the selected BL terminal 74 , while the substrate terminal 78 of the selected cell is grounded. These condition cause hole injection to the floating body 24 of the selected memory cell (e.g. cell 750 a in FIG. 103 A ).

›DETAILED DESCRIPTION · 53 of 64

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 750 a : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about +1.2 volts is applied to BL terminal 74 , a potential of about +1.2 volts is applied to the selected WL terminal 70 , and about 0.0 volts is applied to substrate terminal 78 ; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to unselected SL terminal 72 , about 0.0 volts is applied to unselected BL terminal 74 , a potential of about 0.0 volts is applied to unselected WL terminal 70 , and about 0.0 volts is applied to unselected substrate terminal 78 . FIG. 103 A shows the bias conditions for the selected memory cell in the example described above. FIG. 103 B shows the bias conditions for memory cells sharing the same row as the selected memory cell in the example described above with regard to FIG. 102 . FIG. 103 C shows the bias conditions for memory cells sharing the same column as the selected memory cell in the example described above with regard to FIG. 102 . FIG. 103 D shows the bias conditions for memory cells that share neither the same row nor the same column as the selected memory cell in the example described above with regard to FIG. 102 . However, these voltage levels may vary.

If floating body region 24 stores a positive charge, the positive charge stored will decrease over time due to the diode leakage current of the p-n junctions formed between the floating body 24 and regions 16 and 18 , respectively, and due to charge recombination. A positive bias can be applied to region 16 (connected to SL terminal 72 ) and/or to region 18 (connected to BL terminal 74 ), while zero or negative voltage is applied to WL terminal 70 and substrate terminal 78 .

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 750 : a potential of about +1.2 volts is applied to SL terminal 72 , a potential of about +1.2 volts is applied to BL terminal 74 , a potential of 0.0 volts is applied to WL terminal 70 , and 0.0 volts is applied to substrate terminal 78 . Under these conditions, the p-n junctions formed between the floating body 24 and regions 16 and 18 are reverse biased, improving the lifetime of the positive charge stored in the floating body region 24 .

The connection between region 16 of the memory cell 750 and the SL terminal 72 and the connection between region 18 of the memory cell 750 and the BL terminal 74 are usually made through conductive contacts, which for example could be made of polysilicon or tungsten. FIG. 104 shows contact 71 connecting region 16 and the SL terminal 72 and contact 73 connecting region 18 and the BL terminal 74 . Many difficulties arise with contact formation. For example, separation between the contact and other electrodes (e.g. the gate electrode or neighboring contacts) must be provided to avoid electrical shorts between neighboring conductive regions. Difficulties related to contact formation and some potential solutions are described for example in U.S. Patent Application Publication No. 2010/0109064, titled “Semiconductor Device and Manufacturing Method Thereof”, which is hereby incorporated herein, in its entirety, by reference thereto.

To simplify the manufacturing of the memory cell 750 and to reduce the size of the memory 750 , adjacent memory cells can be designed to share a common region 16 (and SL terminal 72 ) or a common region 18 (and BL terminal 74 ). For example, as shown in FIG. 105 , U.S. Pat. No. 6,937,516, “Semiconductor Device” to Fazan and Okhonin, which is hereby incorporated herein, in its entirety, by reference thereto, shows an arrangement where adjacent memory cells share common contacts 50 and 52 . This reduces the number of contacts from two contacts per memory cell (when adjacent contacts are not shared between adjacent memory cells) to where the number of contacts of memory cells in connection equals the number of memory cells plus one. For example, in FIG. 105 , the number of interconnected memory cells (the cross section shows memory cells interconnected in the same column) is four and the number of contacts is five.

The present invention provides a semiconductor memory device having a plurality of floating body memory cells which are connected either in series to from a string, or in parallel to form a link. The connections between the memory cells are made to reduce the number of contacts for each memory cell. In some embodiments, connections between control lines, such as source line or bit line, to the memory cells are made at the end or ends of a string or link of several memory cells, such that memory cells not at the end are “contactless” memory cells, because no contacts are provided on these cells to connect them to control lines. Rather, they are in direct contact with other memory cells that they are immediately adjacent to. Because several memory cells are connected either in series or in parallel, a compact memory cell can be achieved.

FIG. 106 A shows a cross-sectional schematic illustration of a memory string 500 that includes a plurality of memory cells 750 ( 750 a - 750 n in FIG. 106 A , although there may be more or fewer cells 750 ), while FIG. 106 B shows a top view of the memory cell array 780 , which shows two strings 500 of memory cells 750 between the SL terminal 72 and BL terminal 74 . Each memory string 500 includes a plurality of memory cells 750 connected in a NAND architecture, in which the plurality of memory cells 750 are serially connected to make one string of memory cells. In a series connection, the same current flows through each of the memory cells 750 , from the BL terminal 74 to the SL terminal 72 , or vice versa. String 500 includes “n” memory cells 750 , where “n” is a positive integer, which typically ranges between eight and sixty-four (although this number could be lower than eight (as low as two) or higher than sixty-four), and in at least one example, is sixteen. The region 18 of a second conductivity at one end of the memory string is connected to the BL terminal 74 , while the source region 16 of a second conductivity at the other end of the memory string is connected to the SL terminal 72 . Although FIG. 106 B schematically illustrates an array of two strings, it should be noted that the present invention is not limited to two strings.

›DETAILED DESCRIPTION · 54 of 64

Each memory cell transistor 750 includes a floating body region 24 of a first conducting type, and first and second regions 20 (corresponding to first and second regions 16 and 18 in the single cell embodiments of cell 750 described above) of a second conductivity type, which are spaced apart from each other and define a channel region. A buried insulator layer 22 isolates the floating body region 24 from the bulk substrate 12 . A gate 60 is positioned above the surface of floating body 24 and is in between the first and second regions 20 . An insulating layer 62 is provided between gate 60 and floating body 24 to insulate gate 60 from floating body 24 . As can be seen in FIGS. 106 A- 106 B , connections to the control lines SL terminal 72 and BL terminal 74 are only made at the ends of the string 500 . Connection between SL terminal 72 and region 16 is made through contact 71 and connection between BL terminal 74 and region 18 is made through contact 73 . No contacts are made to the regions 20 of the memory cells 750 in memory string 500 , resulting in contactless memory cells intermediate of the end memory cells. In some embodiments, the transistors at the end of the string 500 (e.g., cells 750 a and 750 n in FIG. 106 A ) may be configured as access transistors to the memory string 500 , wherein the charges stored in the associated floating bodies 24 (in the FIG. 106 A example, 24 a and 24 n ) are not read.

FIG. 107 shows an equivalent circuit representation of the memory array 780 of FIG. 106 B . In FIG. 107 , the memory cells are arranged in a grid, with the rows of the memory array being defined by the WL terminals 70 , while the columns are defined by the BL terminals 74 . Within each column, multiple memory cells 750 are serially connected forming the string 500 . Adjacent columns are separated by columns of isolation 26 (see FIG. 106 B ), such as shallow trench isolation (STI).

A read operation is described with reference to FIGS. 108 and 109 A- 109 B . The read operation can be performed by applying the following bias conditions, where memory cell 750 c is being selected in this example: a positive voltage is applied to the selected BL terminal 74 , and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70 , zero voltage is applied to the selected SL terminal 72 , and zero voltage is applied to the substrate terminal 78 . The unselected BL terminals 74 will remain at zero voltage and the unselected SL terminals 72 will remain at zero voltage. A positive voltage greater than the positive voltage applied to the selected WL terminal 70 c is applied to passing WL terminals 70 a , 70 b , 70 l , 70 m , and 70 n (see FIGS. 108 and 109 A- 109 B ). Passing WL terminals are connected to the gates of the passing cells, i.e. the unselected cells which are serially connected to the selected memory cell 750 c (e.g. memory cells 750 a , 750 b , 750 l , 750 m , and 750 n in FIG. 108 ). The voltages applied to the gate of the passing cells are such that the passing transistors are turned on, irrespective of the potentials of their floating body regions. The passing cells need to be turned on because in a series connection, the current flows from the BL terminal 74 to SL terminal 72 (or vice versa) thereby flowing through each of the memory cells 750 . As a result, the passing cells will pass the potentials applied to the SL terminal 72 and BL terminal 74 to the source and drain regions 20 b and 20 c of the selected cell 750 c . For example, the memory cell 750 n will pass the voltage applied to the BL terminal 74 to region 20 m connected to cell 750 n (and 750 m ), which memory cell 750 m will subsequently pass to the region 201 connected to cell 750 l . The adjacent passing memory cells will subsequently pass the voltage applied to BL terminal 74 until the voltage reaches region 20 c of the selected cell 750 c.

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 750 c : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about +0.4 volts is applied to BL terminal 74 , a potential of about +1.2 volts is applied to selected WL terminal 70 , about +3.0 volts is applied to passing WL terminals 70 , and about 0.0 volts is applied to substrate terminal 78 ; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to SL terminal 72 (i.e., unselected SL terminal 72 not shown in FIG. 109 A ), about 0.0 volts is applied to BL terminal 74 , a potential of about 0.0 volts is applied to WL terminal 70 that are not passing WL terminals (not shown in FIG. 109 A ), and about 0.0 volts is applied to substrate terminal 78 . FIGS. 108 and 109 A- 109 B show bias condition for the selected and unselected memory cells in memory array 780 . However, these voltage levels may vary.

Under these conditions, about +1.2 volts will be applied to the gate 60 of the selected cell 750 c and about 0.0 volts and 0.4 volts will be passed to the regions 20 b and 20 c of the selected cells 750 c , similar to the read condition described in FIG. 94 A . As described, the passing cells are biased so that its channels are conducting, and therefore the current flowing from the BL terminal 74 and SL terminal 72 of the string 500 is then determined by the potential of the floating body region 24 of the selected cell 750 c . If cell 750 c is in a state “1” having holes in the floating body region 24 , then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently be conducting a larger current compared to if cell 750 c is in a state “0” having no holes in floating body region 24 .

A sensing circuit/read circuitry 90 typically connected to BL terminal 74 of memory array 780 (e.g., see read circuitry 90 in FIG. 109 B ) can be used to determine the data state of the memory cell. An example of a sensing circuit is described in Ohsawa et al., “An 18.5 ns 128 Mb SOI DRAM with a Floating body Cell”, pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005, which is hereby incorporated herein, in its entirety, by reference thereto.

›DETAILED DESCRIPTION · 55 of 64

A write “0” operation is described with reference to FIGS. 110 - 111 . Bias conditions shown include: zero voltage applied to the SL terminal 72 , zero voltage applied to the WL terminals 70 , and negative voltage applied to the BL terminal 74 , while the substrate terminal 78 is grounded. Under these conditions, the p-n junctions between floating bodies 24 and regions 20 of the respective memory cells in string 500 are forward-biased, evacuating any holes from each floating body 24 . In one particular non-limiting embodiment, about −1.2 volts is applied to terminal 74 , about 0.0 volts is applied to terminal 70 , about 0.0 volts is applied to terminal 72 and about 0.0 volts is applied to terminal 78 . Alternatively, a positive voltage can be applied to the WL terminals 70 to ensure that the negative voltage applied to the BL terminal 74 is passed to all the memory cells in string 500 . However, these voltage levels may vary, while maintaining the relative relationship between the charges applied, as described above.

An alternative write “0” operation that allows for individual bit writing is shown in FIGS. 112 A- 112 B . This write “0” operation can be performed by applying a negative voltage to BL terminal 74 , zero voltage to SL terminal 72 , zero voltage to substrate terminal 78 , and a positive voltage to passing WL terminals. The selected WL terminal is initially grounded until the voltages applied to SL terminal 72 and BL terminal 74 reach the regions 20 b and 20 c , respectively, of the selected memory cell 750 c . Subsequently, the potential of the selected WL terminal 70 ( 70 c in this example) is raised to a positive voltage higher than the positive voltage applied to passing WL terminals. Under these conditions, a positive voltage will be applied to the gate of the selected memory cell (e.g. memory cell 750 c in FIGS. 112 A- 112 B ) and consequently the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70 . The passing cells (e.g. memory cell 750 l , 750 m , and 750 n ) will pass the negative voltage applied to the BL terminal 74 to the region 20 c of the memory cell 750 c , while passing cells 750 a and 750 b will pass zero voltage applied to the SL terminal 72 to the region 20 b of the memory cell 750 c . Under these conditions, the bias conditions of the selected memory cell 750 c will be similar to the conditions described in FIG. 99 A . As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74 , the p-n junction between 24 c and region 20 c is forward-biased, evacuating any holes from the floating body 24 . To reduce undesired write “0” disturb to other memory cells 750 in the memory array 780 , the applied potential can be optimized as follows: if the floating body 24 potential of state “1” is referred to V FB1 , then the voltage applied to the selected WL terminal 70 is configured to increase the floating body 24 potential by V FB1 /2 while −V FB1 /2 is applied to BL terminal 74 . The voltage applied to WL terminal of the passing cells is optimized such that it is high enough to pass the negative voltage applied to the BL terminal 74 , but cannot be too high to prevent the potential of the floating body 24 of the passing cells becoming too high, which will result in holes being evacuated from the passing cells that are in state “1”. A higher positive voltage can be applied to passing WL terminals passing zero voltage applied to the SL terminal 72 (e.g. passing WL terminals to the left of selected WL terminal 70 c , i.e. 70 a and 70 b in FIG. 112 A ) than the voltage applied to passing WL terminals passing negative voltage applied to the BL terminal 74 (e.g. passing WL terminals to the right of selected WL terminal 70 c ). This is because the higher voltage applied to terminal 72 (compared to the negative voltage applied to terminal 74 ) may require a higher passing gate voltage for the passing transistors to be turned on.

In one particular non-limiting embodiment, the following bias conditions are applied to the memory string 500 : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about −0.2 volts is applied to BL terminal 74 , a potential of about +0.5 volts is applied to selected terminal 70 , a potential of about +0.2 volts is applied to passing WL terminals 70 and about 0.0 volts is applied to substrate terminal 78 ; while about 0.0 volts is applied to unselected SL terminal 72 , about 0.0 volts is applied to unselected BL terminal 74 , about 0.0 volts is applied to unselected (but not passing) WL terminal 70 , and about 0.0 volts is applied to unselected terminal 78 . FIG. 112 A shows the bias conditions for the selected and passing memory cells in selected memory string 500 , while FIG. 112 B shows the bias conditions for selected and unselected memory cells in memory array 780 where memory cell 750 c is the selected cell. However, these voltage levels may vary.

Under these bias conditions, a positive voltage will be applied to the gate 60 of the selected cell 750 c , while a negative voltage applied to the BL terminal 74 will be passed to the region 20 c of the selected cell 750 c , and zero voltage applied to the SL terminal 72 will be passed to the region 20 b of the selected cell 750 c . This condition is similar to the condition described in FIG. 99 A , which will result in hole evacuation out of the floating body 24 of the cell 750 c.

A write “1” operation can be performed on memory cell 750 through impact ionization as described for example in Lin et al., “A New 1T DRAM Cell with Enhanced Floating Body Effect”, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, which was incorporated by reference above, or by a band-to-band tunneling mechanism, as described for example in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.

›DETAILED DESCRIPTION · 56 of 64

An example of bias conditions of a selected memory cell 750 during a band-to-band tunneling write “1” operation is illustrated in FIGS. 113 A and 113 B. A negative bias is applied to the selected WL terminal 70 , a positive voltage is applied to the passing WL terminals 70 , zero voltage is applied to the SL terminal 72 (and to all SL terminals 72 ), and a positive bias is applied to the selected BL terminal 74 (zero voltage is applied to unselected BL terminals 74 ), while the substrate terminal 78 is grounded. These conditions cause hole injection to the floating body 24 of the selected memory cell (e.g. cell 750 c in FIGS. 113 A- 113 B ).

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory string 500 : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about +1.2 volts is applied to BL terminal 74 , a potential of about −1.2 volts is applied to the selected WL terminal 70 , about +3.0 volts is applied to the passing WL terminals 70 , and about 0.0 volts is applied to substrate terminal 78 ; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to SL terminal 72 , about 0.0 volts is applied to BL terminal 74 , a potential of about 0.0 volts is applied to unselected (but not passing) WL terminal 70 (not shown in FIG. 113 B ), and about 0.0 volts is applied to substrate terminal 78 . FIG. 113 A shows the bias conditions for the selected and passing memory cells in selected memory string 500 , while FIG. 113 B shows the bias conditions for the selected and unselected memory cells in memory array 780 , where memory cell 750 c is the selected cell. However, these voltage levels may vary.

Under these bias conditions, a negative voltage will be applied to the gate 60 of the selected cell 750 c , while a positive voltage applied to the BL terminal 74 will be passed to the region 20 c of the selected cell 750 c , and zero voltage applied to the SL terminal 72 will be passed to the region 20 b of the selected cell 750 c . This condition is similar to the condition described in FIG. 101 A , which will result in hole injection to the floating body 24 of the cell 750 c.

An example of the bias conditions of the selected memory cell 750 under an impact ionization write “1” operation is illustrated in FIGS. 114 A- 114 B . A positive bias is applied to the selected WL terminal 70 , a positive voltage more positive than the positive voltage applied to the selected WL terminal 70 is applied to the passing WL terminals 70 , zero voltage is applied to the SL terminal 72 (both the selected SL terminal 72 as well as all other SL terminals 72 ), and a positive bias is applied to the selected BL terminal 74 (zero voltage is applied to the unselected BL terminals 74 ), while the substrate terminal 78 is grounded. These conditions cause hole injection to the floating body 24 of the selected memory cell (e.g. cell 750 c in FIGS. 114 A- 114 B ).

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory string 500 : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about +1.2 volts is applied to BL terminal 74 , a potential of about +1.2 volts is applied to the selected WL terminal 70 , about +3.0 volts is applied to the passing WL terminals 70 , and about 0.0 volts is applied to substrate terminal 78 ; while the following bias conditions are applied to the unselected terminals (i.e., terminals in strings other than the string that the selected cell is in): about 0.0 volts is applied to SL terminal 72 , about 0.0 volts is applied to BL terminal 74 , a potential of about 0.0 volts is applied to WL terminal 70 (not shown in FIG. 114 B ), and about 0.0 volts is applied to substrate terminal 78 . FIG. 114 A shows the bias conditions for the selected and passing memory cells in selected memory string 500 , while FIG. 114 B shows bias conditions for selected and unselected memory cells in memory array 780 (with memory cell 750 c as the selected cell). However, these voltage levels may vary.

A multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to the memory cell 750 , followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to the memory cell 750 , followed by another read verification operation. This loop is repeated until the desired memory state is achieved.

For example, using band-to-band hot hole injection, a positive voltage is applied to BL terminal 74 , zero voltage is applied to SL terminal 72 , a negative voltage is applied to the selected WL terminal 70 , a positive voltage is applied to the passing WL terminals, and zero voltage is applied to the substrate terminal 78 . Positive voltages of different amplitudes are applied to BL terminal 74 to write different states to floating body 24 . This results in different floating body potentials 24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied to BL terminal 74 . In one particular non-limiting embodiment, the write operation is performed by applying the following bias conditions: a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about −1.2 volts is applied to the selected WL terminal 70 , about +3.0 volts is applied to the passing WL terminals, and about 0.0 volts is applied to substrate terminal 78 , while the potential applied to BL terminal 74 is incrementally raised. For example, in one non-limiting embodiment, 25 millivolts is initially applied to BL terminal 74 , followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e. cell current corresponding to whichever state of states 00, 01, 10 or 11 is desired is achieved), then the multi write operation is concluded. If the desired state is not achieved, then the voltage applied to BL terminal 74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary. The write operation is followed by a read operation to verify the memory state.

›DETAILED DESCRIPTION · 57 of 64

The string 500 may be provided as planar cells, such as the embodiments described above with reference to FIGS. 91 and 106 A , or may be provided as fin-type, three-dimensional cells, such as those illustrated in FIGS. 115 A- 115 B , for example. Other variations, modifications and alternative cells 750 may be provided without departing from the scope of the present invention and its functionality.

Referring now to FIG. 23 above, a memory cell 150 according to an embodiment of the present invention is shown. The cell 150 is fabricated on a bulk substrate 12 having a first conductivity type (such as p-type conductivity). A buried layer 22 of a second conductivity type (such as n-type conductivity) is also provided in the substrate 12 and buried in the substrate 12 , as shown. Buried layer 22 may be formed by an ion implantation process on the material of substrate 12 . Alternatively, buried layer 22 can be grown epitaxially.

A first region 16 having the second conductivity type is provided in substrate 12 and first region 16 is exposed at surface 14 . A second region 18 having the second conductivity type is also provided in substrate 12 , is also exposed at surface 14 and is spaced apart from the first region 16 . First and second regions 16 and 18 may be formed by an implantation process formed on the material making up substrate 12 , according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process can be used to form first and second regions 16 and 18 .

A floating body region 24 having a first conductivity type, such as p-type conductivity type, is bounded by surface 14 , first and second regions 16 , 18 , insulating layers 26 , and buried layer 22 . Insulating layers 26 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulating layers 26 insulate cell 150 from neighboring cells 150 when multiple cells 150 are joined in an array 180 . The floating body region 24 can be formed by an implantation process formed on the material making up substrate 12 , or can be grown epitaxially. A gate 60 is positioned in between the regions 16 and 18 , and above the surface 14 . The gate 60 is insulated from surface 14 by an insulating layer 62 . Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Cell 150 further includes word line (WL) terminal 70 electrically connected to gate 60 , source line (SL) terminal 72 electrically connected to region 16 , bit line (BL) terminal 74 electrically connected to region 18 , buried well (BW) terminal 76 connected to buried layer 22 , and substrate terminal 78 electrically connected to substrate 12 at a location beneath insulator 22 .

The operation of a memory cell 150 has been described for example in Ranica et al., “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-cost eDRAM Applications”, pp. 38-41, Tech. Digest, Symposium on VLSI Technology, 2005 and application Ser. No. 12/797,334, titled “Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor”, both of which are hereby incorporated herein, in their entireties, by reference thereto.

Memory cell states are represented by the charge in the floating body 24 . If cell 150 has holes stored in the floating body region 24 , then the memory cell 150 will have a lower threshold voltage (gate voltage where transistor is turned on) compared to when cell 150 does not store holes in floating body region 24 .

As shown in FIG. 25 above, inherent in this embodiment of the memory cell 150 are n-p-n bipolar devices 130 a , 130 b formed by buried well region 22 , floating body 24 , and SL and BL regions 16 , 18 . A holding operation can be performed by utilizing the properties of the n-p-n bipolar devices 130 a , 130 b through the application of a positive back bias to the BW terminal 76 while grounding terminal 72 and/or terminal 74 . If floating body 24 is positively charged (i.e. in a state “1”), the bipolar transistor 130 a formed by SL region 16 , floating body 24 , and buried well region 22 and bipolar transistor 130 b formed by BL region 18 , floating body 24 , and buried well region 22 will be turned on.

A fraction of the bipolar transistor current will then flow into floating region 24 (usually referred to as the base current) and maintain the state “1” data. The efficiency of the holding operation can be enhanced by designing the bipolar devices 130 a , 130 b formed by buried well layer 22 , floating region 24 , and regions 16 / 18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of BW terminal 76 to the base current flowing into the floating region 24 .

FIG. 116 A shows an energy band diagram of the intrinsic n-p-n bipolar device 130 when the floating body region 24 is positively charged and a positive bias voltage is applied to the buried well region 22 . The dashed lines indicate the Fermi levels in the various regions of the n-p-n transistor 130 . The Fermi levels are located in the band gap between the solid line 17 indicating the top of the valance band (the bottom of the band gap) and the solid line 19 indicating the bottom of the conduction band (the top of the band gap). The positive charge in the floating body region 24 lowers the energy barrier of electron flow into the floating body region 24 (i.e., the base region of the n-p-n bipolar device). Once injected into the floating body region 24 , the electrons will be swept into the buried well region 22 (connected to BW terminal 76 ) due to the positive bias applied to the buried well region 22 . As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into the BW terminal 76 while the resulting hot holes will subsequently flow into the floating body region 24 . This process restores the charge on floating body 24 to its maximum level and will maintain the charge stored in the floating body region 24 which will keep the n-p-n bipolar transistor 130 on for as long as a positive bias is applied to the buried well region 22 through BW terminal 76 .

›DETAILED DESCRIPTION · 58 of 64

If floating body 24 is neutrally charged (the voltage on floating body 24 being equal to the voltage on grounded bit line region 16 ), a state corresponding to state “0”, the bipolar device will not be turned on, and consequently no base hole current will flow into floating region 24 . Therefore, memory cells in the state “0” will remain in the state “0”.

FIG. 116 B shows an energy band diagram of the intrinsic n-p-n bipolar device 130 when the floating body region 24 is neutrally charged and a bias voltage is applied to the buried well region 22 . In this state the energy level of the band gap bounded by solid lines 17 A and 19 A is different in the various regions of n-p-n bipolar device 130 . Because the potential of the floating body region 24 and the bit line region 16 are equal, the Fermi levels are constant, resulting in an energy barrier between the bit line region 16 and the floating body region 24 . Solid line 23 indicates, for reference purposes, the energy barrier between the bit line region 16 and the floating body region 24 . The energy barrier prevents electron flow from the bit line region 16 (connected to BL terminal 74 ) to the floating body region 24 . Thus the n-p-n bipolar device 130 will remain off.

Although the embodiment discussed in FIGS. 25 , 116 A and 116 B refers to bipolar devices 130 as n-p-n transistors, persons of ordinary skill in the art will readily appreciate that by reversing the first and second connectivity types and inverting the relative values of the applied voltages memory cell 150 could include a bipolar device 130 which is a p-n-p transistor. Thus the choice of an n-p-n transistor as an illustrative example for simplicity of explanation in FIGS. 25 , 116 A and 116 B is not limiting in any way. In addition, the discussions in regard to FIGS. 25 , 116 A and 116 B use bipolar device 130 b formed by bit line region 18 , floating body region 24 , and buried well region 22 , and the same principles also apply to bipolar device 130 a formed by source line region 16 , floating body region 24 and buried well region 22 .

The charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 150 . If cell 150 is in a state “1” having holes in the floating body region 24 , then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current (e.g. current flowing from BL to SL terminals), compared to if cell 150 is in a state “0” having no holes in floating body region 24 . Examples of the read operation is described in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003; Ohsawa et al., “An 18.5 ns 128 Mb SOI DRAM with a Floating body Cell”, pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005; and U.S. Pat. No. 7,301,803 “Bipolar reading technique for a memory cell having an electrically floating body transistor”, which are hereby incorporated herein, in their entireties, by reference thereto.

A read operation can be performed on cell 150 by applying the following bias conditions: zero voltage is applied to the BW terminal 76 , zero voltage is applied to SL terminal 72 , a positive voltage is applied to the selected BL terminal 74 , and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70 , while zero voltage is applied to substrate terminal 78 . When cell 150 is in an array 180 of cells 150 (e.g., see FIG. 117 ), the unselected BL terminals 74 will remain at zero voltage and the unselected WL terminals 70 will remain at zero or negative voltage. In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72 , about +0.4 volts is applied to the selected terminal 74 a , about +1.2 volts is applied to the selected terminal 70 a , about 0.0 volts is applied to terminal 76 , and about 0.0 volts is applied to terminal 78 , as illustrated in FIG. 117 .

A write “0” operation of the cell 150 is now described with reference to FIG. 118 . In this example, to write “0” to cell 150 , a negative bias is applied to SL terminal 72 , zero voltage is applied to BL terminal 74 , zero or negative voltage is applied to WL terminal 70 , zero or positive voltage is applied to BW terminal 76 , and zero voltage is applied to substrate terminal 78 . The SL terminal 72 for the unselected cells 150 that are not commonly connected to the selected cell 150 a will remain grounded. Under these conditions, the p-n junctions (junction between 24 and 16 ) are forward-biased, evacuating any holes from the floating body 24 . In one particular non-limiting embodiment, about −1.2 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 74 , about 0.0 volts is applied to terminal 70 , about 0.0 volts is applied to terminal 76 , and about 0.0 volts is applied to terminal 78 . However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above. Under these conditions, all memory cells sharing the same SL terminal 72 will be written into state “0”.

A write “0” operation can also be performed by applying a negative bias to the BL terminal 74 as opposed to the SL terminal 72 . The SL terminal 72 will be grounded, while zero or positive voltage is applied to BW terminal 76 , zero voltage is applied to the substrate terminal 78 , and zero or negative voltage is applied to the WL terminal 70 . Under these conditions, all memory cells sharing the same BL terminal 74 will be written into state “0”.

The write “0” operations referred to above with regard to FIG. 118 have a drawback in that all memory cells 150 sharing either the same SL terminal 72 or the same BL terminal 74 will be written to simultaneously and as a result, these operations do not allow individual bit writing, i.e. writing to a single cell 150 memory bit. To write multiple data to different memory cells 150 , write “0” is first performed on all the memory cells, followed by write “1” operations on a selected bit or selected bits.

›DETAILED DESCRIPTION · 59 of 64

An alternative write “0” operation, which, unlike the previous write “0” operations described above with regard to FIG. 118 , allows for individual bit write, can be performed by applying a positive voltage to WL terminal 70 , a negative voltage to BL terminal 74 , zero or positive voltage to SL terminal 72 , zero or positive voltage to BW terminal 76 , and zero voltage to substrate terminal 78 , an example of which is illustrated in FIG. 119 . Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70 . As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74 , the p-n junction (junction between 24 and 18 ) is forward-biased, evacuating any holes from the floating body 24 . The applied bias to selected WL terminal 70 and selected BL terminal 74 can potentially affect the states of the unselected memory cells 150 sharing the same WL or BL terminal as the selected memory cell 150 . To reduce undesired write “0” disturb to other memory cells 150 in the memory array 180 , the applied potential can be optimized as follows: if the floating body 24 potential of state “1” is referred to as V FB1 , then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V FB1 /2 while −V FB1 /2 is applied to BL terminal 74 . This will minimize the floating body 24 potential change in the unselected cells 150 in state “1” sharing the same BL terminal as the selected cell 150 from V FB1 to V FB1 /2. For memory cells 150 in state “0” sharing the same WL terminal as the selected cell 150 , unless the increase in floating body 24 potential is sufficiently high (i.e., at least V FB /3, see below), then both n-p-n bipolar devices 130 a and 130 b will not be turned on, or so that the base hold current is low enough that it does not result in an increase of the floating body 24 potential over the time during which the write operation is carried out (write operation time). It has been determined according to the present invention that a floating body 24 potential increase of V FB /3 is low enough to suppress the floating body 24 potential increase. A positive voltage can be applied to SL terminal 72 to further reduce the undesired write “0” disturb on other memory cells 150 in the memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74 .

In one particular non-limiting embodiment, for the selected cell 150 a potential of about 0.0 volts is applied to terminal 72 , a potential of about −0.2 volts is applied to terminal 74 , a potential of about +0.5 volts is applied to terminal 70 , about 0.0 volts is applied to terminal 76 , and about 0.0 volts is applied to terminal 78 . For the unselected cells not sharing the same WL terminal or BL terminal with the selected memory cell 150 , about 0.0 volts is applied to terminal 72 , about 0.0 volts is applied to terminal 74 , about 0.0 volts is applied to terminal 70 , about 0.0 volts is applied to terminal 76 , and about 0.0 volts is applied to terminal 78 . FIG. 119 shows the aforementioned bias conditions for the selected memory cell 150 and other cells 150 in the array 180 . However, these voltage levels may vary.

A write “1” operation can be performed on memory cell 150 through impact ionization as described for example in Lin et al., “A New 1T DRAM Cell with Enhanced Floating Body Effect”, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, which was incorporated by reference above, or a band-to-band tunneling mechanism, as described for example in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.

An example of the bias conditions of the selected memory cell 150 under a band-to-band tunneling write “1” operation is illustrated in FIG. 120 A . The negative bias applied to the WL terminal 70 ( 70 a in FIG. 120 A ) and the positive bias applied to the BL terminal 74 ( 74 a in FIG. 120 A ) results in hole injection to the floating body 24 of the selected memory cell 150 ( 150 a in FIG. 120 A ). The SL terminal 72 ( 72 a in FIG. 120 A ) and the substrate terminal 78 ( 78 a in FIG. 120 A ) are grounded during the write “1” operation, while zero or positive voltage can be applied to BW terminal 76 ( 76 a in FIG. 120 A ) (positive voltage can be applied to maintain the resulting positive charge on the floating body 24 as discussed in the holding operation above). The unselected WL terminals 70 ( 70 n in FIG. 31 A ) and unselected BL terminals 74 ( 74 n in FIG. 120 A ) will remain grounded.

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 150 a : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about +1.2 volts is applied to BL terminal 74 , a potential of about −1.2 volts is applied to WL terminal 70 , about 0.0 volts is applied to BW terminal 76 , and about 0.0 volts is applied to substrate terminal 78 ; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to SL terminal 72 , about 0.0 volts is applied to BL terminal 74 , a potential of about 0.0 volts is applied to WL terminal 70 , about 0.0 volts is applied to BW terminal 76 (or +1.2 volts so that unselected cells are in the holding operation) and about 0.0 volts is applied to substrate terminal 78 . FIG. 120 A shows the bias condition for the selected memory cell 150 . However, these voltage levels may vary.

FIG. 120 B shows bias conditions of the selected ( 150 a ) and unselected ( 150 b , 150 c , 150 d ) memory cells 150 during an impact ionization write “1” operation. A positive voltage is applied to the selected WL terminal 70 (i.e., 70 a in FIG. 120 B ) and a positive voltage is applied to the selected BL terminal 74 (i.e., 74 a in FIG. 120 B ), with the SL terminal 72 (i.e., 72 a in FIG. 120 B ), the BW terminal 76 (i.e., 76 a in FIG. 120 B ), and the substrate terminal 78 (i.e., 78 a in FIG. 120 B ) are grounded. This condition results in a lateral electric field in the channel region sufficient to create hot electrons, which subsequently create electron and hole pairs, with the holes being subsequently injected to the floating body region 24 of the selected memory cell. The unselected WL terminals 70 and unselected BL terminals 74 are grounded, while the unselected BW terminal can be grounded or a positive voltage can be applied thereto to maintain the states of the unselected cells.

›DETAILED DESCRIPTION · 60 of 64

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 150 a : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about +1.2 volts is applied to BL terminal 74 , a potential of about +1.2 volts is applied to WL terminal 70 , about 0.0 volts is applied to BW terminal 76 , and about 0.0 volts is applied to substrate terminal 78 ; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to SL terminal 72 , about 0.0 volts is applied to BL terminal 74 , a potential of about 0.0 volts is applied to WL terminal 70 , about 0.0 volts is applied to BW terminal 76 (or +1.2 volts so that unselected cells are in the holding operation) and about 0.0 volts is applied to substrate terminal 78 . FIG. 120 B shows the bias conditions for the selected memory cell 150 . However, these voltage levels may vary.

FIG. 121 A shows a cross-sectional schematic illustration of a memory string 520 that includes a plurality of memory cells 150 connected in series, while FIG. 121 B shows a top view of a memory cell array 180 , which shows two strings of memory cells 520 between the SL terminal 72 and BL terminal 74 . Although FIG. 121 B schematically illustrates an array of two strings, it should be noted that the present invention is not limited to two strings, as one string, or more than two string can be made in the same manner as described. Each memory string 520 includes a plurality of memory cells 150 connected in a NAND architecture, in which the plurality of memory cells 150 are serially connected to make one string of memory cells. In a series connection, the same current flows through each of the memory cells 150 , from the BL terminal 74 to the SL terminal 72 , or vice versa. String 520 includes “n” memory cells 150 , where “n” is a positive integer, which typically ranges between 8 and 64, and in at least one example, is 16. However, string 520 could have less than eight cells (as low as two) or greater than sixty-four cells. The region 18 of a second conductivity at one end of the memory string is connected to the BL terminal 74 , while the source region 16 of a second conductivity at the other end of the memory string is connected to the SL terminal 72 .

Each memory cell transistor 150 includes a floating body region 24 of a first conducting type, and first and second regions 20 (corresponding to first and second regions 16 and 18 in the single cell embodiments of cell 150 described above) of a second conductivity type, which are spaced apart from each other and define a channel region. Regions 20 of adjacent memory cells within a string 520 are connected together by the conducting region 64 .

A buried layer 22 isolates the floating body region 24 from the bulk substrate 12 , while insulating layers 26 isolate the floating body region 24 between adjacent memory cells 150 . A gate 60 is positioned above the surface of floating body 24 and is in between the first and second regions 20 . An insulating layer 62 is provided between gate 60 and floating body 24 to insulate gate 60 from floating body 24 .

FIG. 121 C shows an equivalent circuit representation of a memory array 180 that includes strings 520 a and 520 b as well as additional strings. In FIG. 121 C , the memory cells are arranged in a grid, with the rows of the memory array 180 being defined by the WL terminals 70 , while the columns are defined by the BL terminals 74 . Within each column, multiple memory cells 150 are serially connected forming the string 520 . Adjacent columns are separated by columns of isolation, such as shallow trench isolation (STI).

The memory cell operations of memory string 520 will be described as follows. As will be seen, the operation principles of this embodiment of the memory string 520 will follow the operation principles of memory string 500 described above, where the back bias terminal 76 available in memory string 520 can be used to perform holding operation. In some embodiments, the transistors at the end of the string 520 (e.g., cells 150 a and 150 n in FIG. 121 A ) may be configured as access transistors to the memory string 520 , wherein the charges stored in the associated floating bodies 24 (floating bodies 24 a and 24 n in the example of FIG. 121 A ) are not read.

A read operation is described with reference to FIGS. 122 , 123 A and 123 B . The read operation can be performed by applying the following bias conditions, where memory cell 150 c within the memory string 520 a is being selected (as shown in FIG. 122 ): a positive voltage is applied to the selected BL terminal 74 , and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70 , zero voltage is applied to the selected SL terminal 72 , zero or positive voltage is applied to BW terminal 76 , and zero voltage is applied to the substrate terminal 78 . The unselected BL terminals 74 will remain at zero voltage and the unselected SL terminals 72 will remain at zero voltage as shown in FIG. 123 A . A positive voltage greater than the positive voltage applied to the selected WL terminal 70 c is applied to passing WL terminals 70 a , 70 b , 70 l , 70 m , and 70 n (see FIGS. 122 and 123 A- 123 B ). Passing WL terminals are connected to the gates of the passing cells, i.e. the unselected cells which are serially connected to the selected memory cell 150 c (e.g. memory cells 150 a , 150 b , 150 l , 150 m , and 150 n in FIG. 122 ). The voltages applied to the gates of the passing cells are such that the passing transistors are turned on, irrespective of the potentials of their floating body regions. The passing cells need to be turned on because in a series connection, the current flows from the BL terminal 74 to the SL terminal 72 (or vice versa) wherein current flows through each of the memory cells 150 . As a result, the passing cells will pass the potentials applied to the SL terminal 72 and BL terminal 74 to the source and drain regions 20 b and 20 c of the selected cell 150 c . For example, the memory cell 150 n will pass the voltage applied to the BL terminal 74 to region 20 m connected to cell 150 n (and 150 m ), which memory cell 150 m will subsequently pass to the region 201 connected to cell 150 l , etc. The adjacent passing memory cells sequentially pass the voltage applied to BL terminal 74 until it reaches region 20 c of the selected memory cell 50 c.

›DETAILED DESCRIPTION · 61 of 64

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 150 : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about +0.4 volts is applied to BL terminal 74 , a potential of about +1.2 volts is applied to selected WL terminal 70 , about +3.0 volts is applied to passing WL terminals 70 , about 0.0 volts is applied to BW terminal 76 , and about 0.0 volts is applied to substrate terminal 78 ; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to SL terminal 72 , about 0.0 volts is applied to BL terminal 74 , a potential of about 0.0 volts is applied to WL terminal 70 (but not passing WL terminal), about 0.0 volts is applied to BW terminal 76 (or +1.2 volts is applied to BW terminal 76 to maintain the states of the unselected memory cells), and about 0.0 volts is applied to substrate terminal 78 . FIGS. 123 A- 123 B show the bias conditions for the selected and unselected memory cells in memory array 180 . However, these voltage levels may vary.

Under these conditions, about +1.2 volts will be applied to the gate 60 c and about 0.0 volts and 0.4 volts will be passed to the regions 20 b and 20 c of the selected cell 150 c , similar to the read condition described in FIG. 117 . As described, the passing cells are biased so that their channels are conducting, and therefore the current flowing from the BL terminal 74 and SL terminal 72 of the string 520 is then determined by the potential of the floating body region 24 of the selected cell 150 c . If cell 150 c is in a state “1” having holes in the floating body region 24 , then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently be conducting a larger current compared to if cell 150 is in a state “0” having no holes in floating body region 24 .

The current flow from the BL terminal 74 to SL terminal 72 can then be measured or sensed using a read circuitry 90 attached to BL terminal 74 as illustrated in FIG. 123 B . The memory state can then be determined by comparing it with a reference value generated by a reference generator circuitry 92 coupled to a reference cell in memory string 520 R as shown in FIG. 123 B .

A write “0” operation is described with reference to FIGS. 124 - 125 , where the following bias conditions are applied: zero voltage to the SL terminal 72 , zero voltage to the WL terminals 70 , and negative voltage to the BL terminal 74 , while the BW terminal 76 and substrate terminal 78 are grounded. Under these conditions, the p-n junctions between floating body 24 and regions 20 of the memory cells in string 520 are forward-biased, evacuating any holes from the floating bodies 24 . In one particular non-limiting embodiment, about −1.2 volts is applied to terminal 74 , about 0.0 volts is applied to terminal 70 , and about 0.0 volts is applied to terminals 72 , 76 , and 78 . A positive voltage can also be applied to the WL terminals 70 to ensure that the negative voltage applied to the BL terminal 74 is passed to all the memory cells in string 520 . However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.

An alternative write “0” operation that allows for individual bit writing is illustrated in FIGS. 126 - 127 and can be performed by applying a negative voltage to BL terminal 74 , zero voltage to SL terminal 72 , zero voltage to BW terminal 76 , zero voltage to substrate terminal 78 , and a positive voltage to passing WL terminals. The selected WL terminal is initially grounded until the voltages applied to SL terminal 72 and BL terminal 74 reach the regions 20 b and 20 c , respectively, of selected memory cell 150 c . Subsequently, the potential of the selected WL terminal 70 is raised to a positive voltage higher than the positive voltage applied to passing WL terminals. Under these conditions, a positive voltage will be applied to the gate of the selected memory cell (e.g. memory cell 150 c in FIGS. 126 - 127 ) and consequently the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70 . The passing cells (e.g. memory cell 150 l , 150 m , and 150 n ) will pass the negative voltage applied to the BL terminal 74 to the region 20 c of the memory cell 150 c , while passing cells 150 a and 150 b will pass zero voltage applied to the SL terminal 72 to the region 20 b of the memory cell 150 c , similar to the conditions described in regard to FIG. 119 . As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74 , the p-n junction between floating body region 24 c and region 20 c is forward-biased, evacuating any holes from the floating body 24 . To reduce undesired write “0” disturb to other memory cells 150 in the memory array 180 , the applied potential can be optimized as follows: if the floating body 24 potential of state “1” is referred to V FB1 , then the voltage applied to the selected WL terminal 70 is configured to increase the floating body 24 potential by V FB1 /2 while −V FB1 /2 is applied to BL terminal 74 . The voltage applied to WL terminal of the passing cells is optimized such that it is high enough to pass the negative voltage applied to the BL terminal 74 , but cannot be too high to prevent the potential of the floating body 24 of the passing cells becoming too high, which will result in holes being evacuated from the passing cells that are in state “1”. A higher positive voltage can be applied to passing WL terminals passing zero voltage applied to the SL terminal 72 (e.g. passing WL terminals to the left of selected WL terminal 70 c , i.e. 70 a and 70 b in FIG. 126 ) than the voltage applied to passing WL terminals passing negative voltage applied to the BL terminal 74 (e.g. passing WL terminals to the right of selected WL terminal 70 c ). This is because the higher voltage applied to terminal 72 (compared to the negative voltage applied to terminal 74 ) may require a higher passing gate voltage for the passing transistors to be turned on.

›DETAILED DESCRIPTION · 62 of 64

In one particular non-limiting embodiment, the following bias conditions are applied to the memory string 520 : a potential of about 0.0 volts to SL terminal 72 , a potential of about −0.2 volts to BL terminal 74 , a potential of about +0.5 volts is applied to selected terminal 70 , a potential of about +0.2 volts is applied to passing WL terminals 70 , about 0.0 volts is applied to BW terminal 76 , and about 0.0 volts is applied to substrate terminal 78 ; while about 0.0 volts is applied to unselected SL terminal 72 , about 0.0 volts is applied to unselected BL terminal 74 , about 0.0 volts is applied to BW terminal 76 (or +1.2 volts is applied to BW terminal 76 to maintain the states of the unselected memory cells), about 0.0 volts is applied to unselected (but not passing) WL terminal 70 , and about 0.0 volts is applied to unselected terminal 78 . FIGS. 126 - 127 show the bias conditions for the selected and unselected memory cells in memory array 180 where memory cell 150 c is the selected cell. However, these voltage levels may vary.

Under these bias conditions, a positive voltage will be applied to the gate 60 of the selected cell 150 c , while a negative voltage applied to the BL terminal 74 will be passed to the region 20 c of the selected cell 150 c , and zero voltage applied to the SL terminal 72 will be passed to the region 20 b of the selected cell 150 c . This condition is similar to the condition described in regard to FIG. 119 , and results in hole evacuation out of the floating body 24 c of the cell 150 c.

A write “1” operation can be performed on memory cell 150 through impact ionization as described for example in Lin et al., “A New 1T DRAM Cell with Enhanced Floating Body Effect”, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, which was incorporated by reference above, or a write “1” operation can be performed through a band-to-band tunneling mechanism, as described for example in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.

An example of bias conditions on a selected memory cell 150 under a band-to-band tunneling write “1” operation is illustrated in FIGS. 128 and 129 . A negative bias is applied to the selected WL terminal 70 , a positive voltage is applied to the passing WL terminals 70 , zero voltage is applied to the SL terminal 72 , and a positive bias applied to the BL terminal 74 , zero voltage is applied to the BW terminal 76 , while the substrate terminal 78 is grounded. This condition results in hole injection to the floating body 24 of the selected memory cell (e.g. cell 150 c in FIGS. 128 - 129 ).

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 150 c : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about +1.2 volts is applied to BL terminal 74 , a potential of about −1.2 volts is applied to the selected WL terminal 70 , about +3.0 volts is applied to the passing WL terminals 70 , about 0.0 volts is applied to BW terminal 76 , and about 0.0 volts is applied to substrate terminal 78 ; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to SL terminal 72 , about 0.0 volts is applied to BL terminal 74 , a potential of about 0.0 volts is applied to WL terminal 70 (but not passing WL terminal), about 0.0 volts is applied to BW terminal 76 (or +1.2 volts is applied to maintain the states of the unselected memory cells), and about 0.0 volts is applied to substrate terminal 78 . FIG. 129 shows the bias conditions for the selected and unselected memory cells in memory array 180 where memory cell 150 c is the selected cell. However, these voltage levels may vary.

Under these bias conditions, a negative voltage will be applied to the gate 60 of the selected cell 150 c , while a positive voltage applied to the BL terminal 74 will be passed to the region 20 c of the selected cell 150 c , and zero voltage applied to the SL terminal 72 will be passed to the region 20 b of the selected cell 150 c . This condition is similar to the condition described in FIG. 120 A , and results in hole injection to the floating body 24 c of the cell 150 c.

An example of the bias conditions on the selected memory cell 150 under an impact ionization write “1” operation is illustrated in FIGS. 130 A- 130 B . A positive bias is applied to the selected WL terminal 70 , a positive voltage more positive than the positive voltage applied to the selected WL terminal 70 is applied to the passing WL terminals 70 , zero voltage is applied to the SL terminal 72 , a positive bias is applied to the BL terminal 74 , and zero voltage is applied to BW terminal 76 , while the substrate terminal 78 is grounded. These conditions result in hole injection to the floating body 24 of the selected memory cell (e.g. cell 150 c in FIGS. 130 A- 130 B ).

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 150 c : a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about +1.2 volts is applied to BL terminal 74 , a potential of about +1.2 volts is applied to the selected WL terminal 70 , about +3.0 volts is applied to the passing WL terminals 70 , about 0.0 volts is applied to BW terminal 76 , and about 0.0 volts is applied to substrate terminal 78 ; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to SL terminal 72 , about 0.0 volts is applied to BL terminal 74 , a potential of about 0.0 volts is applied to WL terminal 70 (but not passing WL terminal), about 0.0 volts is applied to BW terminal 76 (or +1.2 volts is applied to BW terminal 76 to maintain the states of the unselected memory cells), and about 0.0 volts is applied to substrate terminal 78 . FIG. 130 B shows the bias conditions for the selected and unselected memory cells in memory array 180 (with memory cell 150 c as the selected cell). However, these voltage levels may vary.

›DETAILED DESCRIPTION · 63 of 64

A multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to the memory cell 150 , followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to the memory cell 150 , followed by another read verification operation. This loop is repeated until the desired memory state is achieved.

For example, using band-to-band hot hole injection, a positive voltage is applied to BL terminal 74 , zero voltage is applied to SL terminal 72 , a negative voltage is applied to the selected WL terminal 70 , a positive voltage is applied to the passing WL terminals, zero voltage is applied to the BW terminal 76 and zero voltage is applied to the substrate terminal 78 . Positive voltages of different amplitudes are applied to BL terminal 74 to write different states to floating body 24 . This results in different floating body potentials 24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied to BL terminal 74 . In one particular non-limiting embodiment, the write operation is performed by applying the following bias conditions: a potential of about 0.0 volts is applied to SL terminal 72 , a potential of about −1.2 volts is applied to the selected WL terminal 70 , about +3.0 volts is applied to the passing WL terminals, about 0.0 volts is applied to BW terminal 76 , and about 0.0 volts is applied to substrate terminal 78 , while the potential applied to BL terminal 74 is incrementally raised. For example, in one non-limiting embodiment, 25 millivolts is initially applied to BL terminal 74 , followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e. cell current corresponding to whichever state of 00, 01, 10 or 11 is the desired state has been achieved), then the multi write operation is concluded. If the desired state has not been achieved, then the voltage applied to BL terminal 74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary. The write operation is followed by a read operation to verify the memory state.

The string 520 may be constructed from a plurality of planar cells, such as the embodiments described above with reference to FIGS. 23 and 121 A , or may be constructed from fin-type, three-dimensional cells, such as illustrated in FIGS. 32 - 33 above. Other variations, modifications and alternative cells 150 may be provided without departing from the scope of the present invention and its functionality.

Another embodiment of memory array 880 is described with reference to FIGS. 131 A- 131 B , where FIG. 131 A shows a top view of the memory array 880 consisting of two strings of memory cells 540 between the SL terminal 72 and BL terminal 74 , and FIG. 131 B shows the cross section of a memory string 540 . Although FIG. 131 A schematically illustrates an array of two strings, it should be noted that the present invention is not limited to two strings, as more than two, or even only one string could be provided.

Each memory string 540 of array 880 includes a plurality of memory cells 850 connected in a NAND architecture, in which the plurality of memory cells 850 are serially connected to make one string of memory cells. String 540 includes “n” memory cells 850 , where “n” is a positive integer, which typically ranges between 8 and 64, and in at least one example, is 16. However, this embodiment, like the embodiment above is not limited to the stated range, as fewer than eight or more than sixty-four cells could be included in a string. The region 18 of a second conductivity at one end of the memory string is connected to the BL terminal 74 through contact 73 , while the source region 16 of a second conductivity at the other end of the memory string is connected to the SL terminal 72 through contact 71 . In some embodiments, the transistors at the ends of the string 540 (e.g., cells 850 a and 850 n in the example of FIG. 131 B ) may be configured as access transistors to the memory string 540 , and charged stored in the associated floating bodies 24 ( 24 a and 24 n in the example of FIG. 131 B ) are not read.

Referring to FIG. 131 B , the memory cell 850 includes a substrate 12 of a first conductivity type, such as p-type, for example. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. A buried layer 22 of a second conductivity type such as n-type, for example, is provided in the substrate 12 . Buried layer 22 may be formed by an ion implantation process on the material of substrate 12 . Alternatively, buried layer 22 can also be grown epitaxially on top of substrate 12 .

A floating body region 24 of the first conductivity type, such as p-type, for example, is bounded on top by region 16 (or region 18 or region 20 ) of the second conductivity type and insulating layer 62 , on the sides by region 16 (or region 18 or region 20 ) of the second conductivity type and insulating layers 30 and 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulating layer 30 and the region 16 (or region 18 or region 20 ) of the second conductivity type insulate the floating body region 24 along the I-I′ direction as shown in FIG. 131 B , while insulating layer 28 insulates the floating body region 24 along the II-II′ direction as shown in FIG. 131 A .

Regions 16 , 18 , and 20 having a second conductivity type, such as n-type, for example, are provided in substrate 12 and are exposed at surface 14 . Regions 16 , 18 , and 20 may be formed by an implantation process formed on the material making up substrate 12 , according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to form regions 16 , 18 , and 20 . Although regions 16 , 18 , and 20 have the same conductivity type (for example n-type), the dopant concentration forming these regions can be (but need not necessarily be) different. In FIGS. 131 A and 131 B , regions 16 and 18 are located at the ends of the memory string 540 , while regions 20 are located inside the memory string 540 , isolating adjacent floating body regions 24 of adjacent memory cells 850 .

›DETAILED DESCRIPTION · 64 of 64

A gate 60 is positioned above the surface of floating body 24 and is in between the first and second regions 20 (or between region 16 and region 20 or between region 18 and region 20 ). The gate 60 is insulated from floating body region 24 by an insulating layer 62 .

Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Memory string 540 further includes word line (WL) terminals 70 electrically connected to gates 60 , source line (SL) terminal 72 electrically connected to region 16 , bit line (BL) terminal 74 electrically connected to region 18 , buried layer (BW) terminal 76 connected to buried layer 22 , and substrate terminal 78 electrically connected to substrate 12 .

The BW terminal 76 connected to the buried layer region 22 serves as a back bias terminal, i.e. a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor.

A method of manufacturing memory array 880 will be described with reference to FIGS. 132 A- 132 U . These figures are arranged in groups of three related views, with the first figure of each group being a top view of memory cell 850 , the second figure of each group being a vertical cross section of the top view in the first figure of the group designated I-I′, and the third figure of each group being a vertical cross section of the top view in the first figure of the group designated II-II′.

Turning now to FIGS. 132 A through 132 C , the first steps of the process can be seen starting with growing a thick conductive region 202 comprised of a different material from the materials forming the substrate region 12 . The conductive region 202 can be selectively etched without removing the substrate region 12 . For example, the conductive region 202 could be made of silicon germanium (SiGe) material, while substrate 12 could be made of silicon, although materials for both of these layers may vary.

As shown in FIGS. 132 D through 132 F , a pattern 30 ′ covering the areas to become insulator region 30 (as shown in the final structures in FIGS. 132 S through 132 U) is formed using a lithography process. The conductive region 202 is then etched following the lithography pattern.

Referring to FIGS. 132 G through 132 I , a conductive region 204 comprising for example the same material forming the substrate 12 is grown (like, for example, silicon). A chemical mechanical polishing step can then be performed to polish the resulting films so that the silicon surface is flat. Subsequently, a thin layer of silicon oxide 206 is grown on the surface of film 204 . This is followed by a deposition of a polysilicon layer 208 and then silicon nitride layer 210 .

Next, a pattern is formed for use in opening the areas to become insulator regions 28 . The pattern can be formed using a lithography process. This is then followed by dry etching of the silicon nitride layer 210 , polysilicon layer 208 , silicon oxide layer 206 , and silicon layer 204 , creating trench 212 , as shown in FIGS. 132 J and 132 L (trenches 212 are not visible in the view of FIG. 132 K ).

A wet etch process that selectively removes the region 202 is then performed, leaving gaps that are mechanically supported by region 204 The resulting gap regions are then oxidized to form buried oxide regions 30 as shown in FIGS. 132 N and 132 O . Subsequently, the remaining silicon nitride layer 210 , polysilicon layer 208 , and silicon oxide layer 206 are then removed, followed by a silicon oxide deposition process and a chemical mechanical polishing step to planarize the resulting silicon oxide film, resulting in the silicon oxide insulator region 28 as shown in FIGS. 132 M and 132 O . Alternatively, the silicon deposition step can be performed prior to the removal of the silicon nitride layer 210 , polysilicon layer 208 and silicon oxide layer 206 .

Referring to FIGS. 132 P through 132 R , an ion implantation step is next performed to form the buried layer region 22 . Subsequently a silicon oxide layer (or high-dielectric material layer) 62 is formed on the silicon surface ( FIGS. 132 Q- 132 R ), followed by polysilicon (or metal) layer 214 deposition ( FIGS. 132 Q- 132 R ).

A pattern covering the area to be made into gate 60 is next made, such as by using a lithography process. The pattern forming step is followed by dry etching of the polysilicon (or metal) layer 214 and silicon oxide (or high dielectric materials) layer 62 . An ion implantation step is then performed to form the regions 20 of the second conductivity type (e.g. n-type). The conductive region 204 underneath the gate region 60 is protected from the ion implantation process and is now bounded by regions 20 , insulating layer 30 and insulating layer 28 on the sides, and by buried layer 22 from the substrate 12 , and by insulating layer 62 at the surface, forming the floating body region 24 (see FIG. 132 T ). This is then followed by backend process to form contact and metal layers (not shown in figures).

Another embodiment of memory array is shown as memory array 980 in FIG. 133 , wherein memory array 980 comprises a link connecting a plurality of memory cells 950 in parallel. FIG. 134 A shows a top view of memory cell 950 in isolation, with FIGS. 134 B and 134 C showing sectional views of the memory cell 950 taken along lines I-I′ and II-II′, respectively.

Referring to FIGS. 134 B and 134 C together, the cell 950 is fabricated on silicon on insulator (SOI) substrate 12 of a first conductivity type such as a p-type, for example. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, galliu

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Claims as granted

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Classifications

14 codes

IPC · International Patent Classification

Section G — Physics

G11C14/00
G11C11/404
G11C11/56
G11C16/04
G11C16/06

Section H — Electricity

H10B41/35
H10B41/30
H10B41/00
H10B12/00
H10B69/00
H10D30/68
H10D62/10
H10D64/27
H10D64/66

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