Signal receiver and slicer

1. Field of the Invention

The present disclosure is related to a signal receiver and a slicer, especially to a signal receiver and a slicer capable of mitigating the static mismatch error of a far-end digital-to-analog converter.

2. Description of Related Art

The variation in a process, voltage, and temperature (PVT) will cause a mismatch problem with respect to the scale and the pulse shape of the output of a digital-to-analog converter (DAC) (e.g., current DAC). A mismatch appears on the scale is called a static mismatch error and a mismatch appears on the pulse shape is called a dynamic mismatch error, wherein the static mismatch error will seriously affect the performance of a circuit system. It is noted that when the above-mentioned DAC is a far-end DAC, the circuit system receiving signals originated from the far-end DAC acts as a local system.

An object of the present disclosure is to provide a signal receiver and a slicer capable of mitigating the static mismatch error of a far-end digital-to-analog converter (far-end DAC).

An embodiment of the signal receiver of the present disclosure includes an analog-front-end (APE) circuit, an analog-to-digital converter (ADC), an equalizer circuit, an adjustable slicing circuit, and an error signal generating circuit. The AFE circuit is configured to generate an analog signal according to a received signal originated from a far-end DAC. The ADC is configured to generate a digital signal according to the analog signal. The equalizer circuit is configured to generate an input signal according to the digital signal. The adjustable slicing circuit is configured to determine which level of (N+1) signal levels is corresponding to the input signal according to N slicer levels and thereby generate an output signal, wherein the N is an integer greater than two. The adjustable slicing circuit is further configured to adjust at least a part of the (N+1) signal levels according to an error signal and adjust at least a part of the N slicer levels so as to mitigate the static mismatch error of the far-end DAC. The error signal generating circuit is coupled to the adjustable slicing circuit and configured to generate the error signal according to the input signal and output signal.

An embodiment of the slicer of the present disclosure includes an adjustable slicing circuit and an error signal generating circuit. The adjustable slicing circuit is configured to determine which level of (N+1) signal levels is corresponding to an input signal according to N slicer levels and thereby generate an output signal, wherein the input signal is originated from a far-end DAC and the N is an integer greater than two. The adjustable slicing circuit is further configured to adjust at least a part of the (N+1) signal levels according to an error signal and adjust at least a part of the N slicer levels so as to mitigate the static mismatch error of the far-end DAC. The error signal generating circuit is coupled to the adjustable slicing circuit and configured to generate the error signal according to the input signal and output signal.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings.

FIG. 1 shows an embodiment of the signal receiver of the present disclosure.

FIG. 2 shows an embodiment of the equalizer circuit of FIG. 1 .

The present specification discloses a signal receiver and a slicer capable of mitigating the static mismatch error of a far-end digital-to-analog converter (far-end DAC). The static mismatch error is referred to: the level of an output signal of the far-end DAC being equal to a predetermined signal level plus an unwanted offset due to the variation in a process, voltage, or temperature, which may bring a signal receiver difficulty in determining the level of the output signal accurately.

FIG. 1 shows an embodiment of the signal receiver of the present disclosure. The signal receiver 100 of FIG. 1 is a wired signal receiver (e.g., Gigabit Ethernet device) including an analog-front-end (AFE) circuit 110 , an analog-to-digital converter (ADC) 120 , an equalizer circuit 130 , an adjustable slicing circuit 140 , and an error signal generating circuit 150 . The details of the embodiment of FIG. 1 are described in the following paragraphs.

In regard to the embodiment of FIG. 1 , the AFE circuit 110 is configured to generate an analog signal S A according to a received signal S R , wherein the received signal S R is originated from the aforementioned far-end DAC and transmitted to the signal receiver 100 via a wired transmission channel. The AFE circuit 110 alone is a known/self-developed circuit, and its detail falls beyond the scope of the present disclosure.

In regard to the embodiment of FIG. 1 , the ADC 120 is configured to generate a digital signal S D according to the analog signal S A . The ADC 120 alone is a known/self-developed circuit, and its detail falls beyond the scope of the present disclosure.

In regard to the embodiment of FIG. 1 , the equalizer circuit 130 is configured to generate an input signal S IN according to the digital signal S D . The equalizer circuit 130 can optionally be configured to generate the input signal S IN according to a feedback signal from the adjustable slicing circuit 140 (i.e., the output signal S OUT from the adjustable slicing circuit 140 to the equalizer circuit 130 ) and an error signal S ERR from the error signal generating circuit 150 (i.e., the error signal S ERR from the error signal generating circuit 150 to the equalizer circuit 130 ) as shown in FIG. 1 . The equalizer circuit 130 alone is a known/self-developed circuit; for example, as shown in FIG. 2 , the equalizer circuit 130 includes a feed-forward equalizer (FFE) 210 , a multiplier 220 , a digital automatic gain control (DACG) circuit 230 , an adder 240 , and a feedback equalizer (FBE) 250 . Each circuit in FIG. 2 alone is a known/self-developed circuit, and its detail falls beyond the scope of the present disclosure. It is noted that the setting and adjustment of parameters of the equalizer circuit 130 can be determined according to the demand for implementation, and this falls beyond the scope of the present disclosure.

In regard to the embodiment of FIG. 1 , the adjustable slicing circuit 140 is configured to determine which level of (N+1) signal levels is corresponding to the input signal S IN according to N slicer levels and thereby generate an output signal S OUT having the determined level, wherein the N slicer levels are in incremental order (i.e., 1 st slicer level, 2 nd slicer level, . . . , N th slicer level), the (N+1) signal levels are in incremental order (i.e., 1 st signal level, 2 nd signal level, . . . , (N+1) th signal level), and the N is an integer greater than two. For example, when the level of the input signal S IN is higher than the N th slicer level (i.e., the maximum slicer level of the N slicer levels), the adjustable slicing circuit 140 determines that the input signal S IN is corresponding to the (N+1) th signal level (i.e., the maximum signal level of the (N+1) signal levels) and then generates the output signal S OUT having the (N+1) th signal level; when the level of the input signal S IN is lower than the 1 st slicer level (i.e., the minimum slicer level of the N slicer levels), the adjustable slicing circuit 140 determines that the input signal S IN is corresponding to the 1 st signal level (i.e., the minimum signal level of the (N+1) signal levels) and then generates the output signal S OUT having the 1 st signal level; and when the level of the input signal S IN is higher than a certain slicer level (hereinafter referred to as “the X th slicer level”) of the N slicer levels, the adjustable slicing circuit 140 determines that the input signal S IN is corresponding to the (X+1) th signal level of the (N+1) signal levels and then generates the output signal S OUT having the (X+1) th signal level, wherein the X is a positive integer not greater than N.

In regard to the embodiment of FIG. 1 , the adjustable slicing circuit 140 is further configured to adjust at least a part of the (N+1) signal levels according to the error signal S ERR and adjust at least a part of the N slicer levels so as to mitigate the static mismatch error of the aforementioned far-end DAC, wherein the error signal S ERR is generated by the error signal generating circuit 150 according to the input signal S IN and the output signal S OUT . For example, the error signal S ERR is equal to the difference between the input signal S IN and the output signal S OUT (i.e., S ERR =S IN −S OUT ).

On the basis of the above description, when the level of the output signal S OUT is a K th signal level of the (N+1) signal levels, the adjustable slicing circuit 140 adjusts the K th signal level according to the error signal S ERR and then adjusts at least one target slicer level of the N slicer levels neighboring the K th signal level according to a K th cumulative adjustment amount of the K th signal level, wherein the K is a positive integer between 1 and (N+1).

In an exemplary embodiment, as the error signal S ERR changes, the K th cumulative adjustment amount (Train(K th )) is adjusted to be equal to the current K th cumulative adjustment amount plus a coefficient (e.g., 2 −10 ) multiplied by the error signal S ERR , which can be expressed as follows:

Train( K th )=Train( K th )+Mu×S ERR   (eq. 1)

The above equation shows that the K th cumulative adjustment amount is increased by Mu×S ERR . An initial value of the K th cumulative adjustment amount can be zero or determined according to the demand for implementation. The coefficient can be determined according to the demand for implementation.

In the aforementioned exemplary embodiment, when the level of the output signal S OUT is the K th signal level, the adjustable slicing circuit 140 can add up the initial value of the K th signal level (i.e., Lvl(K th ) INI ) and the K th cumulative adjustment amount (i.e., Train(K th ) on the left side of the equal sign of eq. 1) to obtain the adjusted K th signal level (i.e., Lvl(K th )), which can be expressed as follows:

Lvl ( K th )= Lvl ( K th ) INI +Train( K th )  (eq. 2)

In the aforementioned exemplary embodiment, if the K is less than (N+1), after adjusting the K th signal level, the adjustable slicing circuit 140 adjusts an upper target slicer level of the N slicer levels between the K th signal level and a (K+1) th signal level of the (N+1) signal levels according to the K th signal level and the (K+1) th signal level. For example, the adjustable slicing circuit 140 adds up an initial value of the upper target slicer level

( i . e . , Slicer ⁢ Lv ⁢ 1 ⁢ ( K + ( K + 1 ) th 2 ) INI ) ,

and an average of the K th cumulative adjustment amount (i.e., the latest Train(K th )) and a (K+1) th cumulative adjustment amount (i.e., the latest Train((K+1) th )) of the (K+1) th signal level to obtain the adjusted upper target slicer level

( i . e . , Slicer ⁢ Lv ⁢ 1 ⁢ ( K + ( K + 1 ) th 2 ) ) ,

which can be expressed as follows:

In the aforementioned exemplary embodiment, if the K is greater than one, after adjusting the K th signal level, the adjustable slicing circuit 140 adjusts a lower target slicer level of the N slicer levels between the K th signal level and a (K−1) th signal level of the (N+1) signal levels according to the K th signal level and the (K−1) th signal level. For example, the adjustable slicing circuit 140 adds up an initial value of the upper target slicer level

( i . e . , Slicer ⁢ Lv ⁢ 1 ⁢ ( K + ( K - 1 ) th 2 ) INI )

and an average of the K th cumulative adjustment amount (i.e., the latest Train(K th )) and a (K−1) th cumulative adjustment amount (i.e., the latest Train((K−1) th )) of the (K−1) th signal level to obtain the adjusted lower target slicer level

( i . e . , Slicer ⁢ Lv ⁢ 1 ⁢ ( K + ( K - 1 ) th 2 ) ) ,

which can be expressed as follows:

It is noted that if the equalizer circuit 130 generates the input signal S IN according to the digital signal S D and the feedback signal (i.e., the output signal S OUT ) of the adjustable slicing circuit 140 , the input signal S IN and the output signal Sour may interact with each other and change interdependently, which may lead to the overflow of hardware. In order to prevent the overflow of hardware, the adjustable slicing circuit 140 can optionally make at least two signal levels of the (N+1) signal levels remain unchanged and thereby make an anchoring effect. For example, the at least two signal levels are a (N+1) th signal level and a first signal level of the (N+1) signal levels; in other words, the at least two signal levels are the maximum and minimum signal levels of the (N+1) signal levels. For example, the at least two signal levels are any other two signal levels of the (N+1) signal levels (e.g., the second maximum signal level and the second minimum signal level of the (N+1) signal levels), if practicable.

In an exemplary embodiment, the (N+1) signal levels are sixteen signal levels (i.e., Lvl(K th ):: Lvl(16 th ), Lvl(15 th ), . . . , Lvl(2 nd ), and Lvl(1 st )), and their initial values (i.e., Lvl(K th ) INI : Lvl(16 th ) INI , Lvl(15 th ) INI , . . . , Lvl(2 st ) INI , and Lvl(1 st ) INI ) are in decremental order as follows: 15, 13, 11, 9, 7, 5, 3, 1, −1, −3, −5, −7, −9, −11, −13, and −15; the N slicer levels are fifteen slicer levels

( i . e . , Slicer ⁢ Lv ⁢ 1 ⁢ ( K + ( K ± 1 ) th 2 ) :

SlicerLvl(15.5 th ), SlicerLvl(14.5 th ), . . . , SlicerLvl(2.5 th ), and SlicerLvl(1.5 th )), and their initial values

( i . e . , Slicer ⁢ Lv ⁢ 1 ⁢ ( K + ( K ± 1 ) th 2 ) INI :

SlicerLvl(15.5 th ) INI , SlicerLvl(14.5 th ) INI , . . . , SlicerLvl(2.5 th ) INI , and SlicerLvl(1.5 th ) INI ) are in decremental order as follows: 14, 12, 10, 8, 6, 4, 2, 0, −2, −4, −6, −8, −10, −12, −14. Each signal level/slicer level here is a numerical value, and its physical meaning (e.g., signal strength) can be defined according to the demand for implementation. Table 1 shows the adjusted sixteen signal levels and the adjusted fifteen slicer levels, wherein the maximum signal level (i.e., Lvl(16 th )=15) and the minimum signal level (i.e., Lvl(1 st )=−15) remain constant to function as anchors. In Table 1, when Train(M) represents the aforementioned Train(K th ), Train(M+2) and Train(M−2) represent the aforementioned Train((K+1) th ) and Train((K−1) th ) respectively, wherein M is an odd integer between 15 and −15.

It is noted that the adjustable slicing circuit 140 and the error signal generating circuit 150 of FIG. 1 can jointly function as a slicer which can be implemented independently. The slicer can be applied to any known/self-developed signal receiver as long as such applications are practicable.

It should be noted that people of ordinary skill in the art can selectively use some or all of the features of any embodiment in this specification or selectively use some or all of the features of multiple embodiments in this specification to implement the present invention as long as such implementation is practicable; in other words, the present invention can be carried out flexibly in accordance with the present disclosure.

To sum up, the signal receiver and the slicer of the present disclosure can mitigate the static mismatch error of a far-end DAC.

The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.