Semiconductor device having buffer circuit

A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) includes a buffer circuit that transfers data between a memory cell array and an I/O (Input/Output) circuit. There is a case where the buffer circuit is divided into an ODD buffer circuit to be allocated to a memory bank accessed at a certain timing and an EVEN buffer circuit to be allocated to a memory bank accessed at another timing Each of the ODD buffer circuit and the EVEN buffer circuit is composed of a plurality of unit buffer circuits to which different addresses are respectively allocated. The unit buffer circuits constituting the ODD buffer circuit and the unit buffer circuits constituting the EVEN buffer circuit are alternately arrayed in one direction in some cases to simplify coupling to a different buffer circuit arranged in the memory cell array. However, this layout has a problem that an area occupied by a control circuit controlling the buffer circuits is increased and that wiring lengths of lines that connect the buffer circuits to the control circuit are elongated.

FIG. 1 is a schematic plan view showing a configuration of a semiconductor memory device according to one embodiment of the present disclosure;

FIG. 2 is a schematic diagram for explaining a circuit configuration of buffer circuits and a connection relation therebetween;

FIG. 3 is a schematic diagram for explaining a connection relation between unit buffer circuits and a control circuit; and

FIG. 4 is a schematic diagram for explaining a connection relation between unit buffer circuits and data buses.

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects, and various embodiments of the present disclosure. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

FIG. 1 is a schematic plan view showing a configuration of a semiconductor memory device 100 according to one embodiment of the present disclosure. The semiconductor memory device 100 shown in FIG. 1 is a DRAM and includes a plurality of bank groups BG 0 to BGn and a peripheral circuit area CHA. The bank groups BG 0 to BGn are arrayed in a Y direction. Each of the bank groups BG 0 to BGn includes a memory cell array 110 , an amplifier circuit 112 , and buffer circuits 20 A and 20 B. The peripheral circuit area CHA is arranged at an end in the Y direction. The peripheral circuit area CHA includes a command address circuit area 30 and data I/O circuit areas 40 A and 40 B. A command address terminal to which a command address signal is input, a decoder circuit that decodes the command address signal, a control circuit that generates various control signals on the basis of the command address signal, a calibration circuit, and the like are arranged in the command address circuit area 30 . A data terminal to and from which data is input and output, an I/O circuit, and the like are arranged in each of the data I/O circuit areas 40 A and 40 B. Buffer circuits 10 A and 10 B are allocated to the data I/O circuit areas 40 A and 40 B, respectively. The buffer circuit 10 A is coupled to the I/O circuit included in the data I/O circuit area 40 A via a data bus 51 A and is coupled to the buffer circuits 20 A included in the bank groups BG 0 to BGn via a data bus 52 A. The buffer circuit 10 B is coupled to the I/O circuit included in the data I/O circuit area 40 B via a data bus 51 B and is coupled to the buffer circuits 20 B included in the bank groups BG 0 to BGn via a data bus 52 B. The data buses 51 A and 51 B extend mainly in an X direction. The data buses 52 A and 52 B extend mainly in the Y direction.

At the time of a read operation, read data that is read from any of the memory cell arrays 110 is transferred to the data bus 52 A or 52 B via the buffer circuit 20 A or 20 B in an associated one of the buffer groups BG 0 to BGn and is further transferred to the data I/O circuit area 40 A or 40 B via the buffer circuit 10 A or 10 B and the data bus 51 A or 51 B. At the time of a write operation, write data that is input to the data I/O circuit area 40 A or 40 B is transferred to the data bus 52 A or 52 B via the data bus 51 A or 51 B and the buffer circuit 10 A or 10 B and is further transferred to one of the memory cell arrays 110 via the buffer circuit 20 A or 20 B included in an associated one of the bank groups BG 0 to BGn.

FIG. 2 is a schematic diagram for explaining a circuit configuration of the buffer circuits 10 A and 20 A and a connection relation therebetween. As shown in FIG. 2 , the buffer circuit 20 A includes 16 unit buffer circuits BUF 0 to BUF 15 arrayed in the X direction, and a control circuit 62 . Different addresses are allocated to the unit buffer circuits BUF 0 to BUF 15 , respectively. The control circuit 62 controls operations of the unit buffer circuits BUF 0 to BUF 15 and corrects errors in data. That is, when an error occurs in data supplied to the unit buffer circuits BUF 0 to BUF 15 , the error is corrected by an error correction circuit (On die ECC) included in the control circuit 62 . Eight-bit data is allocated to each of the unit buffer circuits BUF 0 to BUF 15 . In this case, the number of bits of data input or output at one time via the buffer circuit 20 A is 128 .

The buffer circuit 10 A includes 16 unit buffer circuits BUF 0 o to BUF 15 o constituting the ODD buffer circuit, 16 unit buffer circuits BUF 0 e to BUF 15 e constituting the EVEN buffer circuit, and control circuits 61 o and 61 e . The size of the buffer circuit 10 A in the X direction is smaller than that of the buffer circuit 20 A in the X direction. Accordingly, the buffer circuit 20 A has a part overlapping the buffer circuit 10 A in the Y direction and a part not overlapping the buffer circuit 10 A in the Y direction. The control circuits 61 o and 61 e control operations of the unit buffer circuits BUF 0 o to BUF 15 o and the unit buffer circuits BUF 0 e to BUF 15 e , respectively. An error correction circuit (Link ECC) is included in each of the control circuits 61 o and 61 e . Accordingly, an error is corrected by the error correction circuit included in the control circuit 61 o when the error occurs in data supplied to the unit buffer circuits BUF 0 o to BUF 15 o , and an error is corrected by the error correction circuit included in the control circuit 61 e when the error occurs in data supplied to the unit buffer circuits BUF 0 e to BUF 15 e.

The ODD buffer circuit and the EVEN buffer circuit are provided in one embodiment of the present disclosure. For example, the ODD buffer circuit can be associated with odd-numbered bank groups and the EVEN buffer circuit can be associated with even-numbered bank groups. Alternatively, the ODD buffer circuit and the EVEN buffer circuit may be associated with odd-numbered banks and even-numbered banks in bank groups, respectively, or may be associated with odd-numbered column addresses and even-numbered column addresses in banks, respectively. When one of the groups or addresses is selected, the ODD or EVEN buffer circuit associated therewith is used. When the ODD buffer circuit is to be used, the unit buffer circuits BUF 0 o to BUF 15 o are selected and data transfer to and from the unit buffer circuits BUF 0 to BUF 15 included in each of the buffer circuits 20 A is performed via the data bus 52 A. When the EVEN buffer circuit is to be used, the unit buffer circuits BUF 0 e to BUF 15 e are selected and data transfer to and from the unit buffer circuit BUF 0 to BUF 15 included in each of the buffer circuits 20 A is performed via the data bus 52 A.

The unit buffer circuits BUF 0 e to BUF 7 e and the unit buffer circuit BUF 0 o to BUF 7 o are arrayed in this order in the Y direction. The unit buffer circuits BUF 15 e to BUF 8 e and the unit buffer circuits BUF 15 o to BUF 8 o are arrayed in this order in the Y direction. The unit buffer circuits BUF 0 e to BUF 7 e and the unit buffer circuits BUF 15 e to BUF 8 e are arrayed in the X direction and the control circuit 61 e is arranged therebetween. Similarly, the unit buffer circuits BUF 0 o to BUF 7 o and the unit buffer circuits BUF 15 o to BUF 8 o are arrayed in the X direction and the control circuit 61 o is arranged therebetween. The control circuit 61 e and the control circuit 61 o are next to each other in the Y direction. With this layout, the wiring length of lines that connect the unit buffer circuits BUF 0 e to BUF 15 e to the control circuit 61 e can be shortened and the area occupied by the control circuit 61 e can be reduced as illustrated in FIG. 3 . Similarly, the wiring length of lines that connect the unit buffer circuits BUF 0 o to BUF 15 o to the control circuit 61 o can be shortened and the area occupied by the control circuit 61 o can be reduced.

In the example shown in FIG. 2 , the unit buffer circuits BUF 0 e and BUF 15 e are closest to the buffer circuit 20 A and the unit buffer circuits BUF 7 e and BUF 8 e are farthest from the buffer circuit 20 A among the unit buffer circuits BUF 0 e to BUF 15 e . Meanwhile, the unit buffer circuits BUF 0 and BUF 15 are located at both ends in the X direction, respectively, and the unit buffer circuits BUF 7 and BUF 8 are arranged in a substantial central portion in the X direction in the buffer circuit 20 A. Particularly, the unit buffer circuit BUF 7 has an overlap with the unit buffer circuits BUF 0 e to BUF 7 e in the Y direction and the unit buffer circuit BUF 8 has an overlap with the unit buffer circuits BUF 8 e to BUF 15 e in the Y direction. In contrast thereto, the unit buffer circuits BUF 0 and BUF 15 are located at the both ends in the X direction and accordingly do not have an overlap with the unit buffer circuits BUF 0 e to BUF 15 e in the Y direction. With this layout, ones of the unit buffer circuits BUF 0 to BUF 15 included in the buffer circuit 20 A and arranged at locations closer to the ends in the X direction are farther from the buffer circuit 10 A. However, in the layout shown in FIG. 2 , the unit buffer circuits BUF 0 e and BUF 15 e corresponding to the unit buffer circuits BUF 0 and BUF 15 farthest from the buffer circuit 10 A are arranged on a side closer to the buffer circuit 20 A, and the unit buffer circuits BUF 7 e and BUF 8 e corresponding to the unit buffer circuits BUF 7 and BUF 8 closest to the buffer circuit 10 A are arranged on a side farther from the buffer circuit 20 A. Therefore, differences in the wiring length of the data bus 52 A among the unit buffer circuits can be decreased. The same holds true for the ODD buffer circuit.

Furthermore, it is preferable that the data bus 51 A that connects the buffer circuit 10 A to the I/O circuit included in the data I/O circuit area 40 A are arranged so as to equalize the wiring distance on the ODD side and the wiring distance on the EVEN side. That is, in a case where a data bus 51 A 0 o coupled to the unit buffer circuit BUF 0 o and a data bus 51 A 0 e coupled to the unit buffer circuit BUF 0 e are laid out in the vicinity as shown in FIG. 4 , the data bus 51 A 0 o is constituted of a section S 1 extending in the X direction and a section S 2 extending in the Y direction, and the data bus 51 A 0 e is constituted of a section S 3 extending in the X direction and a section S 4 extending in the Y direction. It is preferable that the lengths of the section S 2 and the section S 4 are equal to each other. When the section S 2 is extended in the Y direction toward the unit buffer circuit BUF 0 o and the section S 4 is extended in the Y direction toward the unit buffer circuit BUF 0 e , the wiring distances of the data bus 51 A 0 e and 51 A 0 o are substantially equal to each other because the sections S 1 and S 3 are located between the unit buffer circuit BUF 0 o and the unit buffer circuit BUF 0 e . The same holds true for the data bus 51 B that connects the buffer circuit 10 B to the I/O circuit included in the data I/O circuit area 40 B.

Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this disclosure will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosures. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments. Thus, it is intended that the scope of at least some of the present disclosure should not be limited by the particular disclosed embodiments described above.