Three dimension memory device capable of improving sensing accuracy in high-speed data sensing operation

Technology Field

The disclosure relates to a three dimension memory device, and particularly, to a three dimension memory device capable of improving the accuracy of sensing results.

In memory devices, when a high-speed data sensing operation is performed, the bit line voltage cannot be quickly stabilized, so extra offset current often occurs in the sensing path of the sense amplifier. If the load of the bit line is charged when the memory cell is performing the sensing operation, the displacement current (similar to the read current of the memory cell) of up to several microamps may affect the accuracy of the sensing.

The disclosure provides a three dimension memory device capable of improving the accuracy of data reading.

The three dimension memory device of the disclosure includes a memory cell tile, multiple source line switches, multiple first bit line switches, multiple second bit line switches, multiple third bit line switches, and multiple fourth bit line switches. The memory cell tile is divided into a first memory cell sub-tile and a second memory cell sub-tile. The first memory cell sub-tile includes multiple first memory cells, and the second memory cell sub-tile includes multiple second memory cells. Multiple source line switches are commonly coupled to a common source line and respectively coupled to multiple first source lines of the first memory cell sub-tile and multiple second source lines of the second memory cell sub-tile. First bit line switches are commonly coupled to a first global bit line and respectively coupled to multiple first bit lines in a first part of the first memory cell sub-tile. Second bit line switches are commonly coupled to a second global bit line and respectively coupled to multiple second bit lines in a second part of the first memory cell sub-tile. Third bit line switches are commonly coupled to the first global bit line and respectively coupled to multiple third bit lines in a first part of the second memory cell sub-tile. Fourth bit line switches are commonly coupled to the second global bit line and respectively coupled to multiple fourth bit lines in a second part of the second memory cell sub-tile.

In summary, in the three dimension memory device of the disclosure, the memory cell tile is divided into two memory cell sub-tiles. Through different bit line switches corresponding to the memory cell sub-tiles respectively, in the data read operation, the selected memory cells and the unselected memory cell sub-tiles provide reference memory cells to be coupled to the sense amplifier. Accordingly, the load balance on the two input terminals of the sense amplifier can be increased, and the accuracy of data reading can be improved.

FIG. 1 is a schematic view of a three dimension memory device according to an embodiment of the disclosure.

FIG. 2 A and FIG. 2 B are each schematic views of different implementations of the read operation of the three dimension memory device according to the embodiment of the disclosure.

FIG. 2 C is a schematic view illustrating load states of two input terminals in a read operation of a sense amplifier of the three dimension memory device according to the embodiment of the disclosure.

FIG. 3 is a schematic view illustrating a programming operation of a three dimension memory device according to an embodiment of the disclosure.

FIG. 4 is a schematic view illustrating an erase operation of a three dimension memory device according to an embodiment of the disclosure.

FIG. 5 is a three-dimensional structure view of a three dimension memory device according to an embodiment of the disclosure.

FIG. 6 is a schematic view illustrating an implementation of a word line switch of a three dimension memory device according to an embodiment of the disclosure.

FIG. 7 is a schematic view illustrating another implementation of the word line switch of the three dimension memory device according to the embodiment of the disclosure.

Referring to FIG. 1 , FIG. 1 is a schematic view of a three dimension memory device according to an embodiment of the disclosure. A three dimension memory device 100 includes a memory cell tile 101 , source line switches SLT 1 TO SLT 16 , bit line switches BLT 1 a to BLT 16 a , and bit line switches BLT 1 b to BLT 16 b . The memory cell tile 101 can be divided into memory cell sub-tiles 110 and 120 . The memory cell sub-tile 110 includes multiple memory cells MC 1 disposed in a stack, and the memory cell sub-tile 120 includes multiple memory cells MC 2 disposed in a stack. In the embodiment, the memory cell tile 101 may be a three-dimensional stacked AND flash memory block or an NOR flash memory block.

In addition, the memory cell sub-tile 110 can be divided into a first part Pa 1 and a second part Pa 2 . Correspondingly, the memory cell sub-tile 120 can be divided into a first part Pb 1 and a second part Pb 2 .

Multiple first terminals of the source line switches SLT 1 to SLT 16 are commonly coupled to a common source line CSL, and multiple second terminals of the source line switches SLT 1 to SLT 16 are respectively coupled to multiple source lines of the memory cell sub-tile 110 . In addition, the second terminals of the source line switches SLT 1 to SLT 16 are also respectively coupled to multiple source lines of the memory cell sub-tile 120 . That is, the memory cell sub-tiles 110 and 120 can share the source line switches SLT 1 to SLT 16 .

In addition, multiple first terminals of the bit line switches BLT 1 a to BLT 8 a are commonly coupled to a global bit line GBL 1 , and multiple first terminals of the bit line switches BLT 9 a to BLT 16 a are commonly coupled to a global bit line GBL 2 . The bit line switches BLT 1 a to BLT 8 a correspond to the first part Pa 1 of the memory cell sub-tile 110 , and multiple second terminals of the bit-line switches BLT 1 a to BLT 8 a are respectively coupled to multiple bit lines of the first part Pa 1 of the memory cell sub-tile 110 . The bit line switches BLT 9 a to BLT 16 a correspond to the second part Pa 2 of the memory cell sub-tile 110 , and multiple second terminals of the bit-line switches BLT 9 a to BLT 16 a are respectively coupled to multiple bit lines of the second part Pa 2 of the memory cell sub-tile 110 .

In addition, multiple first terminals of the bit line switches BLT 1 b to BLT 8 b are commonly coupled to a global bit line BL 1 , and multiple first terminals of the bit line switches BLT 9 b to BLT 16 b are commonly coupled to a global bit line BL 2 . The bit line switches BLT 1 b to BLT 8 b correspond to the first part Pb 1 of the memory cell sub-tile 120 , and multiple second terminals of the bit line switches BLT 1 b to BLT 8 b are respectively coupled to multiple bit lines of the first part Pb 1 of the memory cell sub-tile 120 . The bit line switches BLT 9 b to BLT 16 b correspond to the second part Pb 2 of the memory cell sub-tile 120 , and multiple second terminals of the bit line switches BLT 9 b to BLT 16 b are respectively coupled to multiple bit lines of the second part Pb 2 of the memory cell sub-tile 120 .

Regarding the positional layout, the first part Pa 1 of the memory cell sub-tile 110 and the second part Pb 2 of the memory cell sub-tile 120 can be opposite to each other and symmetrical about a reference center, the second part Pa 2 of the memory cell sub-tile 110 and the first tile Pb 1 of the memory cell sub-tile 120 may be opposite to each other and symmetrical about the reference center.

Regarding the operation details, when the read operation is performed, if a memory cell in the first part Pa 1 of the memory cell sub-tile 110 is selected as the selected memory cell for reading, the selected memory cell and the corresponding source line switch and the bit line switch can provide a sensing input terminal of the sense amplifier with a first load. Meanwhile, a reference memory cell can be provided in the second tile Pb 2 of the relatively symmetrical memory cell sub-tile 120 . The source line switch and the bit line switch corresponding to the reference memory cell can provide a reference input terminal of the sense amplifier with a second load. The source line switch and the bit line switch corresponding to the reference memory cell and the selected memory cell can have the same circuit structure, so the load between the sensing input terminal and the reference input terminal of the sense amplifier can be balanced, so that the accuracy of the generated sensing results can be improved.

In the read operation, when the selected memory cell is located in the second part Pa 2 of the memory cell sub-tile 110 , the reference memory cell can be located in the first tile Pb 1 of the memory cell sub-tile 120 ; if the selected memory cell is located in the first tile Pb 1 of the memory cell sub-tile 120 , the reference memory cell can be located in the second part Pa 2 of the memory cell sub-tile 110 ; if the selected memory cell is located in the second tile Pb 2 of the memory cell sub-tile 120 , the reference memory cell may be located in the first part Pa 1 of the memory cell sub-tile 110 .

Moreover, in the embodiment, the quantities of the bit line switches BLTla to BLT 16 a , the bit line switches BLT 1 b to BLT 16 b , and the source line switches SLT 1 to SLT 16 are not limited. The quantities shown in FIG. 1 are only for the convenience of description and are not intended to limit the scope of the disclosure.

It should be noted here, in present disclosure, the source line switches SLT 1 to SLT 8 and the source line switches SLT 9 to SLT 16 may be respectively implemented by same eight switches.

Referring to FIG. 2 A and FIG. 2 B , FIG. 2 A and FIG. 2 B are each schematic views of different implementations of the read operation of the three dimension memory device according to the embodiment of the disclosure. The hardware architecture of the three dimension memory device 100 is adopted. In the embodiment, the three dimension memory device 100 further includes a path selector 130 and a sense amplifier SA. The sense amplifier SA has a sensing input terminal SE and a reference input terminal RE. The sensing input terminal SE is configured for receiving a sensed electrical signal, and the reference input terminal RE is configured for receiving a reference signal serving as a sensing standard. The path selector 130 is coupled between the sense amplifier SA and the memory cell sub-tiles 110 and 120 . The path selector 130 includes four switches T 1 -T 4 composed of transistors. Moreover, the switch T 1 is coupled between the global bit line GBL 1 and the reference input terminal RE of the sense amplifier SA; the switch T 2 is coupled between the global bit line GBL 1 and the sensing input terminal SE of the sense amplifier SA; the switch T 3 is coupled between the global bit line GBL 2 and the sensing input terminal SE of the sense amplifier SA; the switch T 4 is coupled between the global bit line GBL 2 and the reference input terminal RE of the sense amplifier SA.

In the embodiment, when a memory cell (a selected memory cell SMC 1 ) in the memory cell sub-tile 110 is selected for the read operation, the position is symmetrical to the selected memory cell SMC 1 , and one memory cell located in the memory cell sub-tile 120 can serve as a reference memory cell RMC 2 . In the read operation, both the source line switch SLT 1 and the bit line switch BLTla corresponding to the selected memory cell SMC 1 are turned on, and both the source line switch SLT 9 and the bit line switch BLT 9 b corresponding to the reference memory cell RMC 2 are also turned on. In addition, the word line corresponding to the selected memory cell SMC 1 receives a read voltage Vread and allows the selected memory cell SMC 1 to provide a read signal according to the stored data. The word line of the reference memory cell RMC 2 receives a reference ground voltage (0 volts), for example, and is in a turned-off state.

In the read operation, the switches T 1 and T 3 are cut off, and the switches T 2 and T 4 are turned on. The global bit line GBL 1 can be coupled to the sensing input terminal SE of the sense amplifier SA through the switch T 2 , and the global bit line GBL 2 can be coupled to the reference terminal RE of the sense amplifier SA through the switch T 4 .

Furthermore, in the embodiment, the bit line switches BLT 1 b and BLT 9 a are cut off. At the same time, other bit line switches BLT 2 a to BLT 8 a , BLT 10 a to BLT 16 a , BLT 2 b to BLT 8 b and BLT 10 b to BLT 16 b are all in a cut-off state.

Referring to FIG. 2 C , FIG. 2 C is a schematic view illustrating load states of two input terminals in a read operation of a sense amplifier of the three dimension memory device according to the embodiment of the disclosure. Under the premise that the bit line switches BLT 1 a and BLT 9 b and the source line switches SLT 1 and SLT 9 are the same circuit elements, the load difference between the sensing input terminal SE of the sense amplifier SA and the reference input terminal RE is only related to the data storage state of the selected memory cell SMC 1 . Therefore, the sense amplifier SA can sense accurate sensing results according to the signals on the sensing input terminal SE and the reference input terminal RE.

Referring to FIG. 2 B , in the embodiment, when another part of the memory cell (the selected memory cell SMC 2 ) in the memory cell sub-tile 110 is selected for the read operation, the position is symmetrical to the selected memory cell SMC 2 , and the memory cell located in the memory cell sub-tile 120 can serve as a reference memory cell RMC 3 . In the read operation, both the source line switch SLT 9 and the bit line switch BLT 9 a corresponding to the selected memory cell SMC 2 are turned on, and both the source line switch SLT 1 and the bit line switch BLT 1 b corresponding to the reference memory cell RMC 3 are also turned on. In addition, the word line corresponding to the selected memory cell SMC 2 receives the read voltage Vread and allows the selected memory cell SMC 2 to provide a read signal according to the stored data. The word line of the reference memory cell RMC 3 receives the reference ground voltage (0 volts), for example, and is in a turned-off state.

In the read operation, the switches T 2 and T 4 are cut off, and the switches T 1 and T 3 are turned on. The global bit line GBL 1 can be coupled to the reference terminal RE of the sense amplifier SA through the switch T 1 , and the global bit line GBL 2 can be coupled to the sensing terminal SE of the sense amplifier SA through the switch T 3 .

Furthermore, in the embodiment, the bit line switches BLT 9 b and BLT 1 a are cut off. At the same time, other bit line switches BLT 2 a to BLT 8 a , BLT 10 a to BLT 16 a , BLT 2 b to BLT 8 b and BLT 10 b to BLT 16 b are all in a cut-off state.

In the subsequent paragraphs, referring to FIG. 3 , FIG. 3 is a schematic view illustrating a programming operation of a three dimension memory device according to an embodiment of the disclosure. The hardware architecture of the three dimension memory device 100 is adopted. The three dimension memory device 100 further includes page buffers 141 and 142 and switches T 5 and T 6 . The page buffers 141 and 142 are respectively connected to the global bit lines GBL 1 and GBL 2 through the switches T 5 and T 6 composed of transistors.

When the programming operation is performed, the switches T 1 -T 4 in the path selector 130 are all cut off, so that the global bit lines GBL 1 and GBL 2 and the sense amplifier SA are electrically isolated from one another. The switches T 5 and T 6 are turned on, so that data PD 1 and PD 2 respectively received by the page buffers 141 and 142 are transmitted to the global bit lines GBL 1 and GBL 2 respectively. Furthermore, when the three dimension memory device 100 performs the read operation, the switches T 5 and T 6 can be cut off.

In addition, if two parts of the memory cells (the selected memory cells SMC 3 and SMC 4 ) in the memory cell sub-tile 110 are selected to perform the programming operation, both the bit line switch BLT 1 a corresponding to the selected memory cell SMC 3 and the bit line switch BLT 9 a corresponding to the selected memory cell SMC 4 are turned on. Meanwhile, the source line switches SLT 1 and SLT 9 are cut off, and the corresponding bit line switches BLT 1 b and BLT 9 b can also be turned on.

Meanwhile, the word line (the same word line) of the selected memory cells SMC 3 and SMC 4 can receive a programming voltage VPGM and allow the selected memory cells SMC 3 and SMC 4 to perform the programming operation according to the data PD 1 and PD 2 on the global bit lines GBL 1 and GBL 2 .

In addition, to prevent the unselected memory cells from being disturbed by the programming operation, the word lines to which the remaining memory cells other than the selected memory cells SMC 3 and SMC 4 are coupled can receive the reference ground voltage (e.g., 0 volts).

In the embodiment, the circuit structures of the page buffers 141 and 142 can be implemented by using a page buffer circuit well known to those skilled in the art in the memory field, which is not limited in the disclosure.

In the programming operation of the embodiment, multiple selected memory cells can be written at one time, which is one of the implementations of page programming.

In the subsequent paragraphs, referring to FIG. 4 , FIG. 4 is a schematic view illustrating an erase operation of a three dimension memory device according to an embodiment of the disclosure. The hardware architecture of the three dimension memory device 100 is adopted as well. In the embodiment, the erase operation is a tile erase operation. When the erase operation is performed, the bit line switches BLT 1 a to BLT 16 a and the bit line switches BLT 1 b to BLT 16 b are all turned on, the source line switches SLT 1 to SLT 16 are also turned on, and voltages with 4 volts to 6 volts are provided to bit lines and source lines of all the memory cells. In the example in which the memory cell sub-tile 110 is the selected tile (the memory cell sub-tile 120 is not erased) for performing the erase operation, the word lines of the memory cell sub-tile 110 may each receive an erase voltage (e.g., −6 volts to −8 volts), and the word lines of the memory cell sub-tile 120 may each receive an erase mask voltage (e.g., 4.5 volts).

It should be noted here, in present disclosure, the source line switches SLT 1 to SLT 8 and the source line switches SLT 9 to SLT 16 may be respectively implemented by same eight switches.

Note that according to the embodiments illustrated in FIG. 1 to FIG. 4 , in the three dimension memory device 100 of the disclosure, the on and off states of the bit line switches BLT 1 b to BLT 8 b and the bit line switches BLT 9 a to BLT 16 a are the same respectively in any operation mode. The on and off states of the bit line switches BLTla to BLT 8 a and the bit line switches BLT 9 b to BLT 16 b are the same respectively in any operation mode. That is, the bit line switches BLT 1 b to BLT 8 b and the bit line switches BLT 9 a to BLT 16 a can share the same eight driving signals, and the bit line switches BLT 1 a to BLT 8 a and the bit line switches BLT 9 b to BLT 16 b can also share other eight driving signals. Accordingly, in the three dimension memory device 100 according to the embodiment of the disclosure, the quantity of the driving signals for controlling the bit line switches BLT 1 a to BLT 16 b can be decreased by half, thereby effectively reducing the layout area of the circuit.

In the subsequent paragraphs, referring to FIG. 5 , FIG. 5 is a three-dimensional structure view of a three dimension memory device according to an embodiment of the disclosure. A three dimension memory device 500 includes memory cell sub-tiles 510 and 520 . The memory cell sub-tile 510 includes multiple word line structures SCWL 1 stacked in a staircase shape, and the memory cell sub-tile 520 includes multiple word line structures SCWL 2 stacked in a staircase shape. Layout areas 511 and 521 are disposed between the memory cell sub-tiles 510 and 520 for configuring bit line switches. The layout areas 511 and 521 are disposed between the memory cell sub-tiles 510 and 520 in sequence. In addition, a layout area 530 with source line switches is disposed on a side of the memory cell sub-tile 520 not adjacent to the layout areas 511 and 521 . The layout areas 511 and 521 are configured for disposing multiple bit line switches corresponding to the memory cell sub-tiles 510 and 520 respectively, and the layout area 530 is configured for disposing multiple source line switches shared by the memory cell sub-tiles 510 and 520 .

In the subsequent paragraphs, referring to FIG. 6 , FIG. 6 is a schematic view illustrating an implementation of a word line switch of a three dimension memory device according to an embodiment of the disclosure. In the embodiment, each memory cell sub-tile having 16 bit lines is illustrated as an example. The three dimension memory device has multiple bit line switches BLT 1 a to BLT 16 a corresponding to the first memory cell sub-tile and multiple bit line switches BLT 1 b to BLT 16 b corresponding to the first memory cell sub-tile. The bit line switches BLT 1 a to BLT 16 a are arranged in an array and respectively coupled to the 16 bit line drivers 601 a to 616 a . The bit line switches BLT 1 b to BLT 16 b are arranged in an array and respectively coupled to the 16 bit line drivers 601 b to 616 b.

The bit line drivers 601 a to 616 a and the bit line drivers 601 b to 616 b correspond to the bit line switches BLT 1 a to BLT 16 a and the bit line switches BLT 1 b to BLT 16 b one-to-one, respectively, and the on and off states of the bit line switches BLT 1 a to BLT 16 a and the bit line switches BLT 1 b to BLT 16 b are controlled by the generated driving signal.

In the subsequent paragraphs, referring to FIG. 7 , FIG. 7 is a schematic view illustrating another implementation of the word line switch of the three dimension memory device according to the embodiment of the disclosure. According to the foregoing implementation, in the three dimension memory device of the disclosure, the on and off states of the bit line switches have correspondence. That is, in the three dimension memory device of the embodiment of the disclosure, the on and off states of the bit line switches in the first part of the first sub-memory cells are the same as the on and off states of the bit-line switches in the second part of the second sub-memory cells. The on and off states of the bit line switches in the second part of the first sub-memory cells are the same as the on and off states of the bit line switches in the first part of the second sub-memory cells. Therefore, by adjusting the layout positions of the bit line switches BLT 1 a to BLT 16 a and the bit line switches BLT 1 b to BLT 16 b , driving lines DL corresponding to the symmetrical bit line switches are disposed symmetrically with respect to a reference axis RAX.

In addition, the three dimension memory device of the embodiment of the disclosure also has multiple bridge lines CW. The bridge line CW is configured for connecting the two driving lines DL symmetrical to the reference axis RAX to each other and for transmitting the same driving signal.

With such a configuration, the quantity of the bit line drivers 701 to 716 can be decreased by half, which effectively saves the area required for the circuit layout and the power consumption of the three dimension memory device.

In summary, in the three dimension memory device of the disclosure, the memory cell tile is divided into two memory cell sub-tiles. In addition, when the read operation is performed, relatively symmetrical selected memory cells and reference memory cells are coupled to the sense amplifier, so that the loads of the reference input terminal and the sensing input terminal of the sense amplifier can be balanced to improve the accuracy of sensing results.