Communication method and communication device

1. Technical Field

The present disclosure relates to a digital communication field. More specifically, the present disclosure relates to bit interleavers and bit de-interleavers in a bit-interleaved coding and modulation (BICM) system using quasi-cyclic low-density parity-check codes (QC LDPC codes) and quadrature amplitude modulation (QAM).

2. Description of the Related Art

In these years, a lot of transmitters are proposed, and in the transmitters, bit interleavers are disposed between encoders that encode information bits and output codeword bits, and constellation mappers that map the codeword bits to constellations and that output modulation symbols (for example, refer to PTL1).

Patent Literature

PTL 1: EP 11006087.8

Non-Patent Literature

NPL 1: DVB-S2 standard: ETSI EN 302 307, V1.2.1 (August, 2009)

In one general aspect, the techniques disclosed here feature a communication method including executing a cyclic block permutation for a codeword generated based on a quasi-cyclic low-density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the codeword includes a sequence of N cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword, mapping each of the bits of the codeword for which the cyclic block permutation is executed to any one of constellation points of a non-uniform constellation, and transmitting the mapped codeword. In the communication method, the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword, in a case where the code rate of the quasi-cyclic low-density parity-check code is equal to 7/15, the cyclic block permutation is defined according to Table 3.

Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and/or advantages may be individually obtained by the various embodiments and features of the specification and drawings, which need not all be provided in order to obtain one or more of such benefits and/or advantages.

It should be noted that general or specific embodiments may be implemented as a system, a method, an integrated circuit, a computer program, a storage medium, or any selective combination thereof.

FIG. 1 is a block diagram illustrating one configuration example of a transmitter including general bit-interleaved coding and modulation (BICM);

FIG. 2 is a block diagram illustrating one configuration example of a BICM encoder of FIG. 1 ;

FIG. 3 is a diagram illustrating one example of a parity-check matrix of a quasi-cyclic low-density parity-check code with M=6, N=18, Q=8;

FIG. 4 is a diagram illustrating one example of a table that defines repeat-accumulate quasi-cyclic low-density parity-check codes;

FIG. 5 is a diagram illustrating an information part of the parity-check matrix for a first bit in each cyclic block of the information part for the repeat-accumulate quasi-cyclic low-density parity-check codes of FIG. 4 ;

FIG. 6 is a diagram illustrating a full parity-check matrix including entries for all information bits and a staircase parity part for the parity-check matrix of FIG. 5 ;

FIG. 7 is a diagram illustrating a matrix representing quasi-cyclic structure of the parity-check matrix of FIG. 6 ;

FIG. 8 A is a diagram illustrating a 4-QAM constellation;

FIG. 8 B is a diagram illustrating a 16-QAM constellation;

FIG. 8 C is a diagram illustrating a 64-QAM constellation;

FIG. 9 A is a block diagram illustrating configuration of a 4-QAM mapper;

FIG. 9 B is a block diagram illustrating configuration of a 16-QAM mapper;

FIG. 9 C is a block diagram illustrating configuration of a 64-QAM mapper;

FIG. 10 is a schematic view for illustrating different robustness levels in an 8-PAM symbol using Gray encoding;

FIG. 11 is a diagram illustrating one example of a 4096-QAM constellation based on 1 D-64 NU-PAM designed for a specific SNR;

FIG. 12 A is a diagram for illustrating one example of the BICM encoder of FIG. 2 based on DVB-NGH;

FIG. 12 B is a diagram for illustrating one example of the BICM encoder of FIG. 2 based on DVB-NGH;

FIG. 12 C is a diagram for illustrating one example of the BICM encoder of FIG. 2 based on DVB-NGH;

FIG. 13 A is a diagram for illustrating one example of the BICM encoder of FIG. 2 based on ATSC 3.0;

FIG. 13 B is a diagram for illustrating one example of the BICM encoder of FIG. 2 based on ATSC 3.0;

FIG. 13 C is a diagram for illustrating one example of the BICM encoder of FIG. 2 based on ATSC 3.0; and

FIG. 14 is a block diagram illustrating one configuration example of a bit interleaver according to an exemplary embodiment of the present disclosure.

<<Items Confirmed Until the Inventors have Achieved the Present Disclosure>>

FIG. 1 is a block diagram illustrating one configuration example of a transmitter including general bit-interleaved coding and modulation (BICM).

Transmitter 100 illustrated in FIG. 1 includes input processing unit 110 , BICM encoder 120 , orthogonal frequency-division multiplexing (OFDM) modulator 130 , up-converter 140 , radio frequency (RF) amplifier 150 , and antenna 160 .

Input processing unit 110 formats input-bit-streams into blocks of a determined length called baseband frames. BICM encoder 120 converts the baseband frames into data-streams including a plurality of complex values. OFDM modulator 130 uses, for example, OFDM modulation, and typically performs time interleaving and frequency interleaving for improving diversity. Up-converter 140 converts digital baseband signals into analog RF signals. RF amplifier 150 performs power amplification of the analog RF signals, and outputs the analog RF signals to antenna 160 .

FIG. 2 is a block diagram illustrating one configuration example of BICM encoder 120 of FIG. 1 .

BICM encoder 120 illustrated in FIG. 2 includes low-density parity-check (LDPC) encoder 121 , bit interleaver 122 , and quadrature amplitude modulation (QAM) mapper 124 .

LDPC encoder 121 encodes input blocks, that is, the baseband frames, and outputs LDPC codewords to bit interleaver 122 . Bit interleaver 122 permutates bits of each LDPC codeword, and then QAM mapper 124 maps the bits of each LDPC codeword to complex cells. QAM mapper 124 maps the permutated bits of each LDPC codeword to the complex cells by using QAM.

Each component of BICM encoder 120 in FIG. 2 will be described in more detail below.

First, LDPC encoder 121 will be described.

LDPC encoder 121 encodes the baseband frames by using a specific LDPC code. The present disclosure is particularly designed for LDPC block codes having staircase parity structure which is employed in the DVB-S2, DVB-T2, DVB-C2 standards, and for variations of Raptor-like LDPC codes. More details will be described below.

The LDPC block code is a linear error-correcting code that is fully defined by its parity-check matrix (PCM). This PCM is a binary sparse matrix representing connection of the codeword bits (also referred to as bit nodes or variable nodes) to parity checks (also referred to as check nodes). Columns and rows of the PCM correspond to the variable nodes and check nodes, respectively. Connection of the variable nodes to the check nodes are represented by “1” entries in the PCM matrix.

Quasi-cyclic low-density parity-check (QC LDPC) codes have structure especially suitable for hardware implementation. In fact, most if not all standards today use the QC LDPC codes. The PCM of such a QC LDPC code has special structure having cyclic matrices (or also referred to as cyclic). The cyclic matrix is a square matrix in which each row is a cyclic shift of a previous row by one matrix element, and may have one or more folded diagonals.

A size of each cyclic matrix is Q×Q (Q rows and Q columns), and Q is referred to as a cyclic factor of the QC LDPC code. This quasi-cyclic structure makes it possible to process Q check nodes in parallel. Therefore, the quasi-cyclic structure is clearly advantageous for efficient hardware implementation.

The PCM of a QC LDPC code is a matrix having Q×M rows and Q×N columns, and the codewords each include N blocks including Q bits. In addition, M is a number of blocks in a parity part. Note that a Q-bit block is referred to as a quasi-cyclic block or simply a cyclic block throughout this document, and is abbreviated as QB.

FIG. 3 is a diagram illustrating one example of the PCM of the QC LDPC code with M=6, N=18, Q=8. The PCM includes cyclic matrices having one or two folded diagonals. This QC LDPC code encodes a block of 8×12=96 bits to a codeword of 8×18=144 bits, and thus a code rate is 2/3. Note that in FIG. 3 , FIG. 5 to FIG. 7 , a black square is a matrix element of a value “1,” and a white square is a matrix element of a value “0.”

The QC LDPC code with the PCM illustrated in FIG. 3 belongs to a special family of QC LDPC codes referred to as repeat-accumulate quasi-cyclic low-density parity-check (RA QC LDPC) codes. The RA QC LDPC codes are known for ease of encoding, and are employed in a very large number of standards such as the second generation DVB standards (DVB-S2, DVB-T2, DVB-C2).

Next, the following describes definition of the RA QC LDPC codes used in the standard family of DVB-S2, DVB-T2, DVB-C2, as described in Section 5.3.2 and Appendixes B and C of NPL1 of the DVB-S2 standard (DVB-S2 standard: ETSI EN 302 307: V1.2.1 (August, 2009)). In this standard family, cyclic factor Q is equal to 360.

Each LDPC code is fully defined by a table containing, for a first bit of each cyclic block in an information part, indices of each check node to which the first bit is connected. Note that the indices of each check node start with zero. These indices are referred to as “addresses of the parity bit accumulators” in the DVB-S2 standard. FIG. 4 illustrates the table for the LDPC code one example of which is illustrated in FIG. 3 .

FIG. 5 is a diagram illustrating the information part of the PCM for a first bit in each cyclic block of the information part for the RA QC LDPC code of FIG. 4 .

The full PCM includes entries for all information bits and the staircase parity part, and is illustrated in FIG. 6 .

For each bit other than the first bit of each cyclic block in the information part, the indices of each check node to which the bit is connected are calculated by Equation 1 described below.

where q is a bit index (0, . . . , Q−1) within one cyclic block, i q is a check node index for bit q, and i 0 is one of the check nodes to which the first bit of the cyclic block in the table of FIG. 4 is connected. M is a number of cyclic blocks in the parity part, and is 6 in the example of FIG. 6 , and Q is a number of bits of one cyclic block and is 8 in the example of FIG. 6 . Q×M is a number of parity bits, and is 8×6=48 in the example of FIG. 6 . % is a modulo operator. Note that for example, for the cyclic block QB of “1,” calculation by Equation 1 described above is performed on each of i 0 =13, 24, 27, 31, 47 in the case of FIG. 4 .

In order to represent the quasi-cyclic structure of the PCM in FIG. 6 , a permutation expressed by Equation 2 described below is applied to the rows of the PCM in FIG. 6 , and this application of the permutation results in the matrix illustrated in FIG. 7 .

where i and j are indices starting with zero. i is an index of the check nodes before permutation, and j is an index of the check nodes after permutation. M is a number of cyclic blocks in the parity part, and is 6 in the example of FIG. 6 , and Q is a number of bits of one cyclic block, and is 8 in the example of FIG. 6 . % is a modulo operator, and floor(x) is a function that outputs a maximum integer equal to or less than X.

Since this permutation by Equation 2 is not applied to the bits, code definition is not changed. However, the parity part of the PCM resulting from this permutation by Equation 2 is not quasi-cyclic. In order to make the parity part quasi-cyclic, a special permutation expressed by Equation 3 described below is applied to the parity bits.

where i and j are indices starting with zero, i is an index of the parity bits before permutation, and j is an index of the parity bits after permutation. M is a number of cyclic blocks in the parity part, and is 6 in the example of FIG. 7 , and Q is a number of bits of one cyclic block, and is 8 in the example of FIG. 7 . % is a modulo operator, and floor(x) is a function that outputs a maximum integer equal to or less than x.

This permutation by Equation 3 applied to the parity bits changes the code definition.

Note that the permutation by Equation 3 applied to the parity bits is referred to as a parity permutation or parity interleaving throughout this document. However, the parity permutation or the parity interleaving will be regarded as part of the LDPC encoding process hereinafter.

The next-generation ATSC 3.0 standard for terrestrial reception of digital video service is currently under development, and will define 1/15, 2/15, . . . , 13/15 as code rates, and 16200 code bits and 64800 code bits as code lengths.

Next, QAM mapper 124 will be described.

QAM mapper 124 maps the bit of the codeword to one point of a plurality of points in a QAM constellation by independently modulating real components and imaginary components by using pulse-amplitude modulation (PAM). Each point in the QAM constellation corresponds to one combination of the bits. FIG. 8 A to FIG. 8 C are diagrams illustrating three types of QAM constellations relevant to the present disclosure, a 4-QAM constellation, a 16-QAM constellation, and a 64-QAM constellation.

Here, the real components and the imaginary components use the same type of PAM. The real components and the imaginary components use 2-PAM, 4-PAM, 8-PAM in the 4-QAM constellation, the 16-QAM constellation, and the 64-QAM constellation, respectively.

The present disclosure also assumes that the PAM mapping uses Gray encoding, as illustrated from FIG. 8 A to FIG. 8 C .

FIG. 9 A , FIG. 9 B , FIG. 9 C are blocks illustrating configurations of the QAM mappers corresponding to the constellations of FIG. 8 A , FIG. 8 B , FIG. 8 C , respectively. 4-QAM mapper 124 A of FIG. 9 A includes two independent 2-PAM mappers 124 A- 1 , 124 A- 2 each of which encodes one bit. 16-QAM mapper 124 B of FIG. 9 B includes two independent 4-PAM mappers 124 B- 1 , 124 B- 2 each of which encodes two bits. 64-QAM mapper 124 C of FIG. 9 C includes two independent 8-PAM mappers 124 C- 1 , 124 C- 2 each of which encodes three bits.

The bits encoded in a PAM symbol have different robustness levels, in other words, different reliability when the PAM symbol received in a receiver is demapped. This is a well known fact, and FIG. 10 illustrates a schematic view for illustrating the different robustness levels in an 8-PAM symbol using Gray encoding.

The different robustness levels result from a fact that a distance between a portion with a bit value of zero and a portion with a bit value of one is different for each of three bits b 1 , b 2 , b 3 . The reliability of a bit is proportional to an average distance between the portion with a bit value of zero and the portion with a bit value of one. In the example illustrated in FIG. 10 , bit b 1 has lowest reliability, bit b 2 has second lowest reliability, and bit b 3 has highest reliability.

In order to increase a transmission rate of bits, that is, BICM capacity, non-uniform constellations have been introduced in the DVB-NGH standard, which is the first time. This increase is achieved by changing an interval between PAM constellation points, and so-called 1D-NU-PAMs are obtained. Next, a square non-uniform constellation is obtained from the 1D-NU-PAMs.

In ATSC 3.0, this idea is further improved by introducing two-dimensional non-uniform constellations, so-called 2D-NUCs. The 2D-NUCs involve increased demapping complexity at the receiver because An in-phase (I)-component and a quadrature (Q)-component of the received complex cells are dependent on each other. Higher demapping complexity is considered acceptable in ATSC 3.0 up to a constellation order of 1024. Moreover, constellations based on PAM for 4096-QAM constellations are determined to be allowed. FIG. 11 illustrates one example of a 4096-QAM constellation based on 1D-64 NU-PAM.

A number of bits in the QAM symbol is represented by B. Since the QAM constellations are square, B is an even number. Further, since a square QAM symbol includes two PAM symbols of the same type, the bits encoded in the QAM symbol can be grouped into pairs having the same robustness levels. The bits encoded in the QAM symbol are referred to as a constellation word.

Next, bit interleaver 122 will be described.

Typically, the bits of an LDPC codeword have different importance levels, and the bits of a constellation have different robustness levels. Direct, that is, non-interleaved mapping of the LDPC codeword bits to the QAM constellation bits does not achieve optimal performance. In order to prevent such performance reduction, the codeword bits need to be interleaved before the codeword bits are mapped to constellations.

For this purpose, bit interleaver 122 is provided between LDPC encoder 121 and QAM mapper 124 , as illustrated in FIG. 2 . Careful designing of bit interleaver 122 can achieve an optimal relationship between the bits of the LDPC codeword and the bits encoded by the constellation, and leads improved performance. Typically, evaluation criterion of the performance is a bit error rate (BER) or a frame error rate (FER) as a function of a signal-to-noise ratio (SNR).

The different importance levels of the bits of an LDPC codeword result firstly from a fact that a number of parity checks (check nodes) is different in some of the bits. The larger the number of the parity checks (check nodes) connected to a codeword bit (variable node) is, the more important the bit is in iterative LDPC decoding processing.

Further, the different importance levels of the bits of the LDPC codeword results secondly from a fact that the variable nodes have different connectivity to the cycles in the Tanner graph representation of the LDPC code. Thus, the importance levels of the bits may be different even when the number of the parity checks (check nodes) connected to the codeword bits of the LDPC codeword is the same number in each of the bits.

These ideas are well known in the art. As a general rule, the larger the number of the check nodes connected to a variable node is, the larger the importance level of the variable node is.

Particularly, in the case of QC LDPC codes, all bits included in a cyclic block of Q bits have the same importance level because the number of the parity checks (check nodes) connected to each of the bits is the same number, and connectivity to the cycles in the Tanner graph representation is the same.

Next, a method for mapping the bits of a QC LDPC codeword to constellation words will be described. This mapping is performed by bit interleaver 122 in FIG. 2 . Note that this method for mapping is disclosed in PTL1 (EP11006087.8), which is incorporated herein by reference in its entirety. While PTL1 (EP11006087.8) relates to a case where a number of transmission antennas is any number T, the following describes a case relevant to the present disclosure, that is, a case where number of transmission antennas T is one.

According to PTL1 (EP11006087.8), the bits of a QC LDPC codeword are mapped to constellation words such that

(i) each constellation word is made of bits in B/2 cyclic blocks of the QC LDPC codeword, and

(ii) each pair of constellation word bits that are encoded in the same QAM symbol and that have the same robustness level is made of bits in the same cyclic block.

Particularly, the Q×B/2 bits of the B/2 cyclic blocks are mapped to Q/2 spatial-multiplexing blocks. In this case, the B/2 cyclic blocks are referred to as a section.

FIG. 12 A to FIG. 12 C are diagrams for illustrating one example of BICM encoder 120 of FIG. 2 .

FIG. 12 A illustrates arrangement of 24 cyclic blocks with four sections. In the example of FIG. 12 A , a number of cyclic blocks per section is B/2=12/2=6.

FIG. 12 B is a diagram illustrating one example of structure of a pathway from bit interleaver 122 to QAM mapper 124 (including one pair of PAM mappers 124 - 1 , 124 - 2 ) in BICM encoder 120 in FIG. 2 based on DVB-NGH.

The LDPC codeword generated by LDPC encoder 121 in FIG. 2 is fed to bit interleaver 122 in FIG. 12 B . Bit interleaver 122 is six cyclic blocks per section. Note that processing is performed by bit interleaver 122 and QAM mapper 124 in FIG. 12 B (a pair of PAM mappers 124 - 1 , 124 - 2 are included) for each section in FIG. 12 A . Bit interleaver 122 permutates the fed bits, and then arranges the permutated bits to the real part and the imaginary part of the corresponding constellation words. The pair of PAM mappers 124 - 1 , 124 - 2 map bits (b 1, Re , b 2, Re , . . . , b 6, Re ) to a real component (Re) of complex symbol s 1 , and map bits (b 1, Im , b 2, Im , . . . , b 6, Im ) to an imaginary component (Im) of complex symbol s 1 by using the 64-PAM constellation.

FIG. 12 C is a diagram for illustrating bit permutation executed by bit interleaver 122 in FIG. 12 B . As illustrated in FIG. 12 C , bit interleaver 122 executes processing equivalent to writing all bits of one section of the codeword row-by-row in a matrix, and to reading the written bits column-by-column from the matrix. Note that this matrix is of B/2 rows and Q columns.

FIG. 13 A to FIG. 13 C are diagrams for illustrating other examples of BICM encoder 120 of FIG. 2 . FIG. 13 A to FIG. 13 C are similar to FIG. 12 A to FIG. 12 C , respectively, except that FIG. 13 A to FIG. 13 C illustrate the arrangement based on ATSC 3.0.

FIG. 13 A illustrates arrangement of 24 cyclic blocks with two sections. Unlike the case of FIG. 12 A , in the example of FIG. 13 A , a number of cyclic blocks per section is bit number B of the QAM symbol, and is 12 in the example of FIG. 13 A .

FIG. 13 B is a diagram illustrating one example of structure of a pathway from bit interleaver 122 to QAM mapper 124 of BICM encoder 120 in FIG. 2 based on ATSC 3.0.

The LDPC codeword generated by LDPC encoder 121 in FIG. 2 is fed to bit interleaver 122 in FIG. 13 B . Bit interleaver 122 is 12 cyclic blocks per section. Note that processing is performed by bit interleaver 122 and QAM mapper 124 in FIG. 13 B for each section of FIG. 13 A . Bit interleaver 122 permutates the fed bits. QAM mapper 124 maps bits (b 0 , b 1 , . . . , b 11 ) to complex symbol s 1 by using the 4096-QAM constellation.

FIG. 13 C is a diagram for illustrating bit permutation executed by bit interleaver 122 in FIG. 13 B . As illustrated in FIG. 13 C , bit interleaver 122 executes processing equivalent to writing all bits of one section of the codeword row-by-row in a matrix, and to reading the written bits column-by-column from the matrix. Note that this matrix is of B rows and Q columns.

Exemplary Embodiment

As described above, the different cyclic block of a determined LDPC code may have a different importance level because the importance level of a bit is dependent on the number of check nodes connected to the bit. Thus, improvement in transmission performance may be achieved by matching the importance level of the cyclic block with robustness of the bit of the constellation word to which this cyclic block is mapped. Particularly, the bit of the cyclic block with the highest importance level is mapped to the bit of the constellation word with the strongest robustness. Conversely, the bit of the cyclic block with the lowest importance level is mapped to the bit of the constellation word with the weakest robustness.

FIG. 14 is a block diagram illustrating one configuration example of the bit interleaver according to an exemplary embodiment of the present disclosure. In the example of FIG. 14 , the LDPC codeword includes N=12 cyclic blocks QB 1 , QB 2 , . . . , QB 12 which each include Q=8 bits.

In the bit interleaver, in order to permutate the cyclic blocks within the codeword without affecting a sequence of the bits within each cyclic block in a first stage, a cyclic block permutation (QB permutation) is executed for the codeword. This processing in the first stage is performed by cyclic block permutation unit 210 .

In a second stage, in order to permutate the bits within the cyclic blocks, an intra-cyclic block permutation (intra-QB permutation) is executed for the cyclic blocks. This processing in the second stage is executed by intra-QB permutation units 220 - 1 to 220 - 12 . Note that the second stage may not exist.

In a third stage, after the first stage and the second stage are executed, the bits of each cyclic block of the codeword are mapped to the constellation word. This third stage can be implemented by dividing the codeword into a plurality of sections and performing mapping to the constellation word for each section (section permutation). For example, the third stage is realized by disposing an interleaver (section interleaver) that has a function equivalent to bit interleaver 122 described with reference to FIG. 13 A to FIG. 13 C , in a subsequent stage of the intra-QB permutation unit.

The inventors have found that improvement in communication performance for a determined LDPC code is achieved by optimizing the cyclic block permutation, that is, by selecting the cyclic block permutation that matches the constellation bits of different reliability with the cyclic blocks of different importance levels.

However, the mapping of the cyclic blocks to the constellation word bits is not straightforward. Since no analytical solution has been known so far, finding an optimized cyclic block permutation is very time-consuming work. A method used for finding the optimal cyclic block permutation disclosed in the present disclosure includes the following steps, and is applied to each of different constellations and different code rates.

In a preliminary step, a very huge number (1e4, . . . , 1e5) of cyclic block permutations are generated randomly under no constraint. Monte-Carlo simulations are executed for these cyclic block permutations by using blind demapping and iterative demapping in order to determine a threshold signal-to-noise ratio (SNR) at a determined target value of a block error rate (BLER). The cyclic block permutation with the lowest threshold SNR, that is, with the best performance is kept.

The inventors have found that optimization of the cyclic block permutation for the blind demapping does not result in optimal performance in the iterative demapping, and vice versa. It remains as a challenging task to find a cyclic block permutation that achieves good performance for both the blind demapping and the iterative demapping.

Thus, cyclic block permutations that achieve good performance for both the blind demapping and the iterative demapping are presented.

An SNR range for various cyclic block permutations is determined from the preliminary step. Then, the threshold SNR is set in order to select only cyclic block permutations that achieve good performance for the blind demapping. The good performance means a low SNR. The threshold SNR should not be set too low. This is because the too low threshold SNR leads to exclusion of many cyclic block permutations that achieve very good performance for the iterative demapping. On the other hand, when the cyclic block permutation that is strictly optimized for the blind demapping is used for the iterative demapping, performance becomes poor. It is a question of experience to select the initial threshold SNR appropriately.

In a first selection step, a large number of cyclic block permutations are generated randomly under no constraint. A BLER curve regarding the blind demapping is determined for each cyclic block permutation by using Monte-Carlo simulations, for example. Only the cyclic block permutations with the SNR at the BELR target value being lower than a determined threshold SNR is kept. The BLER curve regarding the iterative demapping is determined for the kept cyclic block permutations, and the best cyclic block permutation is kept.

In a second selection step, a medium number of cyclic block permutations determined from the cyclic block permutation selected in the first selection step is generated randomly under a constraint. Then, a selection criterion in the first selection step is applied. The constrained cyclic block permutations are determined by application of a random permutation to the cyclic block of one section randomly selected. The application of such a constraint ensures that changes in performance are small and concentrated around the good-performance cyclic block permutation that has already selected in the first selection step. The good-performance cyclic block permutation can be found by this method more effectively than by using blind unconstrained search.

In a third selection step, the medium number of cyclic block permutations determined from the cyclic block permutation selected in the second selection step is generated randomly under a constraint. Then, the selection criterion in the first selection step is applied. The constrained cyclic block permutations are determined by application of random permutations to the bits having the same robustness level. Thus, changes in performance are very small and affect the iterative demapping more than the blind demapping. Accordingly, the performance regarding the iterative demapping is optimized without scarification of the performance regarding the blind demapping.

The inventors have carried out optimization of the cyclic block permutations for each of the code rates 6/15, 7/15, 8/15. In addition, simultaneously with the optimization of the cyclic block permutations, the inventors have determined the optimal non-uniform constellation to be used together with the code rates 6/15, 7/15, 8/15. The following describes QB permutations and non-uniform constellations optimized for each of the code rates 6/15, 7/15, 8/15.

Table 1 and Table 2 are tables illustrating the cyclic block permutations and non-uniform 64-PAM constellations that constitute non-uniform 4096-QAM constellations according to the present disclosure when the code rate is 6/15, respectively.

However, in Table 1, and in Table 3 and Table 5 described below, the indices of the cyclic blocks start with zero and end with 179. “j-th block of Group-wise Interleaver Output” indicates the index of the cyclic block within the codeword after the cyclic blocks are permutated. In addition, “n(j)-th block of Group-wise Interleaver Input” indicates the index of the cyclic block within the codeword before the cyclic blocks are permutated. In addition, in Table 2, and in Table 3 and Table 5 described below, address label x starts with zero and ends with 63. Regarding “Address Label x (integer, MSB first),” an address label of the most significant bit (MSB) of the bits is “0,” and an address label of the next bit of the most significant bit is “1.” “PAM spots p(x)” indicates the real value of the PAM symbol corresponding to the address label.

Table 3 and Table 4 are tables illustrating the cyclic block permutations and the non-uniform 64-PAM constellations that constitute the non-uniform 4096-QAM constellations according to the present disclosure when the code rate is 7/15, respectively.

Table 5 and Table 6 are tables illustrating the cyclic block permutations and the non-uniform 64-PAM constellations that constitute the non-uniform 4096-QAM constellations according to the present disclosure when the code rate is equal to 8/15, respectively.

Note that cyclic block permutation unit 210 in FIG. 14 permutates the cyclic blocks within the codeword according to the code rate of the code used by LDPC encoder 121 , based on the cyclic block permutations of Table 1, Table 3, and Table 5 according to the code rates 6/15, 7/15, and 8/15, respectively.

Next, operations of the QAM mapper of the present exemplary embodiment will be described.

Mapping to complex cells s (Re, Im) by QAM mapper 124 is performed by calculation of Equation 4 described below. However, non-uniform PAM coordinates p(x) are obtained from Table 2 in the case of the code rate 6/15, from Table 4 in the case of the code rate 7/15, and from Table 6 in the case of the code rate 8/15.

where address labels x′ for real part p (x′) are calculated by Equation 5 by using even numbered bits b 0 , b 2 , b 4 , b 6 , b 8 , b 10 which are output from the interleaver (section interleaver) (a number of cyclic blocks per section is B) that is disposed in a subsequent stage of FIG. 14 and that has a function equivalent to bit interleaver 122 described with reference to FIG. 13 A to FIG. 13 C .

In addition, address label x″ of imaginary part p (x″) is calculated by Equation 6 by using odd numbered bits b 1 , b 3 , b 5 , b 7 , b 9 , b 11 that are output from the above-described section interleaver.

The above-described cyclic block permutations (for example, Table 1, Table 3, Table 5) and the non-uniform QAM constellations (for example, Table 2, Table 4, Table 6) are relevant to both the transmitter side and the receiver side in a digital communication system. Each of the above-described cyclic block permutations uniquely defines its inverse cyclic block permutation. One of the above-described cyclic block permutations is used for bit interleaving on the transmitter side, and its inverse cyclic block permutation is used for bit de-interleaving on the receiver side. Further, based on the above-described definition of the above-described non-uniform QAM constellation (two-dimensional non-uniform constellation), mapping of constellation words, that is, bits of the codeword to complex cells used for transmission is performed in the transmitter, and demapping of the received complex cells is performed in the receiver on the other side of a communication channel.

The above-described cyclic block permutations and the above-described non-uniform 4096-QAM constellations are optimized for special LDPC codes with the code rates of 6/15, 7/15, 8/15.

Table 7-1, Table 7-2 illustrate definition of this LDPC code with the code rate of 6/15 and a code length of 64800 code bits. Note that actually, the definition of the LDPC code is completed by a last row of Table 7-1 followed by a first row of Table 7-2.

Table 8-1 and Table 8-2 illustrate definition of this LDPC code with the code rate of 7/15 and the code length of 64800 code bits. Note that actually, the definition of the LDPC code is completed by the last row of Table 8-1 followed by the first row of Table 8-2.

Table 9-1 and Table 9-2 illustrate definition of this LDPC code with the code rate of 8/15 and the code length of 64800 code bits. Note that actually, the definition of the LDPC code is completed by the last row of Table 9-1 followed by the first row of Table 9-2.

Calculation processing of the parity bits performed by LDPC encoder 121 will be described below.

The LDPC code with the code rates of 6/15, 7/15 is defined based on the following algorithm.

The LDPC code is used for encoding information block s=(s 0 , s 1 , . . . , s K−1 ), and for accordingly generating codeword A with code length N=K+M 1 +M 2 , Λ=(λ 0 , λ 1 , . . . , λ N−1 )=(λ 0 , λ 1 , . . . , λ k−1 , p 0 , p 1 , . . . , p M1+M2−1 ).

where, in the case of the code rate 6/15, M 1 =1080, M 2 =37800, Q 1 =3, Q 2 =105. In addition, in the case of the code rate 7/15, M 1 =1080, M 2 =33480, Q 1 =3, Q 2 =93.

LDPC encoder 121 calculates the parity bit as follows.

(1) Initialization by Equation 7 is performed.

(2) For λ m (where, m=0, 1, . . . , 359), λ m is accumulated at parity bit addresses by Equation 8.

where x indicates the address of the parity bit accumulator corresponding to first bit λ 0 . Note that mod represents a modulo operator (the same applies to the followings).

(3) For 360-th information bit λ L , the addresses of the parity bit accumulators are provided in the second row of the definition based on each of Table 7-1 and Table 7-2 in the case of the code rate 6/15, and the addresses of the parity bit accumulators are provided in the second row of the definition based on each of Table 8-1 and Table 8-2 in the case of the code rate 7/15. Similarly, the addresses of the parity bit accumulators for next λ m (where m=L+1, L+2, . . . , L+359) are obtained by Equation 9.

where x indicates the address of λ L . In the case of the code rate 6/15, x is a value in the second row of the definition based on each of Table 7-1 and Table 7-2, and in the case of the code rate 7/15, x is a value in the second row of the definition based on each of Table 8-1 and Table 8-2.

(4) Similarly, a new row of the definition based on each of Table 7-1 and Table 7-2 in the case of the code rate 6/15, and a new row of the definition based on each of Table 8-1 and Table 8-2 in the case of the code rate of 7/15 are used for each group of new 360 information bits in order to find the addresses of the parity bit accumulators.

(5) After the codeword bits from λ 0 to λ K−1 are processed, an operation expressed by Equation 10 is performed sequentially with start of i=1.

(6) The parity bits from λ K to λ K+M1−1 are obtained by using an interleaving operation of L=360 expressed by Equation 11.

(7) The addresses of the parity bit accumulators are calculated by Equation 12 for each group of the new codeword bits of L=360 from λ K to λ K+M1−1 , by using a new row of the definition based on each of Table 7-1 and Table 7-2 in the case of the code rate 6/15, and by using a new row of the definition based on each of Table 8-1 and Table 8-2 in the case of the code rate 7/15.

where x indicates the address corresponding to a head code bit of each group of the codeword bits. In the case of the code rate 6/15, x is a value of the row corresponding to each group of the definition based on each of Table 7-1 and Table 7-2. In the case of the code rate 7/15, x is a value of the row corresponding to each group of the definition based on each of Table 8-1 and Table 8-2.

(8) After the codeword bits from λ K to λ K+M1−1 are processed, the parity bits from λ K+M1 to λ K+M1+M2−1 are obtained by using an interleaving operation of L=360 expressed by Equation 13.

(9) Subsequently, codeword bits λ i (i=0, 1, . . . , N−1) are sent to cyclic block permutation unit 210 of the bit interleaver.

The LDPC code with the code rate of 8/15 is defined by the following algorithm.

(1) The bits of the LDPC codeword are denoted as c 0 , c 1 , . . . , c N−1 , and the first K bits are equal to information bits and are represented by Equation 14.

Then, parity bit p k =c k+K is calculated as follows by LDPC encoder 121 .

(2) Initialization by Equation 15 is performed.

where N=64800, and K=N×code rate.

(3) For k which is equal to or greater than 0 and is less than K, i is a maximum integer that is not larger than a value obtained by division of k by 360, and l=k mod 360. For all j, i k is accumulated in p q (i, j, k) , as expressed by Equation 16.

⋮

where w(i) is a number of elements in the i-th row in the index list of the definition based on each of Table 9-1 and Table 9-2.

(4) Processing by Equation 17 is performed on all k of 0<k<N−K.

(5) All codeword bits c 0 , c 1 , . . . , c N−1 are obtained in the above-described steps. A parity interleaver expressed by Equation 18 is applied to the last N−K codeword bits.

A role of the parity interleaver is to convert the staircase structure of the parity part of the LDPC parity-check matrix into a quasi-cyclic structure similar to the information part of the matrix. Parity interleaved codeword bits c 0 , c 1 , . . . , c N−1 are sent to cyclic block permutation unit 210 of the bit interleaver.

Parameters q (i, j, 0) indicate j-th entry of the i-th row in the index list of the definition based on each of Table 9-1 and Table 9-2, and satisfy a relationship of Equation 19.

Every accumulation is realized by addition regarding the Galois field GF (2). R is 84 in the case of the code rate 8/15.

<<Supplemental (1)>>

The present disclosure is not limited to the description provided in the above-described exemplary embodiment, and can be carried out in any form for achieving the object of the present disclosure and an object related or relevant to the object of the present disclosure. For example, the present disclosure may be as follows.

(1) The present disclosure is described with reference to the special exemplary embodiment illustrated in the accompanying drawings, particularly, by presenting one example as values of key parameters N, M, Q. However, the present disclosure is not limited to the specific combination of these parameters. In fact, the present disclosure is applicable to any combination practically relevant to values (positive integers) for these parameters, such as those described in the DVB-T2 standard or those defined by a similar standard.

(2) The present disclosure is not limited to a specific form for implementing the disclosed methods or devices in both software and hardware.

Particularly, the present disclosure may be implemented in a form of a computer-readable medium that embodies computer-executable instructions adapted such that a computer, a microprocessor, a microcontroller, and the like can execute all the steps of the method according to the exemplary embodiment of the present disclosure.

In addition, the present disclosure may be implemented in a form of an application-specific integrated circuit (ASIC) or in a form of a field programmable gate array (FPGA).

(3) The present disclosure relates to a digital communication system based on the QC LDPC codes and high-order constellations. The present disclosure provides special permutations that permutate the LDPC code bits and special non-uniform constellations that transmit interleaved codewords. The permutations and the non-uniform constellations are jointly optimized at the code rate of 6/15, 7/15, or 8/15.

<<Supplemental (2)>>

The communication method and the like according to the present disclosure will be summarized as follows.

(1) A first communication method is a data communication method for performing data communication in a digital communication system using a quasi-cyclic low-density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code. The communication method includes an interleaving step of executing a cyclic block permutation for a codeword generated based on the quasi-cyclic parity-check code, where the codeword includes a sequence of N cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword, and a constellation mapping step of mapping each of the bits of the codeword for which the cyclic block permutation is executed to a constellation point of a non-uniform constellation. In the communication method, the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword.

(2) According to a second communication method, in the first communication method, the code rate of the quasi-cyclic low-density parity-check code is 6/15, and the non-uniform constellation is a non-uniform 4096-QAM constellation having real coordinates and complex coordinates each of which is a non-uniform 64-PAM constellation given according to Table 2 described above.

(3) According to a third communication method, in the first or second communication method, the code rate of the quasi-cyclic low-density parity-check code is 6/15, and the cyclic block permutation is defined according to Table 1 described above.

(4) According to a fourth communication method, in the first communication method, the code rate of the quasi-cyclic low-density parity-check code is 7/15, and the non-uniform constellation is a non-uniform 4096-QAM constellation having real coordinates and complex coordinates each of which is a non-uniform 64-PAM constellation given according to Table 4 described above.

(5) According to a fifth communication method, in the first or fourth communication method, the code rate of the quasi-cyclic low-density parity-check code is 7/15, and the cyclic block permutation is defined according to Table 3 described above.

(6) According to a sixth communication method, in the first communication method, the code rate of the quasi-cyclic low-density parity-check code is 8/15, and the non-uniform constellation is a non-uniform 4096-QAM constellation having real coordinates and complex coordinates each of which is a non-uniform 64-PAM constellation given according to Table 6 described above.

(7) According to a seventh communication method, in the first or sixth communication method, the code rate of the quasi-cyclic low-density parity-check code is 8/15, and the cyclic block permutation is defined according to Table 5 described above.

(8) According to an eighth communication method, in any one of the first to seventh communication methods, N is equal to 180 and Q is equal to 360.

(9) According to a ninth communication method, in any one of the first to eighth communication methods, the quasi-cyclic parity-check code used for generation of the codeword is selected from a plurality of the determined quasi-cyclic parity-check codes having code rates different from each other.

(10) A first communication device is a communication device in a digital communication system that performs communication by any one of the first to ninth communication methods.

(11) A tenth communication method is a data communication method for performing data communication in a digital communication system using quasi-cyclic low-density parity-check including a repeat-accumulate quasi-cyclic low-density parity-check code. The communication method includes executing a cyclic block permutation for a codeword generated based on the quasi-cyclic low-density parity-check code, performing demapping based on a non-uniform constellation on each of complex cells obtained by performing constellation mapping of the non-uniform constellation on a bit of the codeword for which the cyclic block permutation is executed, and performing processing inverse to the cyclic block permutation on a result of the demapping.

(12) A second communication device is a communication device in a digital communication system that performs communication by the tenth communication method.

(13) An eleventh communication method includes executing a cyclic block permutation for a codeword generated based on a quasi-cyclic low-density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the codeword includes a sequence of N cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword, mapping each of the bits of the codeword for which the cyclic block permutation is executed to any one of constellation points of a non-uniform constellation, and transmitting the mapped codeword. In the eleventh communication method, the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword, in a case where the code rate of the quasi-cyclic low-density parity-check code is equal to 7/15, the cyclic block permutation is defined according to Table 1.

According to a twelfth communication method, in the eleventh communication method, N is equal to 180, and Q is equal to 360.

According to a thirteenth communication method, in the eleventh communication method, the quasi-cyclic parity-check code used for generation of the codeword is selected from a plurality of the determined quasi-cyclic parity-check codes having the code rates different from each other.

A third communication device includes interleaving circuitry which, in operation, executes a cyclic block permutation for a codeword generated based on a quasi-cyclic low-density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the codeword includes a sequence of N cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword, a constellation mapping circuitry which, in operation, maps each of the bits of the codeword for which the cyclic block permutation is executed to any one of constellation points of a non-uniform constellation, and a transmitting circuitry which, in operation, transmits the mapped codeword. In the third communication device, the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword, in a case where the code rate of the quasi-cyclic low-density parity-check code is equal to 7/15, the cyclic block permutation is defined according to Table 3.

Although various exemplary embodiments have been described above with reference to the drawings, the present disclosure is of course not limited to such examples. It will be apparent that various changes or modifications are conceivable by those skilled in the art within the scope described in the appended claims. It is understood that those changes or modifications naturally belong to the technical scope of the present disclosure. In addition, the components in the aforementioned exemplary embodiments may be combined in any manner within the spirit of the disclosure.

Although the above-described exemplary embodiments have described the example in which the configuration in the present disclosure is made by using hardware, the present disclosure can also be realized by software in cooperation with hardware.

In addition, the functional blocks used for the description of the above-described exemplary embodiments are each typically realized as an LSI that is an integrated circuit having input terminals and output terminals. These functional blocks may be individually integrated into one chip, or may be integrated into one chip such that part or all of the functional blocks are incorporated. Although the integrated circuit is an LSI here, the integrated circuit may be referred to as an IC, a system LSI, a super LSI, and an ultra LSI, depending on a difference in a degree of integration.

In addition, an approach for circuit integration is not limited to an LSI, and circuit integration may be realized by using a dedicated circuit or a general-purpose processor. A field programmable gate array (FPGA) which is programmable after manufacture of an LSI, or a reconfigurable processor in which connection or settings of circuit cells within the LSI are reconfigurable may be used.

Further, when an advance in semiconductor technologies or other related technologies yields a circuit integration technology that can substitute for an LSI, the functional blocks may of course be integrated by using such a technology. For example, application of biotechnology may be possible.

The present disclosure can be used for a BICM system that uses a QC LDPC code and QAM.