Wireless communication technology, apparatuses, and methods

This application is a divisional of U.S. patent application Ser. No. 16/472,830, filed Jun. 21, 2019, which is a U.S. National Stage Filing under 35 U.S.C. 371 from International Application No. PCT/US2017/067739, filed on Dec. 20, 2017, and published in English as WO 2018/119153 on Mar. 14, 2019, each of which claims the benefit of priority to the following provisional patent applications:

U.S. Provisional Patent Application Ser. No. 62/437,385, entitled “MILLIMETER WAVE ANTENNA STRUCTURES” and filed on Dec. 21, 2016;

U.S. Provisional Patent Application Ser. No. 62/511,398, entitled “MILLIMETER WAVE TECHNOLOGY” and filed on May 26, 2017;

U.S. Provisional Patent Application Ser. No. 62/527,818, entitled “ANTENNA CIRCUITS AND TRANSCEIVERS FOR MILLIMETER WAVE (MMWAVE) COMMUNICATIONS” and filed on Jun. 30, 2017; and

U.S. Provisional Patent Application Ser. No. 62/570,680, entitled “RADIO FREQUENCY TECHNOLOGIES FOR WIRELESS COMMUNICATIONS” and filed on Oct. 11, 2017.

Each of which is incorporated herein by reference in its entirety.

Some aspects of the present disclosure pertain to antennas and antenna structures. Some aspects of the present disclosure pertain to antennas and antenna structures for millimeter-wave communications. Some aspects of the present disclosure pertain to wireless communication devices (e.g., mobile devices and base stations) that use antennas and antenna structures for communication of wireless signals. Some aspects of the present disclosure relate to devices that operate in accordance with 5th Generation (5G) wireless systems. Some aspects of the present disclosure relate to devices that operate in accordance with the Wireless Gigabit Alliance (WiGig) (e.g., IEEE 802.11ad) protocols. Some aspects of the present disclosure relate to using multi-stage copper pillar etching. Some aspects of the present disclosure relate to co-located millimeter wave (mmWave) and near-field communication (NFC) antennas. Some aspects of the present disclosure relate to a scalable phased array radio transceiver architecture (SPARTA). Some aspects of the present disclosure relate to a phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable. Some aspects of the present disclosure relate to communicating radio frequency (RF) signals over cable (RFoC) in a distributed phased array communication system. Some aspects of the present disclosure relate to clock noise leakage reduction. Some aspects of the present disclosure relate to intermediate frequency (IF)-to-RF companion chip for backwards and forwards compatibility and modularity. Some aspects of the present disclosure relate to on-package matching networks. Some aspects of the present disclosure relate to 5G scalable receiver (Rx) architecture.

Physical space in mobile devices for wireless communication is usually at a premium because of the amount of functionality that is included within the form factor of such devices. Challenging issues arise, among other reasons, because of need for spatial coverage of radiated radio waves, and of maintaining signal strength as the mobile device is moved to different places, or because a user may orient the mobile device differently from time to time. This can lead to the need, in some aspects, for a large number of antennas, varying polarities, directions of radiation, varying spatial diversity of the radiated radio waves at varying time, and related needs. When designing packages that include antennas operating at millimeter wave (mmWave or mmW) frequencies, efficient use of space can help resolve such issues.

The ubiquity of wireless communication has continued to raise a host of challenging issues. In particular, challenges have evolved with the advent of mobile communication systems, such as 5G communications systems due to both the wide variety of devices with different needs and the spectrum to be used. In particular, the ranges of frequency bands used in communications has increased, most recently due to the incorporation of carrier aggregation of licensed and unlicensed bands and the upcoming use of the mmWave bands.

A challenge in mmWave radio front end modules (RFEMs) is providing for complete or near-complete directional coverage. Millimeter Wave systems require high antenna gain to close link budgets, and phased array antennas can be used to provide beam steering. However, the use of phased array antennas (such as an array of planar patch antennas) by themselves provide limited angular coverage. Although beam steering can help to direct energy towards the intended receiver (and reciprocally increase gain at the receiver in the direction of the intended transmitter), a simple array limits the coverage of steering angles. In addition, polarization of radio frequency (RF) signals is a major issue for mmWave. There are significant propagation differences between vertical and horizontal polarization, and in addition, use of both polarizations can be used to provide spatial diversity. Given the expected applications of this technology to mobile devices, it will become important to provide for selectable polarization in the antennas.

Another issue of increasing concern is atmospheric attenuation loss. Due to the high path loss caused by atmospheric absorption and high attenuation through solid materials, massive multiple input, multiple output (MIMO) systems may be used for communication in the mmWave bands. The use of beamforming to search for unblocked directed spatial channels, and the disparity between line of sight (LOS) and non-line of sight (NLOS) communications, may complicate mmWave architecture compared to the architecture used for communication through a wireless personal area network (WPAN) or a wireless local area network (WLAN).

FIG. 1 illustrates an exemplary user device according to some aspects.

FIG. 1 A illustrates a mmWave system, which can be used in connection with the device of FIG. 1 according to some aspects.

FIG. 2 illustrates an exemplary base station radio head according to some aspects.

FIG. 3 A illustrates exemplary millimeter wave communication circuitry according to some aspects.

FIG. 3 B illustrates aspects of exemplary transmit circuitry illustrated in FIG. 3 A according to some aspects.

FIG. 3 C illustrates aspects of exemplary transmit circuitry illustrated in FIG. 3 A according to some aspects.

FIG. 3 D illustrates aspects of exemplary radio frequency circuitry illustrated in FIG. 3 A according to some aspects.

FIG. 3 E illustrates aspects of exemplary receive circuitry in FIG. 3 A according to some aspects.

FIG. 4 illustrates exemplary useable RF circuitry in FIG. 3 A according to some aspects.

FIG. 5 A illustrates an aspect of an exemplary radio front end module (RFEM) according to some aspects.

FIG. 5 B illustrates an alternate aspect of an exemplary radio front end module, according to some aspects.

FIG. 6 illustrates an exemplary multi-protocol baseband processor useable in FIG. 1 or FIG. 2 , according to some aspects.

FIG. 7 illustrates an exemplary mixed signal baseband subsystem, according to some aspects.

FIG. 8 A illustrates an exemplary digital baseband subsystem, according to some aspects.

FIG. 8 B illustrates an alternate aspect of an exemplary baseband processing subsystem, according to some aspects.

FIG. 9 illustrates an exemplary digital signal processor subsystem, according to some aspects.

FIG. 10 A illustrates an example of an accelerator subsystem, according to some aspects.

FIG. 10 B illustrates an alternate exemplary accelerator subsystem, according to some aspects.

FIGS. 11 A to 11 E illustrate exemplary periodic radio frame structures, according to some aspects.

FIGS. 12 A to 12 C illustrate examples of constellation designs of a single carrier modulation scheme that may be transmitted or received, according to some aspects.

FIGS. 13 A and 13 B illustrate alternate exemplary constellation designs of a single carrier modulation scheme that may be transmitted and received, according to some aspects.

FIG. 14 illustrates an exemplary system for generating multicarrier baseband signals for transmission, according to some aspects.

FIG. 15 illustrates exemplary resource elements depicted in a grid form, according to some aspects.

FIG. 16 A , FIG. 16 B , FIG. 16 C , and FIG. 16 D illustrate example of coding, according to some aspects.

FIG. 17 is a cross-sectional view and a top view of an exemplary semiconductor die with metallic pillars according to some aspects.

FIG. 18 A is a cross-sectional view and a top view of an exemplary semiconductor die with metallic pillars forming a first type of interconnect structures according to some aspects.

FIG. 18 B is a cross-sectional view and a top view of an exemplary semiconductor die with metallic pillars forming a second type of interconnect structures according to some aspects.

FIG. 18 C is a cross-sectional view and a top view of an exemplary semiconductor die with metallic pillars forming a third type of interconnect structures according to some aspects.

FIG. 19 is a cross-sectional view of an exemplary semiconductor die with metallic pillars forming interconnect structures where the pillars are attached to a package laminate according to some aspects.

FIG. 20 A is a side view, in section illustration, of an exemplary user device sub-system as described in this disclosure, according to some aspects.

FIG. 20 B illustrates an exemplary pedestal part of the laminate structure of FIG. 20 A , according to some aspects.

FIG. 21 illustrates exemplary RF feeds inside the cavity of the laminate structure of FIG. 20 A , according to some aspects.

FIG. 22 illustrates exemplary RF feed traces piercing through an opening in a shield cage, according to some aspects.

FIG. 23 illustrates multiple views of an exemplary semi-conductor package with co-located millimeter wave (mmWave) antennas and a near field communication (NFC) antenna according to some aspects.

FIG. 24 illustrates an exemplary radio frequency front-end module (RFEM) with a phased antenna array according to some aspects.

FIG. 25 illustrates example locations of an exemplary RFEM in a mobile device according to some aspects.

FIG. 26 is a block diagram of an exemplary RFEM according to some aspects.

FIG. 27 is a block diagram of an exemplary media access control (MAC)/baseband (BB) sub-system according to some aspects.

FIG. 28 is a diagram of an exemplary NFC antenna implementation according to some aspects.

FIG. 29 illustrates multiple views of an exemplary semi-conductor package with co-located mmWave antennas and a near field communication (NFC) antenna on multiple printed circuit board (PCB) substrates according to some aspects.

FIG. 30 is a block diagram of an exemplary RF phased array system that implements beamforming by phase-shifting and combining the signals at RF according to some aspects.

FIG. 31 is a block diagram of an exemplary phased array system that implements beamforming by phase-shifting the local oscillator (LO) and combining the analog signals at IF/baseband according to some aspects.

FIG. 32 is a block diagram of an exemplary phased array system with digital phase-shifting and combining according to some aspects.

FIG. 33 is a block diagram of an exemplary transceiver cell element which can be used in a scalable phased array radio transceiver architecture according to some aspects.

FIG. 34 is a block diagram of an exemplary phased array radio transceiver architecture using multiple transceiver cells according to some aspects.

FIG. 35 illustrates exemplary dicing of semiconductor die into individual transceiver cells forming phased array radio transceivers according to some aspects.

FIG. 36 is a block diagram of an exemplary phased array radio transceiver architecture packaged with a phased array antenna according to some aspects.

FIG. 37 is a block diagram of an exemplary transceiver cell with communication busses according to some aspects.

FIG. 38 is a block diagram of an exemplary phased array transceiver architecture with transceiver tiles in LO phase-shifting operating mode using a single analog-to-digital converter (ADC) according to some aspects.

FIG. 39 is a block diagram of an exemplary phased array transceiver architecture with transceiver tiles in LO phase-shifting operating mode using multiple ADCs according to some aspects.

FIG. 40 is a block diagram of an exemplary phased array transceiver architecture with transceiver tiles in hybrid operating mode (LO and digital phase-shifting and combining) using multiple ADCs to generate multiple digital signals according to some aspects.

FIG. 41 is a block diagram of an exemplary phased array transceiver architecture with transceiver tiles in analog IF/baseband phase-shifting and combining operating mode using a single ADC according to some aspects.

FIG. 42 is a block diagram of an exemplary phased array transceiver architecture with transceiver tiles in analog IF/baseband phase-shifting operating mode using multiple ADCs to generate multiple digital signals according to some aspects.

FIG. 43 illustrates exemplary operation modes of a phased array transceiver architecture with transceiver tiles according to some aspects.

FIG. 44 A illustrates a top view of an exemplary substrate of one package of a two-package system, according to some aspects.

FIG. 44 B illustrates a bottom view of the substrate of FIG. 44 A , according to some aspects.

FIG. 44 C illustrates a bottom view of an exemplary substrate of a second package of the two package system of FIGS. 44 A and 44 B , according to some aspects.

FIG. 44 D illustrates the first package and the second package of FIGS. 44 A through 44 C , stacked in a package-on-package implementation, according to some aspects.

FIG. 45 A illustrates a top view of another exemplary substrate of one package of another two-package system, according to some aspects.

FIG. 45 B illustrates a bottom view of the substrate of FIG. 45 A , according to some aspects.

FIG. 45 C illustrates a bottom view of an exemplary substrate of a second package of the two package system of FIGS. 45 A and 45 B , according to some aspects.

FIG. 45 D illustrates the first package and the second package of FIGS. 45 A through 45 C , stacked in a package-on-package implementation, according to some aspects.

FIG. 46 A illustrates a top view of an exemplary substrate of one package of a yet another two-package system, according to some aspects.

FIG. 46 B illustrates a bottom view of the substrate of FIG. 45 A , according to some aspects.

FIG. 46 C illustrates a bottom view of an exemplary substrate of a second package of the two package system of FIGS. 45 A and 45 B , according to some aspects;

FIG. 46 D illustrates the first package and the second package of FIGS. 46 A through 46 C , stacked in a package-on-package implementation, according to some aspects.

FIG. 47 A illustrates a top view of an exemplary substrate of one package of still another two-package system, according to some aspects.

FIG. 47 B illustrates a bottom view of the substrate of FIG. 46 A , according to some aspects.

FIG. 47 C illustrates a bottom view of an exemplary substrate of a second package of the two package system of FIGS. 47 A and 47 B , according to some aspects.

FIG. 47 D illustrates the first package and the second package of FIGS. 44 A through 44 C , stacked in a package-on-package implementation, according to some aspects.

FIG. 48 A illustrates a top view of two packages of a two-package, side-by-side package system, according to some aspects.

FIG. 48 B illustrates a bottom view of the two packages of FIG. 48 A , according to some aspects.

FIG. 48 C illustrates a side view of the two packages of FIGS. 48 A and 48 B in a side-by-side implementation, according to some aspects.

FIG. 49 is an exemplary illustration of the various sizes of SD flash memory cards.

FIG. 50 illustrates a three dimensional view of an exemplary Micro SD card with content and functionality changed to repurpose the card for mmWave wireless communication operation, according to some aspects.

FIG. 51 A illustrates an exemplary Micro SD card of FIG. 50 showing the radiation pattern for the dipole antennas of FIG. 2 , according to some aspects.

FIG. 51 B illustrates the Micro SD card of FIG. 50 with vertically polarized monopole antenna elements standing vertically in the exposed area that is limited in Z-height, according to some aspects.

FIG. 51 C illustrates the Micro SD card of FIG. 50 with folded back dipole antennas, according to some aspects.

FIG. 52 illustrates three exemplary Micro SD cards modified as discussed above to provide a plurality of cards per motherboard, according to some aspects.

FIG. 53 A is a side view of an exemplary separated ball grid array (BGA) or land grid array (LGA) pattern package PCB sub-system with an attached transceiver sub-system, according to some aspects.

FIG. 53 B is a side view cross section of the sub-system of FIG. 53 A , according to some aspects.

FIG. 53 C is a top view of the sub-system of FIG. 53 A illustrating a top view of a shield and further illustrating a cutout, according to some aspects.

FIG. 53 D is a top view of the sub-system of FIG. 53 A illustrating the cutout to enable the antennas to radiate out, and illustrating contacts, according to some aspects.

FIG. 53 E shows an arrangement of exemplary sub-systems arranged circularly around a pole, for radiation coverage in substantially all directions, according to some aspects.

FIG. 53 F illustrates an exemplary sub-system in a corner shape, according to some aspects.

FIG. 53 G illustrates the sub-system of FIG. 3 A according to some aspects.

FIG. 53 H illustrates a side view of an exemplary antenna sub-system according to some aspects.

FIG. 53 I is a top view of an exemplary configuration of a dual-shield antenna sub-system according to some aspects.

FIG. 53 J illustrates a slide view of the antenna sub-system of FIG. 53 I , according to some aspects.

FIG. 54 A illustrates an exemplary 60 GHz phased array System-in-Package (SIP), according to some aspects.

FIG. 54 B illustrates a side perspective view of an exemplary 60 GHz phased array SIP, according to some aspects.

FIG. 55 illustrates a 60 GHz SIP placed on a self-tester, according to some aspects.

FIG. 56 A illustrates a test setup for a first part of a test to address undesired on-chip or on-package crosstalk in an SIP, according to some aspects.

FIG. 56 B illustrates an exemplary test setup for a second part of a test to address undesired on-chip or on-package crosstalk in an SIP, according to some aspects.

FIG. 57 illustrates exemplary automated test equipment suitable for testing a 60 GHz phased array SIP, according to some aspects.

FIG. 58 illustrates an exemplary component to be added to the automated test equipment of FIG. 57 , according to some aspects.

FIG. 59 illustrates an exemplary RF front-end module (RFEM) of a distributed phased array system according to some aspects.

FIG. 60 illustrates an exemplary baseband sub-system (BBS) of a distributed phased array system according to some aspects.

FIG. 61 illustrates an exemplary distributed phased array system with MIMO support and multiple coax cables coupled to a single RFEM according to some aspects.

FIG. 62 illustrates an exemplary distributed phased array system with MIMO support where each RFEM transceiver is coupled to a separate coax cable according to some aspects.

FIG. 63 illustrates an exemplary distributed phased array system with MIMO support and a single coax cable coupled to a single RFEM according to some aspects.

FIG. 64 illustrates exemplary spectral content of various signals communicated on the single coax cable of FIG. 3 according to some aspects.

FIG. 65 illustrates an exemplary distributed phased array system with a single BBS and multiple RFEMs with MIMO support and a single coax cable between the BBS and each of the RFEMs according to some aspects.

FIG. 66 illustrates an exemplary RF front-end module (RFEM) of a distributed phased array system according to some aspects.

FIG. 67 illustrates an exemplary baseband sub-system (BBS) of a distributed phased array system according to some aspects.

FIG. 68 illustrates an exemplary frequency diagram of signals communicated between a RFEM and a BBS according to some aspects.

FIG. 69 illustrates an exemplary RFEM coupled to an exemplary BBS via a single coax cable for communicating RF signals according to some aspects.

FIG. 70 illustrates a more detailed diagram of the BBS of FIG. 69 according to some aspects.

FIG. 71 illustrates an exemplary massive antenna array (MAA) using multiple RFEMs coupled to a single BBS according to some aspects.

FIG. 72 is an exploded view of a laptop computer illustrating exemplary waveguides for RF signals to reach the lid of the laptop computer, according to some aspects.

FIG. 73 is an illustration of one or more exemplary coaxial cables proceeding from a radio sub-system of a laptop computer and entering through a hole in a hinge of the laptop, en route to the lid of the laptop, according to some aspects.

FIG. 74 is an illustration of one or more exemplary coaxial cables from a radio sub-system of a laptop computer, exiting a hole in a hinge of a laptop lid, en route to an antenna or antenna array in the lid, according to some aspects.

FIG. 75 is a schematic of exemplary transmission lines for signals from a motherboard of a laptop computer to the lid of the laptop, and to a radio front end module (RFEM), according to some aspects.

FIG. 76 is a schematic of exemplary transmission lines for signals from a motherboard of a laptop computer to the lid of the laptop, and to a plurality of RFEMs, according to some aspects.

FIGS. 77 A and 77 B are illustrations of exemplary substrate-integrated waveguides (SIW), according to some aspects.

FIG. 78 illustrates an exemplary RF front-end module (RFEM) of a distributed phased array system with clock noise leakage reduction according to some aspects.

FIG. 79 illustrates an exemplary baseband sub-system (BBS) of a distributed phased array system with clock noise leakage reduction according to some aspects.

FIG. 80 illustrates an exemplary frequency diagram of signals communicated between an RFEM and a BBS according to some aspects.

FIG. 81 illustrates clock spreader and despreader circuits, which can be used in connection with clock noise leakage reduction according to some aspects.

FIG. 82 illustrates a frequency diagram of signals communicated between a RFEM and a BBS using clock noise leakage reduction according to some aspects.

FIG. 83 illustrates an exemplary RF front-end module (RFEM) of a distributed phased array system with IF processing according to some aspects.

FIG. 84 illustrates an exemplary baseband sub-system (BBS) of the distributed phased array system of FIG. 83 according to some aspects.

FIG. 85 illustrates an exemplary multi-band distributed phased array system with IF processing within the RFEMs according to some aspects.

FIG. 86 illustrates an exemplary distributed phased array system with an RFEM coupled to a BBS via a single coax cable for communicating RF signals according to some aspects.

FIG. 87 illustrates a more detailed diagram of the BBS of FIG. 86 according to some aspects.

FIG. 88 illustrates an exemplary distributed phased array system supporting multiple operating frequency bands, using multiple RFEMs coupled to a single BBS according to some aspects.

FIG. 89 illustrates a more detailed diagram of the BBS of FIG. 88 according to some aspects.

FIG. 90 illustrates an exemplary distributed phased array system including RFEM, a companion chip and a BBS, with IF processing offloaded to the companion chip according to some aspects.

FIG. 91 illustrates a more detailed diagram of the companion chip and the BBS of FIG. 90 according to some aspects.

FIG. 92 illustrates an exemplary multi-band distributed phased array system with IF processing within the companion chip according to some aspects.

FIG. 93 illustrates an exemplary on-chip implementation of a two-way power combiner according to some aspects.

FIG. 94 illustrates an exemplary on-chip implementation of a large scale power combiner according to some aspects.

FIG. 95 illustrates an exemplary on-chip implementation of an impedance transformation network according to some aspects.

FIG. 96 illustrates an exemplary on-package implementation of a two-way power combiner according to some aspects.

FIG. 97 illustrates an exemplary on-package implementation of a large scale power combiner according to some aspects.

FIG. 98 illustrates an exemplary on-package implementation of an impedance transformation network according to some aspects.

FIG. 99 illustrates an exemplary on-package implementation of a Doherty power amplifier according to some aspects.

FIG. 100 A is a side view of an exemplary unmolded stacked package-on-package embedded die radio system using a connector, according to some aspects.

FIG. 100 B is a side view of an exemplary dual patch antenna, according to some aspects

FIG. 1000 is a simulated graph of return loss of the dual patch antenna of FIG. 100 B as the volume of the antenna is increased, according to some aspects.

FIG. 101 A is a side view of an exemplary unmolded stacked package-on-package embedded die radio system using a flex interconnect, according to some aspects.

FIG. 101 B is a side view of the unmolded stacked package-on-package embedded die radio system using a flex interconnect where the flex interconnect is shown in photographic representation, according to some aspects.

FIG. 102 is a side view of an exemplary molded stacked package-on-package embedded die radio system, according to some aspects.

FIG. 103 is a side view of an exemplary molded package-on-package embedded die radio system, according to some aspects.

FIG. 104 is a side view of a package-on-package embedded die radio systems using redistribution layers, according to some aspects.

FIG. 105 is a side view of the molded stacked package-on-package embedded die radio system with recesses in the molded layers to gain height in the z-direction, according to some aspects.

FIG. 106 is a side view of the molded stacked package-on-package embedded die radio system that includes a mechanical shield embedded in the mold for EMI shielding and for heat spreading, according to some aspects.

FIG. 107 is a perspective view of an exemplary stacked ultra-thin system in a package radio system with a laterally placed antennas or antenna arrays, according to some aspects.

FIGS. 108 A through 108 C illustrate an exemplary embedded die package according to some aspects.

FIG. 109 illustrates a block diagram of a side view of an exemplary stacked ring resonators (SRR) antenna package cell using according to some aspects.

FIG. 110 illustrates exemplary ring resonators, which can be used in one or more layers of the antenna package cell of FIG. 109 according to some aspects.

FIG. 111 illustrates exemplary ring resonators with multiple feed lines using different polarization, which can be used in one or more layers of the antenna package cell of FIG. 109 according to some aspects.

FIG. 112 illustrates exemplary electric field lines in the E plane of the SRR antenna of FIG. 109 according to some aspects.

FIG. 113 is an exemplary graphical representation of reflection coefficient and boresight realized gain of the SRR antenna package cell of FIG. 109 according to some aspects.

FIG. 114 illustrates a block diagram of an exemplary antenna array using the SRR antenna package cell of FIG. 109 according to some aspects.

FIG. 115 illustrates a set of exemplary layers that make up an exemplary SRR antenna package cell of FIG. 109 according to some aspects.

FIG. 116 illustrates a block diagram of an exemplary stack up of the SRR antenna package cell of FIG. 109 according to some aspects.

FIG. 117 illustrates a block diagram of a plurality of exemplary striplines, which can be used as feed lines for the SRR antenna package cell of FIG. 109 according to some aspects.

FIG. 118 A illustrates an exemplary mobile device using a plurality of waveguide antennas according to some aspects.

FIG. 118 B illustrates an exemplary radio frequency front-end module (RFEM) with waveguide transition elements according to some aspects.

FIG. 119 A and FIG. 119 B illustrate perspective views of an exemplary waveguide structure for transitioning between a PCB and a waveguide antenna according to some aspects.

FIG. 120 A , FIG. 120 B , and FIG. 120 C illustrate various cross-sectional views of the waveguide transitioning structure of FIGS. 119 A- 119 B according to some aspects.

FIG. 121 A , FIG. 121 B , and FIG. 121 C illustrate various perspective views of the waveguide transitioning structure of FIGS. 119 A- 119 B including an exemplary impedance matching air cavity according to some aspects.

FIG. 122 illustrates another view of the air cavity when the PCB and the waveguide are mounted via the waveguide transitioning structure of FIGS. 119 A- 119 B according to some aspects.

FIG. 123 illustrates a graphical representation of simulation results of reflection coefficient values in relation to air gap width according to some aspects.

FIG. 124 illustrates an exemplary dual polarized antenna structure, according to some aspects.

FIGS. 125 A through 125 C illustrate an exemplary dual polarized antenna structure implemented on a multilayer PCB, according to some aspects.

FIG. 126 illustrates Simulated S-parameters of the antenna structure illustrated in FIGS. 125 A through 125 C , according to some aspects.

FIGS. 127 A and 127 B illustrate exemplary simulated far-field radiation patterns of the antenna structure illustrated in FIGS. 125 A through 125 C , according to some aspects.

FIG. 128 A illustrates a top view of the antenna structure of FIGS. 125 A through 125 C with surface wave holes drilled in one configuration, according to some aspects.

FIG. 128 B illustrates a top view of the antenna structure of FIGS. 125 A through 125 C with surface wave holes drilled in another configuration, according to some aspects.

FIG. 129 illustrates an alternative implementation of an exemplary dual polarized antenna structure according to some aspects.

FIG. 130 A illustrates a top view of the antenna of FIG. 129 , according to some aspects.

FIGS. 130 B and 130 C are perspective views of the antenna of FIG. 129 , according to some aspects.

FIG. 131 A illustrates a simulation of total radiation efficiency versus frequency for the antenna structures of FIGS. 130 A through 130 C , according to some aspects.

FIG. 131 B illustrates a top view of an exemplary 4×1 array of antennas of the type illustrated in FIGS. 130 A through 130 C , according to some aspects.

FIG. 131 C is a perspective view of the 4×1 array of antennas of the type illustrated in FIG. 131 B , according to some aspects.

FIGS. 131 D and 131 E illustrate exemplary simulation radiation patterns of the 4×1 antenna array of FIGS. 131 B and 131 C , a 0° phasing, according to some aspects.

FIGS. 131 F and 131 G illustrate exemplary simulation radiation patterns of the 4×1 antenna array of FIGS. 131 B and 131 C , a 120° phasing, according to some aspects.

FIG. 132 illustrates an exemplary simulation of worst case coupling between neighboring elements of the antenna array of FIGS. 131 B and 131 C , according to some aspects.

FIG. 133 illustrates envelope correlation for the 4×1 antenna array of FIGS. 131 B and 131 C at 0° degree phasing, according to some aspects.

FIG. 134 illustrates the coordinate system for the polar simulation radiation patterns described below, according to some aspects.

FIG. 135 illustrates an exemplary radio sub-system having a die embedded inside a primary substrate and shielded surface mounted devices above the primary substrate, according to some aspects.

FIG. 136 illustrates an exemplary radio sub-system having a die and surface mounted devices placed above the primary substrate within a cavity in a secondary substrate, according to some aspects.

FIG. 137 illustrates an exemplary radio system package having a die embedded inside a primary substrate and surface mounted devices placed above the primary substrate within a cavity in a secondary substrate, according to some aspects.

FIG. 138 A is a perspective cut-away view of an exemplary radio system package having a die embedded inside a primary substrate and surface mounted devices placed above the primary substrate within a cavity in a secondary substrate, according to some aspects.

FIG. 138 B is a perspective view of the radio system of FIG. 138 A illustrating the bottom side of the primary substrate, according to some aspects.

FIG. 139 is a perspective view of the radio system of FIG. 138 A illustrating the inside of the secondary substrate, according to some aspects.

FIG. 140 A is a partial perspective top view of the radio system of FIG. 138 A illustrating solder contacts for mechanical connection or electrical connection, according to some aspects.

FIG. 140 B is a partial perspective view of the radio system of FIG. 138 A illustrating solder contacts configured on a secondary substrate to match the solder contacts of FIG. 140 A , according to some aspects.

FIG. 141 A illustrates an exemplary single element edge-fire antenna including a surface component attached to a PCB, according to an aspect.

FIG. 141 B illustrates placement and material details of the single element antenna of FIG. 141 A , according to an aspect.

FIG. 141 C illustrates an end view of the single element antenna illustrated in FIGS. 141 A and 141 B , according to an aspect.

FIG. 141 D illustrates an exemplary four-antenna element array including antenna elements of the type illustrated in FIGS. 141 A and 141 B , according to an aspect.

FIG. 142 illustrates the bandwidth of the antenna illustrated in FIGS. 141 A and 141 B for two different lengths of extended dielectric, according to an aspect.

FIG. 143 illustrates the total efficiency over a frequency range of the antenna illustrated in FIGS. 141 A and 141 B , according to an aspect.

FIG. 144 illustrates total efficiency of the antenna illustrated in FIGS. 141 A and 141 B over a frequency range greater than the frequency range illustrated in FIG. 143 , according to an aspect.

FIG. 145 illustrates maximum realized gain over a frequency range for the antenna illustrated in FIGS. 141 A and 141 B , according to an aspect.

FIG. 146 illustrates the maximum realized gain over another frequency range for the antenna illustrated in FIG. 141 A and FIG. 141 B , according to an aspect.

FIG. 147 illustrates exemplary isolation between two neighboring antenna elements of the antenna array illustrated in FIG. 141 D , according to an aspect.

FIG. 148 A illustrates an exemplary three-dimensional radiation pattern at a given frequency for the antenna element illustrated in FIGS. 141 A and 141 B at a first extended dielectric length, according to an aspect.

FIG. 148 B illustrates an exemplary three-dimensional radiation pattern at a given frequency for the antenna element illustrated in FIGS. 141 A and 141 B for a second extended dielectric length, according to an aspect.

FIG. 148 C illustrates an exemplary three-dimensional radiation pattern at a given frequency for the four-element antenna array illustrated in FIG. 141 D , where each antenna element has a first extended dielectric length, according to an aspect.

FIG. 148 D illustrates an exemplary three-dimensional radiation pattern at a given frequency for the four-array antenna element illustrated in FIG. 141 D , where each antenna element has a second extended dielectric length, according to an aspect.

FIG. 149 illustrates an exemplary E-plane co-polarization radiation pattern at a given frequency for the antenna element illustrated in FIGS. 141 A and 141 B , according to an aspect.

FIG. 150 illustrates an exemplary E-plane cross-polarization radiation pattern at a given frequency for the antenna illustrated at FIG. 141 A and FIG. 141 B , according to an aspect.

FIG. 151 illustrates an exemplary H-plane co-polarization radiation pattern at a given frequency for the antenna illustrated in FIGS. 141 A and 141 B , according to an aspect.

FIG. 152 illustrates an exemplary H-plane cross-polarization radiation pattern at a given frequency for the antenna illustrated in FIGS. 141 A and 141 B , according to an aspect.

FIG. 153 A illustrates an exemplary antenna element similar to the antenna illustrated in FIGS. 141 A and 141 B with part of the surface component merged with the PCB, according to an aspect.

FIG. 153 B illustrates the antenna element illustrated in FIG. 153 A with additional detail illustrating vertical polarization and horizontal polarization feed points, according to an aspect.

FIG. 154 A illustrates an exemplary antenna element similar to that illustrated in FIGS. 141 A and 141 B , including a two surface components on both sides of a PCB, according to an aspect.

FIG. 154 B illustrates the antenna element illustrated in FIG. 154 A in additional detail including a close-up view of the feed line, according to an aspect.

FIG. 155 A is a perspective view of the dual polarization antenna of FIG. 153 B after soldering the small surface component and main PCB together, according to an aspect.

FIG. 155 B illustrates a transparent view of the antenna element illustrated in FIG. 155 A looking into the surface component that is merged with respect to the main PCB, according to an aspect.

FIG. 155 C illustrates a front view of the antenna element illustrated in FIG. 155 A in additional detail, according to an aspect.

FIG. 155 D illustrates a side view of the antenna element illustrated in FIG. 155 A , according to an aspect.

FIG. 156 A illustrates the return loss S-parameter for dual polarization for the antenna element illustrated in FIG. 155 A , according to an aspect.

FIG. 156 B illustrates an exemplary 3D radiation pattern with vertical feed for the antenna element illustrated in FIG. 155 A , according to some aspects.

FIG. 156 C illustrates a 3D radiation pattern with horizontal feed for the antenna element illustrated in FIG. 155 A , according to some aspects.

FIG. 157 A illustrates vertical polarization feed, E-plane radiation patterns for the antenna illustrated in FIG. 155 A , according to an aspect.

FIG. 157 B illustrates horizontal polarization feed, H-plane radiation patterns for the antenna element illustrated in FIG. 155 A , according to an aspect.

FIG. 158 illustrates exemplary realized gain for horizontal feed E-plane patterns of the antenna of FIG. 155 A , according to some aspects.

FIG. 159 A illustrates an exemplary antenna element with orthogonal vertical and horizontal excitation, according to some aspects.

FIG. 159 B illustrates an exemplary antenna element with +45 degree and −45 degree excitation, according to some aspects.

FIG. 160 A illustrates obtaining vertical (V) polarization by use of in-phase excitation for both ports of the antenna of FIG. 159 B , according to some aspects.

FIG. 160 B illustrates obtaining horizontal (H) polarization by use of one hundred eighty degree out-of-phase excitation at the ports of the antenna of FIG. 159 B , according to some aspects.

FIG. 161 A illustrates the antenna element of FIG. 159 A with vertical and horizontal excitation ports, according to some aspects.

FIG. 161 B illustrates exemplary simulated radiation pattern results for the antenna element of FIG. 161 A , according to some aspects.

FIG. 162 A illustrates an exemplary 4×4 array schematic using orthogonally excited antenna elements, according to some aspects.

FIG. 162 B illustrates exemplary simulated radiation pattern results for the 4×4 array of FIG. 162 A with dual-polarized antenna element, according to some aspects.

FIG. 162 C illustrates exemplary simulated radiation pattern results for at +45 degree scan angle excitation for the array of FIG. 162 A , according to some aspects.

FIG. 163 A illustrates an exemplary dual-polarized differential, 4-port patch antenna in an antiphase configuration, according to some aspects.

FIG. 163 B illustrates the antenna configuration of FIG. 163 A in side view according to some aspects.

FIG. 163 C illustrates an exemplary laminated structure stack-up including levels L 1 -L 6 for the antenna configurations of FIGS. 162 A and 162 B , according to some aspects.

FIG. 163 D illustrates exemplary patch antenna polarity in accordance with some aspects.

FIG. 163 E illustrates exemplary suppression of cross-polarization levels according to some aspects.

FIG. 164 illustrates exemplary simulated radiation pattern results for the 4-port antenna configuration aspect of FIGS. 163 A through 163 C , according to some aspects.

FIG. 165 A illustrates an exemplary 4-port excitation antenna topology with feed lines from a feed source to each of the four ports, according to some aspects.

FIG. 165 B illustrates the feed lines in the 4-port configuration of FIG. 165 A with the driven patch of the stacked patch antenna superimposed on the feed lines, according to some aspects.

FIG. 165 C illustrates an exemplary 12-level stack-up for the aspect of FIG. 165 B .

FIG. 166 A illustrates an exemplary 4×4 antenna array schematic using 4-port elements integrated with feed networks, according to some aspects.

FIG. 166 B and FIG. 166 C illustrate exemplary simulated radiation pattern results for the 4-port antenna array of FIG. 166 A , according to some aspects.

FIG. 167 A illustrates an exemplary array configuration using 2-port dual-polarized antenna elements, according to some aspects.

FIG. 167 B and FIG. 167 C illustrate exemplary simulated radiation pattern results for the antenna array of FIG. 167 A , according to some aspects.

FIG. 168 A illustrates another exemplary array configuration using 2-port dual-polarized antenna elements, according to some aspects.

FIG. 168 B and FIG. 168 C illustrate exemplary simulation results on radiation patterns for FIG. 168 A , according to some aspects.

FIG. 169 illustrates an exemplary mast-mounted mmWave antenna block with multiple antenna arrays for vehicle-to-everything (V2X) communications according to some aspects.

FIG. 170 illustrates exemplary beam steering and antenna switching in a millimeter wave antenna array communicating with a single evolved Node-B (eNB_according to some aspects.

FIG. 171 illustrates exemplary beam steering and antenna switching in a millimeter wave antenna array communicating with multiple eNBs according to some aspects.

FIG. 172 illustrates exemplary simultaneous millimeter wave communications with multiple devices using an antenna block with multiple antenna arrays according to some aspects.

FIG. 173 illustrates multiple exemplary beams, which can be used for millimeter wave communications by an antenna block that includes multiple antenna arrays according to some aspects.

FIG. 174 is a block diagram of an exemplary millimeter wave communication device using the antenna block with multiple antenna arrays of FIG. 169 according to some aspects.

FIG. 175 A is an illustration of an exemplary via-antenna array configured in a mobile phone, according to some aspects.

FIG. 175 B is an illustration of an exemplary via-antenna array configured in a laptop, according to some aspects.

FIG. 175 C is an illustration of an exemplary via-antenna array configured on a motherboard PCB, according to some aspects.

FIG. 176 A is a cross section view of an exemplary via-antenna in a multilayer PCB, according to some aspects.

FIG. 176 B is a perspective view of an exemplary via-antenna, according to some aspects.

FIG. 177 A is an illustration of an exemplary PCB via-antenna internal view from the top of a PCB, according to some aspects.

FIG. 177 B is an illustration of an exemplary PCB via-antenna viewed from the bottom of a PCB, according to some aspects.

FIG. 178 A is a top view of an exemplary via-antenna array, according to some aspects.

FIG. 178 B is an illustration of an exemplary vertical feed for a via-antenna, according to some aspects.

FIG. 178 C is an illustration of an exemplary horizontal feed for a via-antenna, according to some aspects.

FIG. 179 A is a perspective view of exemplary back-to-back vias configured as a dipole via-antenna, according to some aspects.

FIG. 179 B is a perspective view of an exemplary back-to-back via configured as a dipole via-antenna illustrating PCB laminate layers, according to some aspects.

FIG. 180 is a graph of antenna return loss for the dipole via-antenna configuration of FIGS. 179 A and 179 B , according to some aspects.

FIG. 181 A is a simulated far field coplanar radiation pattern for the dipole via-antenna configuration of FIGS. 179 A and 179 B at a frequency of 27.5 GHz using the Ludwig definition, according to some aspects.

FIG. 181 B is an exemplary simulated far field coplanar radiation pattern for the dipole via-antenna configuration of FIGS. 179 A and 179 B , at a frequency 28 GHz using the Ludwig definition, according to some aspects.

FIG. 181 C is an exemplary simulated far field coplanar radiation pattern for the dipole via-antenna configuration of FIGS. 179 A and 179 B at a frequency 29.5 GHz using the Ludwig definition, according to some aspects.

FIG. 182 is an exemplary two-element via-antenna array design for operation at 28 GHZ for 5G technology, according to some aspects.

FIG. 183 is a simulated graph of antenna return loss for the two-element via-antenna array design of FIG. 182 , according to some aspects.

FIG. 184 A is a simulated radiation pattern of the two-element via-array of FIG. 182 operating at a frequency of 27.5 GHz, according to some aspects.

FIG. 184 B is a simulated radiation pattern of the two-element via-array of FIG. 182 operating at a frequency of 29.5 GHz, according to some aspects.

FIG. 185 is a perspective view of an exemplary via-antenna designed in a PCB, according to some aspects.

FIG. 186 A is a bottom view of the ground plane of the via-antenna of FIG. 185 , according to some aspects.

FIG. 186 B is a side view of the via-antenna of FIG. 185 , according to some aspects.

FIG. 186 C is a perspective view of the via-antenna of FIG. 185 , according to some aspects.

FIG. 187 is a simulated graph of exemplary via-antenna return loss for the via-antenna of FIG. 185 , according to some aspects.

FIG. 188 is an illustration of air holes drilled around an exemplary via-antenna in a PCB to lower surface wave propagation, according to some aspects.

FIGS. 189 A through 189 C illustrate components of an exemplary modified ground plane for a 3D cone antenna, according to some aspects.

FIG. 189 D illustrates exemplary cone antennas with various defected ground planes.

FIGS. 190 A through 190 C illustrate an exemplary of a cone shaped monopole antenna structure with different types of ground planes, according to some aspects.

FIGS. 191 A and 191 B illustrate radiation pattern comparison between the antenna structures of FIG. 190 A through 190 C , according to some aspects.

FIGS. 192 A and 192 B are more detailed illustrations of some of the antenna structures of FIG. 190 A through 190 C , according to some aspects.

FIGS. 193 A and 193 B illustrate a top and bottom view of an exemplary 3D antenna structures of FIG. 190 A through 190 C , according to some aspects.

FIG. 194 is a graphical comparison between return loss of the antenna of FIG. 192 A and FIG. 192 B , according to some aspects.

FIGS. 195 A through 195 C illustrate E-field distribution for the ground structures of 190 A through 190 C, according to some aspects.

FIGS. 196 A through 196 C illustrate exemplary five-element cone antenna arrays without and with a modified ground plane, according to some aspects.

FIGS. 197 A and 197 B illustrate a cross polarization radiation pattern comparison with and without a modified ground plane, according to some aspects.

FIGS. 198 A and 198 B illustrate the effect of a ground plane on antenna radiation, according to some aspects.

FIG. 199 illustrates a comparison of return loss and isolation comparison for an exemplary antenna array with a modified ground plane, according to some aspects.

FIG. 200 illustrates a comparison of return loss and isolation between antenna elements for an exemplary unmodified grand antenna array, according to some aspects.

FIGS. 201 A through 201 C illustrate an exemplary PCB with slotted modified ground planes which may be used with 3D antennas, according to some aspects.

FIG. 202 illustrates a block diagram of an exemplary receiver operating in switch and split modes.

FIG. 203 illustrates a block diagram of an exemplary receiver using segmented low-noise amplifiers (LNAs) and segmented mixers according to some aspects.

FIG. 204 illustrates a block diagram of an exemplary receiver using segmented low-noise amplifiers (LNAs) and segmented mixers operating in split mode to process a contiguous carrier aggregation signal according to some aspects.

FIG. 205 illustrates a block diagram of an exemplary receiver using segmented LNAs and segmented mixers operating in switch mode with signal splitting at LNA input according to some aspects.

FIG. 206 illustrates a block diagram of an exemplary receiver using segmented LNAs and segmented mixers operating in split mode with signal splitting at LNA input according to some aspects.

FIG. 207 illustrates a block diagram of an exemplary local oscillator (LO) signal generation circuit according to some aspects.

FIG. 208 illustrates a block diagram of an exemplary receiver using a segmented output LNA and segmented mixers operating in switch mode with signal splitting at LNA output according to some aspects.

FIG. 209 illustrates a block diagram of an exemplary receiver using a segmented output LNA and segmented mixers operating in split mode with signal splitting at LNA output according to some aspects.

FIG. 210 illustrates exemplary LO distribution schemes for receivers operating in a switch mode according to some aspects.

FIG. 211 illustrates exemplary LO distribution schemes for receivers operating in a split mode according to some aspects.

FIG. 212 is a side view of an unmolded stacked package-on-package embedded die radio system using a connector, according to some aspects.

FIG. 213 is a side view of an exemplary molded stacked package-on-package embedded die radio system, according to some aspects.

FIG. 214 is a side view of an exemplary molded package-on-package embedded die radio system, according to some aspects.

FIG. 215 illustrates cross-section of an exemplary computing platform with standalone components of an RF frontend, according to some aspects.

FIG. 216 illustrates cross-section of an exemplary computing platform with integrated components of a RF frontend within a laminate or substrate, according to some aspects.

FIG. 217 illustrates an exemplary smart device or an exemplary computer system or a SoC (System-on-Chip) which is partially implemented in the laminate/substrate, according to some aspects.

FIG. 218 is a side view of an exemplary molded package-on-package embedded die radio system, using ultra-thin components configured between the die and the antenna(s), according to some aspects.

FIG. 219 is a side view of the molded stacked package-on-package embedded die radio system with three packages stacked one upon the other, according to some aspects.

FIG. 220 is a high level block diagram of an exemplary mmWave RF architecture for 5G and WiGig, according to some aspects.

FIG. 221 illustrates a frequency conversion plan for an exemplary mmWave RF architecture for 5G and WiGig, according to some aspects.

FIG. 221 A is a schematic of frequency allocation for 5G 40 GHz frequency band, according to some aspects.

FIG. 221 B illustrates an exemplary synthesizer source to shift the second frequency band stream, out of two frequency band streams, across the unused 5G frequency band, according to some aspects.

FIG. 221 C illustrates phase noise power as a function of frequency, according to some aspects.

FIG. 222 illustrates an exemplary transmitter up-conversion frequency scheme for 5G in the 40 GHZ frequency band, according to some aspects.

FIG. 223 illustrates an exemplary transmitter up-conversion frequency scheme for 5G in the 30 GHZ frequency band, according to some aspects.

FIG. 224 A is a first section of an exemplary baseband integrated circuit (BBIC) block diagram, according to some aspects.

FIG. 224 B is a second section of an exemplary baseband integrated circuit (BBIC) block diagram, according to some aspects.

FIG. 225 is an exemplary detailed radio frequency integrated circuit (RFIC) block diagram, according to some aspects.

FIG. 226 A and FIG. 226 B are block diagrams of an exemplary mmWave and 5G communication system, according to some aspects.

FIG. 227 illustrates a schematic allocation of radio frequency (RF), intermediate frequency (IF), and local oscillator (LO) frequency for a sweep across a variety of channel options, according to some aspects.

FIG. 228 illustrates an exemplary fixed LO transmitter up-conversion scheme, according to some aspects.

FIG. 229 illustrates dual conversion in an exemplary radio system including a first conversion with a fixed LO, followed by a second conversion with a varying LO, according to some aspects.

FIG. 230 illustrates a digital-to-time converter (DTC) structure in accordance with some aspects.

FIG. 231 illustrates an open loop calibrated DTC architecture in accordance with some aspects.

FIG. 232 A illustrates time interleaving of DTCs to increase the clock frequency in accordance with some aspects; FIG. 232 B illustrates clock signals of FIG. 232 A in accordance with some aspects.

FIG. 233 illustrates a series injection locking oscillator with pulse shaping in accordance with some aspects.

FIG. 234 illustrates a method of providing a mmWave frequency signal in accordance with some aspects.

FIG. 235 illustrates a receiver in accordance with some aspects.

FIG. 236 illustrates a basic implementation of a feedforward equalizer (FFE) in accordance with some aspects.

FIG. 237 A and FIG. 237 B illustrates a FFE in accordance with some aspects.

FIG. 238 illustrates a method of providing analog signal equalization according to some aspects.

FIGS. 239 A and 239 B illustrate configurations of a reconfigurable decision feedback equalizer (DFE) in accordance with some aspects.

FIGS. 240 A and 240 B illustrate selector/D Flipflop (DFF) combination configurations of a reconfigurable DFE in accordance with some aspects.

FIG. 241 is a method of configuring a DFE in accordance with some aspects.

FIG. 242 illustrates a mmWave architecture in accordance with some aspects.

FIG. 243 illustrates a transmitter hybrid beamforming architecture in accordance with some aspects.

FIG. 244 illustrates a simulation of communication rate in accordance with some aspects.

FIG. 245 illustrates a simulation of a signal-to-noise ratio (SNR) in accordance with some aspects.

FIG. 246 illustrates a method of communicating beamformed mmWave signals in accordance with some aspects.

FIGS. 247 A and 247 B illustrate a transceiver structure in accordance with some aspects.

FIGS. 248 A and 248 B illustrate a transceiver structure in accordance with some aspects.

FIG. 249 illustrates an adaptive resolution analog-to-digital converter (ADC) power consumption in accordance with some aspects.

FIG. 250 illustrates bit error rate (BER) performance in accordance with some aspects.

FIG. 251 illustrates a method of communicating beamformed mmWave signals in accordance with some aspects.

FIGS. 252 A and 252 B illustrate a transceiver structure in accordance with some aspects.

FIG. 253 illustrates an array structure in accordance with some aspects.

FIG. 254 illustrates a simulation of grating lobes in accordance with some aspects.

FIG. 255 illustrates a simulation of optimal phase values in accordance with some aspects.

FIG. 256 illustrates another simulation of optimal phase values in accordance with some aspects.

FIG. 257 illustrates a process for a phase shifter in accordance with some aspects.

FIG. 258 illustrates a phase value determination in accordance with some aspects.

FIG. 259 illustrates a performance comparison in accordance with some aspects.

FIG. 260 illustrates another performance comparison in accordance with some aspects.

FIG. 261 illustrates a method of providing beam steering in a communication device in accordance with some aspects.

FIGS. 262 A and 262 B illustrate an aspect of a charge pump in accordance with some aspects.

FIG. 263 illustrates an aspect of a charge pump in accordance with some aspects.

FIG. 264 A illustrates a simplified scheme of an output portion of the charge pump in accordance with some aspects. FIG. 264 B illustrates a timing diagram of signals of the charge pump in accordance with some aspects.

FIGS. 265 A to 265 C illustrate the operation of the charge pump according to some aspects.

FIGS. 266 A to 266 C illustrate summarization of operation of the charge pump according to some aspects.

FIG. 267 illustrates a method of injecting charge in a charge pump in accordance with some aspects.

FIG. 268 illustrates a receiver architecture in accordance with some aspects.

FIG. 269 illustrates the filter characteristic of a receiver according to some aspects.

FIG. 270 illustrates the BER performance of a receiver according to some aspects.

FIG. 271 illustrates different receiver architectures according to some aspects.

FIG. 272 illustrates a method of compensating for interferers in a receiver in accordance with some aspects.

FIGS. 273 A and 273 B illustrate interference in accordance with some aspects.

FIG. 274 illustrates a receiver architecture in accordance with some aspects.

FIG. 275 illustrates an oversampled signal in accordance with some aspects.

FIGS. 276 A and 276 B illustrate filter characteristics of the receiver in accordance with some aspects.

FIG. 277 illustrates a beamforming pattern according to some aspects.

FIG. 278 illustrates a BER performance according to some aspects.

FIG. 279 illustrates a method of reducing quantizer dynamic range in a receiver in accordance with some aspects.

FIG. 280 illustrates an ADC system (ADCS) according to some aspects.

FIGS. 281 A and 281 B illustrate different operation modes of an ADCS according to some aspects.

FIG. 282 illustrates core ADC averaging according to some aspects.

FIG. 283 illustrates resolution improvement of an averaging system in accordance with some aspects.

FIG. 284 illustrates a method of providing a flexible ADC architecture in accordance with some aspects.

FIG. 285 illustrates a receiver architecture in accordance with some aspects.

FIG. 286 illustrates a simulation of a spatial response in accordance with some aspects.

FIG. 287 illustrates a simulation of BER in accordance with some aspects.

FIG. 288 illustrates a simulation of interference rejection in accordance with some aspects.

FIG. 289 illustrates a method of reducing quantizer dynamic range in a receiver in accordance with some aspects.

FIG. 290 is a block diagram of an example of a Time-Interleaved Analog to Digital Converter (TI-ADC) architecture in accordance with some aspects that may be utilized herein and that achieves a high-speed conversion using M parallel low speed ADC channels in some aspects.

FIG. 291 is a timing diagram 29100 that illustrates how all the channels operate with a same sampling frequency F s (or its inverse T s , illustrated in FIG. 291 ) with M uniformly spaced phases according to an example TI-ADC.

FIG. 292 is a block diagram illustrating an example of a transceiver 29200 having a loopback design according to an example disclosed herein.

FIG. 293 is a flowchart illustrating a process according to an example disclosed herein.

FIG. 294 is a block diagram of an example TI-ADC, according to some aspects.

FIG. 295 is a block diagram of an example of a TI-ADC architecture that achieves a high-speed conversion, according to some aspects.

FIG. 296 is a timing diagram that illustrates how all the channels operate with a same sampling frequency F s (or its inverse T s , illustrated in FIG. 296 ) with M uniformly spaced phases, according to some aspects.

FIG. 297 is a flowchart illustrating an example implementation of a process for applying the gain correction, according to some aspects.

FIG. 298 is a graph illustrating an example of a PA characteristic curve of AM/AM (input amplitude VS. output amplitude), according to some aspects.

FIG. 299 is a graph illustrating an example of a PA characteristic curve of AM/PM (input amplitude VS. output phase variation), according to some aspects.

FIG. 300 is a block diagram of an example of a gain model for a portion of a phased array transmitter, according to an exemplary aspect of the present disclosure.

FIG. 301 is a block diagram of an example of a switchable transceiver portion that the transmitter model described above may represent, according to an exemplary aspect of the present disclosure.

FIG. 302 is essentially a replica transceiver portion of the transceiver portion illustrated in FIG. 301 , but with the switches thrown in a receive configuration, according to an exemplary aspect of the present disclosure.

FIGS. 303 A and 303 B are parts of a block diagram of an overall transceiver example that may contain a transceiver portion, according to an exemplary aspect of the present disclosure.

FIG. 304 is a block diagram illustrating the phased array transceiver that is in communication with an external phased array transceiver (EPAT), according to an exemplary aspect of the present disclosure.

FIG. 305 is a flowchart illustrating an example of a process that may be used by the transceiver, according to an exemplary aspect of the present disclosure.

FIG. 306 is a flowchart illustrating another example of a process that may be used by the transceiver, according to an exemplary aspect of the present disclosure.

FIGS. 307 A and 307 B are parts of a block diagram of an example of an overall distributed phased array transceiver system, according to some aspects.

FIG. 308 is a block diagram of a receiver power amplifier according to some aspects.

FIG. 309 is a graph that plots, for a given automatic gain control (AGC) gain setting, an EVM versus the received power according to some aspects.

FIG. 310 is a graph that includes the EVM vs. receive power curve for a number of the AGC gain settings, where the AGC gain settings have degree of overlap with each other according to some aspects.

FIG. 311 is a graph illustrating optimal threshold values for activating a particular AGC gain setting according to some aspects.

FIG. 312 is a flowchart illustrating an example process that may be utilized to determine the optimal threshold values according to some aspects.

FIG. 313 is a block schematic diagram of a radio frequency (RF) phased array system according to some aspects.

FIG. 314 is a block schematic diagram illustrating another topology of a phased array radio transceiver that is referred to as a local oscillator (LO) phased array system according to some aspects.

FIG. 315 is a block schematic diagram illustrating a third alternative to phased array radio transceiver design according to some aspects and is referred to as a digital phased array system.

FIG. 316 is a block diagram of an example cell element of the SPARTA array, according to some aspects.

FIG. 317 is a block diagram illustrating tiled SPARTA cells according to some aspects.

FIGS. 318 and 319 are pictorial diagrams of wafer dicing according to some aspects.

FIG. 320 is a pictorial illustration of a combined SPARTA array that may be wafer processed and combined with an antenna array according to some aspects.

FIG. 321 is a block diagram illustrating A SPARTA cell (which may be an implementation of the SPARTA cell) that may be used for digital phase array tiling according to some aspects.

FIG. 322 is a block diagram that illustrates LO phased array pipelining between adjacent cells in the LO phase combining mode according to some aspects.

FIG. 323 is a block diagram illustrating the SPARTA cell tiling using an LO phase array and illustrating active data converter ADC according to some aspects.

FIG. 324 is a block diagram that illustrates a SPARTA array in hybrid mode, where each row is tiled in an LO phase shifting and sharing a single ADC according to some aspects.

FIG. 325 is a block diagram illustrating pipelining of the analog phased array combining between adjacent cells for the analog phased array combining operation mode according to some aspects.

FIG. 326 is a schematic diagram illustrating components for Injection-locked (IL)-based phase modulation circuit, according to some aspects, which exploits phase shift characteristics of a conventional locked oscillator.

FIG. 327 is a graph that illustrates how, as a center frequency of the oscillator is changed with respect to the locking frequency, the output phase and amplitude change, while still being locked to the injection frequency, according to some aspects.

FIG. 328 is a timing graph illustrating two symbols with phases φ 1 and φ 2 being generated by controlling the cap-DAC with baseband modulation bits as the data input, according to some aspects.

FIG. 329 is a block diagram for an IL-based phase modulation circuit with a full 360° phase modulation using a cascaded sub-harmonic injection-locked architecture with respect to the carrier frequency, according to some aspects.

FIG. 330 is a combination graph that illustrates a true time delay-based beam forming in which elements one and two are being fed the same baseband data signals (“11”, “00”) at two different offsets, according to some aspects.

FIG. 331 is a schematic block diagram illustrating an example architecture of a four-element phased array transmitter that implements combining harmonic IL based phase modulation with true time delay beam-forming, according to some aspects.

FIG. 332 is a block diagram for an IL-based phase modulation circuit illustrating an example of an injection-locked oscillator at operating at ⅓ of the carrier frequency, according to some aspects.

FIG. 333 is a block diagram for an IL-based phase modulation circuit illustrating an example of an injection-locked oscillator at operating at ½ of the carrier frequency, according to some aspects.

FIG. 334 is a pictorial diagram that illustrates quadrature phase-shift keying (QPSK) (PAM2-wireline-based) modulation (two bits per symbol) with a graph that is a constellation map illustrating the I/Q values that are possible, according to some aspects.

FIG. 335 is a pictorial diagram that illustrates a 16-QAM (PAM4-wireline-based) modulation (four bits per symbol) with a graph that is a constellation map illustrating the I/Q values that are possible, according to some aspects.

FIG. 336 is a pictorial diagram of a design for PAM2 (QPSK) modulation, according to some aspects.

FIG. 337 is a table of data and error values provided according to some aspects.

FIG. 338 is a graph illustrating use of the equation for Z and the first table, according to some aspects.

FIG. 339 is a table illustrating a second idea, in which the error values are all minus one, except above the plus three values and below the minus three value, according to some aspects.

FIG. 340 is a graph of the Z function using the second table, according to some aspects.

FIG. 341 is a block schematic diagram of a typical baud rate CDR loop for wireline, according to some aspects.

FIG. 342 is a block schematic diagram of a novel wireless CDR loop, having both an in-phase (I) and quadrature (Q) inputs, according to some aspects.

FIG. 343 is a table containing various mode values that may be used for the mode in the design of FIG. 342 , according to some aspects.

FIG. 344 A is a block schematic diagram of an example AGC circuit that may be implemented at a receiver where an amplitude of the received signal varies during the operation of the receiver, according to some aspects.

FIG. 344 B is a flowchart of an example AGC process that may be implemented at a receiver where an amplitude of the received signal varies during the operation of the receiver, according to some aspects.

FIG. 345 is a constellation graph for quadrature encoding that illustrates quantization bins for low-resolution ADCs with b=log 2 (2n) bits in each of the I/Q components of a receiver signal in a single antenna receiver system, according to some aspects.

FIG. 346 is a constellation graph for quadrature encoding illustrating quantization regions for a 3-bit ADC, according to some aspects.

FIG. 347 is a graph illustrating conditional probability distributions, where only r 1 and r 5 are monotonically increasing and decreasing, according to some aspects.

FIG. 348 is a graph illustrating the derivative of conditional probability distributions, according to some aspects.

FIG. 349 is a graph illustrating an example of the estimation performance of the proposed power estimation algorithm compared to the classical average power determination, according to some aspects.

FIG. 350 is a graph illustrating the latency of the novel algorithm, according to some aspects.

FIG. 351 is a graph that compares the normalized mean square error (MSE), according to some aspects.

FIG. 352 is a graph illustrating a mean square error (MSE) with a uniform 45° phase noise, according to some aspects.

FIG. 353 is a block schematic diagram illustrating an example of a MIMO receiver with a digital processor, according to some aspects.

FIG. 354 is a block diagram that illustrates an example of a beam forming circuit with N identical transceiver slices and N antenna elements, according to some aspects.

FIG. 355 is a graph that plots SNDR vs. input power at the antenna in the case when the antenna array gain is held constant, according to some aspects.

FIG. 356 is a graph that plots SNDR vs. input power at the antenna in the case when the antenna array gain is varied to enable gain control, according to some aspects.

FIG. 357 is a graph that illustrates the radiated power and the relative current drain versus the number of active elements in the antenna array, according to some aspects.

FIG. 358 is a graph that illustrates operating condition tradeoffs for Rx, according to some aspects.

FIG. 359 is a graph that illustrates operating condition tradeoffs for Tx, according to some aspects.

FIG. 360 is a flowchart that illustrates an example of a receive process that may be used, according to some aspects.

FIG. 361 is a flowchart that illustrates an example of a transmit process that may be used, according to some aspects.

FIG. 362 is a schematic diagram of a DAC architecture, according to some aspects.

FIG. 363 is a schematic diagram of a hierarchically structured, according to one implementation of a device described herein.

FIG. 364 is a combined pictorial chart diagram, including a pair of graphs illustrating co-polarization and cross-polarization when a transmit antenna and a receive antenna are aligned (i.e., parallel), according to some aspects.

FIG. 365 is a combined pictorial chart diagram, including a pair of graphs illustrating co-polarization and cross-polarization when a transmit antenna and a receive antenna are misaligned (i.e., not parallel), according to some aspects.

FIG. 366 is an example of a receiver using the MSFFPE design, according to some aspects.

FIG. 367 is a circuit diagram illustrating a conventional summer.

FIG. 368 is a circuit diagram illustrating an integrating a DFE summer, with the relevant differences highlighted, according to some aspects.

FIG. 369 is a schematic diagram that provides more details about the DFE summer design, according to some aspects.

FIG. 370 is a graph related to the DFE summer design illustrating the clock signal with respect to the summing amplifier out signal and the strong-arm-1 signal, according to some aspects.

FIG. 371 is a schematic illustration of a block diagram of an RF device, in accordance with some demonstrative aspects.

FIG. 372 is a schematic illustration of a block diagram of an RF device, in accordance with some demonstrative aspects.

FIG. 373 is a schematic illustration of a bi-directional amplifier circuit, in accordance with some demonstrative aspects.

FIG. 374 is a schematic illustration of a bi-directional amplifier circuit, in accordance with some demonstrative aspects.

FIG. 375 is a schematic illustration of a bi-directional amplifier circuit, in accordance with some demonstrative aspects.

FIG. 376 is schematic illustration of a block diagram of a transceiver including a cascode topology of an active bidirectional splitter and combiner (ABDSC), in accordance with some demonstrative aspects.

FIG. 377 is a schematic illustration of a circuit diagram of a common source topology of an ABDSC, in accordance with some demonstrative aspects.

FIG. 378 is a schematic illustration of a common gate topology of an ABDSC, in accordance with some demonstrative aspects.

FIG. 379 is a schematic illustration of a common gate/common source (CS/CG) topology of an ABDSC, in accordance with some demonstrative aspects.

FIG. 380 is a schematic illustration of a block diagram of an architecture of a transmitter, in accordance with some demonstrative aspects.

FIG. 381 A is a schematic illustration of an electronic circuit of a stacked-gate control amplifier, in accordance with some demonstrative aspects.

FIG. 381 B is a schematic illustration of an electronic circuit of a stacked-gate control amplifier, in accordance with some demonstrative aspects.

FIG. 382 is a schematic illustration of a block diagram of a transmitter including a stacked-gate modulated digital Power Amplifier (PA), in accordance with some demonstrative aspects.

FIGS. 383 A and 383 B are schematic illustrations of a dynamic realization of a multi-level high speed eye diagram, in accordance with some demonstrative aspects.

FIGS. 384 A and 384 B depict a performance improvement graph ( FIG. 384 A ) and a power reduction graph ( FIG. 384 B ) corresponding to an input series switch amplifier, in accordance with some demonstrative aspects.

FIG. 385 A and FIG. 385 B depict an amplitude resolution graph ( FIG. 385 A ) and a power efficiency graph ( FIG. 385 B ), corresponding to an N bit digital PA, in accordance with some demonstrative aspects.

FIG. 386 depicts a drain efficiency versus power saturation of a stacked gate-controlled amplifier with a driver amplifier before it, in accordance with some demonstrative aspects.

FIG. 387 is a schematic illustration of a block diagram of a transmitter, in accordance with some demonstrative aspects.

FIG. 388 is a schematic illustration of a block diagram of a two-stage Doherty amplifier, which may employ a Sub-Quarter Wavelength (SQWL) balun, in accordance with some demonstrative aspects.

FIG. 389 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects.

FIG. 390 is a schematic illustration of a block diagram of a transmitter, in accordance with some demonstrative aspects.

FIG. 391 is a schematic illustration of a block diagram of an outphasing amplifier employing an SQWL balun as a load, in accordance with some demonstrative aspects.

FIG. 392 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects.

FIG. 393 is a schematic illustration of an electronic circuit plan of phase shifting circuitry, in accordance with some demonstrative aspects.

FIG. 394 is a schematic illustration of a first quadrant of a constellation-point map, in accordance with some demonstrative aspects.

FIG. 395 is a schematic illustration of a graph depicting a gain variation of constellation points verses ideal phase shifted constellation points, in accordance with some demonstrative aspects.

FIG. 396 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects.

FIG. 397 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects.

FIG. 398 is a schematic illustration of a quadrature Local Oscillator (LO) generator, in accordance with some demonstrative aspects.

FIG. 399 is a schematic illustration of a passive quadrature LO generator, in accordance with some demonstrative aspects.

FIG. 400 is a schematic illustration of a block diagram of a transmitter, in accordance with to some demonstrative aspects.

FIG. 401 is a schematic illustration of a band plan of a plurality of channels corresponding to a plurality of channel bandwidths, which may be implemented in accordance with some demonstrative aspects.

FIG. 402 is a schematic illustration of a graph depicting a gain response of a low band amplifier and a high band amplifier, in accordance with some demonstrative aspects.

FIG. 403 is a schematic illustration of a transformer, in accordance with some demonstrative aspects.

FIG. 404 is a schematic illustration of a block diagram of a wireless communication apparatus, in accordance with some demonstrative aspects.

FIG. 405 is a schematic illustration of an impedance matching switch, in accordance to some demonstrative aspects.

FIG. 406 is a schematic illustration of a block diagram of a transceiver, in accordance with some demonstrative aspects.

FIG. 407 is a schematic illustration of a block diagram of a half-duplex transceiver, in accordance with some demonstrative aspects.

FIG. 408 is a schematic illustration of a bi-directional mixer, in accordance to some demonstrative aspects.

FIG. 409 A illustrates a phased-array transceiver, according to some aspects of the present disclosure.

FIG. 409 B illustrates an antenna array with an original reduced angle of coverage, according to some aspects of the present disclosure.

FIG. 409 C illustrates a lens used in conjunction with a phased-array antenna to deflect the radiated beams and extend the angle of coverage, according to some aspects of the present disclosure.

FIG. 409 D illustrates a concave reflector used in conjunction with a phased-array to deflect the radiated beams and extend the angle of coverage, according to some aspects of the present disclosure.

FIG. 410 illustrates a plurality of phased arrays used in conjunction with a printed reflector in a first configuration, according to some aspects of the present disclosure.

FIG. 411 illustrates a plurality of phased arrays used in conjunction with a Cassegrain antenna in the first configuration, according to some aspects of the present disclosure.

FIG. 412 illustrates a plurality of phased arrays used in conjunction with a printed reflector in a second configuration, according to some aspects of the present disclosure.

FIG. 413 illustrates a plurality of phased arrays used in conjunction with a Cassegrain antenna in the second configuration, according to some aspects of the present disclosure.

FIG. 414 illustrates a plurality of phased arrays used in conjunction with a printed reflector in a third configuration, according to some aspects of the present disclosure.

FIG. 415 illustrates a plurality of phased arrays used in conjunction with a Cassegrain antenna in the third configuration, according to some aspects of the present disclosure.

FIG. 416 illustrates a top view of sectorization resulting from a plurality of phased arrays used in conjunction with a reflecting antenna, according to some aspects of the present disclosure.

FIG. 417 illustrates scanning in each sector of the sectorized scan regions, according to some aspects of the present disclosure.

FIG. 418 illustrates a package within which antennas may be embodied within a user device, according to some aspects of the present disclosure.

FIG. 419 illustrates a graph of realized gain of a 1×4 dipole array embodied in the package of FIG. 418 , according to some aspects of the present disclosure.

FIG. 420 illustrates radiation patterns associated with the graph of FIG. 419 , according to some aspects of the present disclosure.

FIG. 421 illustrates the use of an integrated circuit (IC) shield as an antenna ground plane and a reflector for a stacked patch antenna, according to some aspects of the present disclosure.

FIG. 422 illustrates a side view of the monopole antenna illustrated in FIG. 421 showing an unsymmetrical via feeding mechanism, according to some aspects of the present disclosure.

FIGS. 422 A- 422 C illustrate certain dimensions of the monopole antenna illustrated in FIG. 421 , according to some aspects of the present disclosure.

FIG. 423 illustrates patch elements of the monopole antenna of FIGS. 421 and 422 in an antenna array configuration with a mobile platform, according to some aspects of the present disclosure.

FIG. 424 A illustrates a dipole antenna with a surface mounted device (SMD) antenna that transitions the dipole antenna to a dipole with a monopole, according to some aspects of the present disclosure.

FIG. 424 B is a perspective view of the dipole portion of the antenna of FIG. 424 A , according to some aspects of the present disclosure.

FIG. 424 C illustrates a combined dipole and monopole antenna, according to some aspects of the present disclosure.

FIG. 424 D illustrates a perspective view of the monopole part of the antenna of FIG. 424 A , according to some aspects of the present disclosure.

FIG. 424 E is a side view of the antenna of FIGS. 424 A and 424 D , according to some aspects of the present disclosure.

FIG. 425 illustrates a radiation pattern of the antenna of FIG. 424 A , according to some aspects of the present disclosure.

FIG. 426 A illustrates an elevation cut of the radiation pattern of the antenna of FIG. 424 A ,

FIG. 426 B illustrates a radiation pattern of the antenna of FIG. 424 B , according to some aspects of the present disclosure.

FIG. 427 A illustrates a side view of an SMD L-shaped dipole with an IC shield used as a reflector, according to some aspects of the present disclosure.

FIG. 427 B illustrates a perspective view of the SMD L-shaped dipole with an IC shield used as a reflector that is illustrated in FIG. 427 A , according to some aspects of the present disclosure.

FIG. 428 illustrates a perspective view of an array of four SMD L-shaped dipoles, according to an aspect.

FIG. 429 A illustrates the array of FIG. 428 for vertical polarization, with the fields cancelling out, according to some aspects of the present disclosure.

FIG. 429 B illustrates the array of FIG. 428 for vertical polarization, with the fields adding up, according to some aspects of the present disclosure.

FIG. 430 A illustrates the array of FIG. 428 for horizontal polarization, with the fields adding up, according to some aspects of the present disclosure.

FIG. 430 B illustrates the array of FIG. 428 for horizontal polarization, with the fields cancelling out, according to some aspects of the present disclosure.

FIG. 431 illustrates a three-dimensional radiation pattern for vertical (theta) polarization, according to some aspects of the present disclosure.

FIG. 432 illustrates a three-dimensional radiation pattern for horizontal (phi) polarization, according to some aspects of the present disclosure.

FIG. 433 illustrates a single SMD monopole antenna, according to some aspects of the present disclosure.

FIG. 434 illustrates a three-dimensional radiation pattern, according to some aspects of the present disclosure.

FIG. 435 illustrates an impedance plot of a single monopole, according to some aspects of the present disclosure.

FIG. 436 illustrates the return loss of a single monopole over frequency, according to some aspects of the present disclosure.

FIG. 437 illustrates realized vertical polarization (θ) gain in the X-Z plane from a single monopole, according to some aspects of the present disclosure.

FIG. 438 illustrates realized vertical polarization (θ) gain over frequency, at 15° above endfire, from a single monopole, according to some aspects of the present disclosure.

FIG. 439 illustrates a two-element monopole and a two-element dipole array, according to some aspects of the present disclosure.

FIG. 440 illustrates a three-dimensional radiation pattern of the two-dipole array of FIG. 439 at 60 GHz, according to some aspects of the present disclosure.

FIG. 441 illustrates realized horizontal polarity (Ø) gain over frequency in the endfire direction from the two-dipole array of FIG. 439 , according to some aspects of the present disclosure.

FIG. 442 illustrates a three-dimensional radiation pattern of the two-monopole array of FIG. 439 at 60 GHz, according to some aspects of the present disclosure.

FIG. 443 illustrates the realized vertical polarity (θ), according to some aspects of the present disclosure.

FIG. 444 illustrates a single patch, dual feed, dual polarization vertical SMD patch antenna, according to some aspects of the present disclosure.

FIG. 445 illustrates a stacked patch, single feed, single polarization vertical SMD patch antenna, according to some aspects of the present disclosure.

FIG. 446 illustrates a horizontal SMD patch antenna, according to some aspects of the present disclosure.

FIG. 447 illustrates a vertical SMD patch antenna using a cross-hatch pattern, according to some aspects of the present disclosure.

FIG. 448 illustrates an SMD spiral antenna with circular polarization, according to some aspects of the present disclosure.

FIG. 449 illustrates the implementation of a spiral antenna within an SMD, according to some aspects of the present disclosure.

FIG. 450 illustrates coupling radiation to directors on a chassis, according to some aspects of the present disclosure.

FIG. 451 A is a perspective view of an IC shield wall cut-out that forms an antenna, according to some aspects of the present disclosure.

FIG. 451 B is a side view of the wall cut-out that comprises the antenna illustrated in FIG. 451 A , according to some aspects of the present disclosure.

FIG. 451 C is a perspective view of an IC shield with a wall cut-out and a top cut-out that comprise antenna elements of an antenna array, according to some aspects of the present disclosure.

FIG. 451 D is a perspective view of an IC shield with a first wall cut-out and a second wall cut-out that comprise antenna elements of an antenna array, according to some aspects of the present disclosure.

FIG. 452 A illustrates a patch antenna and RF feed line connection including a transmit/receive (TR) switch for a single polarization design, according to some aspects of the present disclosure.

FIG. 452 B illustrates a patch antenna and RF feed line connection including a TR switch for a dual polarization design, according to some aspects of the present disclosure.

FIG. 452 C illustrates a patch antenna in a single polarization design, with the antenna feed line for the RX feed line matching point slightly offset to one side as compared to the TX feed line matching point, according to some aspects of the present disclosure.

FIG. 452 D illustrates a patch antenna in a dual polarization design, with the antenna feed lines for the RX feed line matching point slightly offset to one side as compared to the TX feed line matching point, for both polarizations, according to some aspects of the present disclosure.

FIG. 453 A illustrates a single polarization implementation of a TX feed line and an RX feed line connected directly to antenna feed line matching points, according to some aspects of the present disclosure.

FIG. 453 B illustrates a dual polarization implementation of a horizontal polarization TX feed line and RX feed line, and a vertical polarization TX feed line and RX feed line, connected directly to antenna feed line matching points, according to some aspects of the present disclosure.

FIG. 454 A illustrates an IC shield, according to some aspects of the present disclosure.

FIG. 454 B illustrates an IC shield with a bulge, or extension, to enhance antenna gain and directivity, according to some aspects of the present disclosure.

FIG. 454 C illustrates the use of a folded extension with an IC shield to improve the gain of an array of dipole antenna elements, according to some aspects of the present disclosure.

FIG. 454 D illustrates a hole that occurs in the shield structure because of the bulge, according to some aspects of the present disclosure.

FIG. 454 E is a close-up perspective view of the bulge and the hole of FIG. 54 D , according to some aspects of the present disclosure.

FIG. 455 is top view of a combined patch antenna and dipole antenna array with a shield reflector, according to some aspects of the present disclosure.

FIG. 456 is a side view of the antenna array of FIG. 455 , according to some aspects of the present disclosure.

FIG. 457 is a perspective view of an interposer used with a patch array to bypass large obstacles in a user device, according to some aspects of the present disclosure.

FIG. 458 A is a perspective view of the interposer of FIG. 457 illustrating an IC shield lid, according to some aspects of the present disclosure.

FIG. 458 B is a vertical view of the radiation pattern for the dipole antenna array of FIG. 458 A , with the endfire direction illustrated at minus ninety (−90) degrees, according to some aspects of the present disclosure.

FIG. 459 illustrates realized gain of the patch antenna array of FIGS. 457 and 458 A as a function of the height of the interposer, in various directions, according to some aspects of the present disclosure.

FIG. 460 A is a perspective view of a combined patch and slot antenna for dual band, dual polarization operation, according to some aspects of the present disclosure.

FIG. 460 B is a side view of the combined patch and slot antenna of FIG. 460 A , according to some aspects of the present disclosure.

FIG. 461 A is an exploded view of an antenna-on-a-chip (AOC), according to some aspects of the present disclosure.

FIG. 461 B is a bottom view of the antennas that comprise the AOC of FIG. 461 A , according to some aspects of the present disclosure.

FIG. 461 C is a side view of the AOC of FIG. 461 A , according to some aspects of the present disclosure.

FIG. 462 is another bottom view of the AOC of FIG. 461 A , including dimensions for some aspects of the present disclosure.

FIG. 463 is a radiation pattern for the antenna on a chip of FIGS. 461 A- 461 C and 462 , according to some aspects of the present disclosure.

FIG. 464 A illustrates another view of an AOC for an embedded die in a package on package implementation, according to some aspects of the present disclosure.

FIG. 464 B is an illustration of radiation efficiency as a function of height of the silicon divided by height of the patches, according to some aspects of the present disclosure.

FIG. 464 C is an illustration of realized gain in dBi as a function of height of the silicon divided by height of the patches, according to some aspects of the present disclosure.

FIG. 465 is another illustration of an AOC symbolically showing a chip overview and including the relationship of the antennas and the circuitry on the chip, according to some aspects of the present disclosure.

FIG. 466 illustrates a block diagram of an example machine upon which any one or more of the techniques or methodologies discussed herein may be performed, according to some aspects of the present disclosure.

FIG. 467 illustrates protocol functions that may be implemented in a wireless communication device, according to some aspects of the present disclosure.

FIG. 468 illustrates various protocol entities that may be implemented in connection with a wireless communication device or a wireless communication system, according to some aspects of the present disclosure.

FIG. 469 illustrates a medium access control (MAC) entity that may be used to implement medium access control layer functions according to some aspects of the present disclosure.

FIG. 470 A and FIG. 470 B illustrate formats of PDUs that may be encoded and decoded by the MAC entity of FIG. 469 according to some aspects of the present disclosure.

FIG. 470 C , FIG. 470 D , and FIG. 470 E illustrate various sub-headers that may be used in connection with the MAC entity of FIG. 469 according to some aspects of the present disclosure.

FIG. 471 illustrates functions contained within a radio link control (RLC) layer entity according to some aspects of the present disclosure.

FIG. 472 A illustrates a TMD PDU according to some aspects of the present disclosure.

FIG. 472 B and FIG. 472 C illustrate UMD PDUs according to some aspects of the present disclosure.

FIG. 472 D and FIG. 472 E illustrate AMD PDUs according to some aspects of the present disclosure.

FIG. 472 F illustrates a STATUS PDU according to some aspects of the present disclosure.

FIG. 473 illustrates aspects of functions, which may be contained within a packet data convergence protocol (PDCP) layer entity according to some aspects of the present disclosure.

FIG. 474 illustrates a PDCP PDU that may be transmitted and received by a PDCP entity according to some aspects of the present disclosure.

FIG. 475 illustrates aspects of communication between instances of radio resource control (RRC) layer according to some aspects of the present disclosure.

FIG. 476 illustrates states of an RRC that may be implemented in a user equipment (UE) according to some aspects of the present disclosure.

With the advancement of 5G mmWave-based communications, several challenges have evolved, such as limited communications range, directionality of the antenna systems, achieving desired directionality and beamforming with large scale antenna arrays, signal attenuation due to atmospheric attenuation loss and high attenuation through solid materials. Techniques described herein can be used in connection with digital baseband circuitry, transmit circuitry, receive circuitry, radio frequency circuitry, protocol processing circuitry and antenna arrays to address the challenges associated with the 5G mmWave-based communications.

Discussions herein utilizing terms such as, for example, “processing”, “computing”, “calculating”, “determining”, “establishing”, “analyzing”, “checking”, or the like, may refer to operation(s) and/or process(es) of a computer, a computing platform, a computing system, or other electronic computing device, that manipulate and/or transform data represented as physical (e.g., electronic) quantities within the computer's registers and/or memories into other data similarly represented as physical quantities within the computer's registers and/or memories or other information storage medium that may store instructions to perform operations and/or processes.

The terms “plurality” and “a plurality”, as used herein, include, for example, “multiple” or “two or more”. For example, “a plurality of items” includes two or more items.

References to “one aspect”, “an aspect”, “an example aspect”, “some aspects”, “demonstrative aspect”, “various aspects” etc., indicate that the aspect(s) so described may include a particular feature, structure, or characteristic, but not every aspect necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in one aspect” does not necessarily refer to the same aspect, although it may.

As used herein, unless otherwise specified the use of the ordinal adjectives “first”, “second”, “third” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

Some aspects may be used in conjunction with various devices and systems, for example, a User Equipment (UE), a Mobile Device (MD), a wireless station (STA), a Personal Computer (PC), a desktop computer, a mobile computer, a laptop computer, a notebook computer, a tablet computer, a server computer, a handheld computer, a sensor device, an Internet of Things (IoT) device, a wearable device, a handheld device, a Personal Digital Assistant (PDA) device, a handheld PDA device, an on-board device, an off-board device, a hybrid device, a vehicular device, a non-vehicular device, a mobile or portable device, a consumer device, a non-mobile or non-portable device, a wireless communication station, a wireless communication device, a wireless Access Point (AP), a wired or wireless router, a wired or wireless modem, a video device, an audio device, an audio-video (AN) device, a wired or wireless network, a wireless area network, a Wireless Video Area Network (WVAN), a Local Area Network (LAN), a Wireless LAN (WLAN), a Personal Area Network (PAN), a Wireless PAN (WPAN), and the like.

Some aspects may, for example, be used in conjunction with devices and/or networks operating in accordance with existing IEEE 802.11 standards (including IEEE 802.11-2016 (IEEE 802.11-2016, IEEE Standard for Information technology—Telecommunications and information exchange between systems Local and metropolitan area networks—Specific requirements Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Dec. 7, 2016); IEEE802.11ay (P802.11ay Standard for Information Technology—Telecommunications and Information Exchange Between Systems Local and Metropolitan Area Networks—Specific Requirements Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications—Amendment: Enhanced Throughput for Operation in License-Exempt Bands Above 45 GHz)) and/or future versions and/or derivatives thereof, devices and/or networks operating in accordance with existing WiFi Alliance (WFA) Peer-to-Peer (P2P) specifications (including WiFi P2P technical specification, version 1.5, Aug. 4, 2015) and/or future versions and/or derivatives thereof, devices and/or networks operating in accordance with existing Wireless-Gigabit-Alliance (WGA) specifications (including Wireless Gigabit Alliance, Inc WiGig MAC and PHY Specification Version 1.1, April 2011, Final specification) and/or future versions and/or derivatives thereof, devices and/or networks operating in accordance with existing cellular specifications and/or protocols, e.g., 3rd Generation Partnership Project (3GPP), 3GPP Long Term Evolution (LTE) and/or future versions and/or derivatives thereof, units and/or devices which are part of the above networks, and the like.

Some aspects may be used in conjunction with one way and/or two-way radio communication systems, cellular radio-telephone communication systems, a mobile phone, a cellular telephone, a wireless telephone, a Personal Communication Systems (PCS) device, a PDA device which incorporates a wireless communication device, a mobile or portable Global Positioning System (GPS) device, a device which incorporates a GPS receiver or transceiver or chip, a device which incorporates an RFID element or chip, a Multiple Input Multiple Output (MIMO) transceiver or device, a Single Input Multiple Output (SIMO) transceiver or device, a Multiple Input Single Output (MISO) transceiver or device, a device having one or more internal antennas and/or external antennas, Digital Video Broadcast (DVB) devices or systems, multi-standard radio devices or systems, a wired or wireless handheld device, e.g., a Smartphone, a Wireless Application Protocol (WAP) device, or the like.

Some aspects may be used in conjunction with one or more types of wireless communication signals and/or systems, for example, Radio Frequency (RF), Infra-Red (IR), Frequency-Division Multiplexing (FDM), Orthogonal FDM (OFDM), Orthogonal Frequency-Division Multiple Access (OFDMA), Spatial Divisional Multiple Access (SDMA), FDM Time-Division Multiplexing (TDM), Time-Division Multiple Access (TDMA), Multi-User MIMO (MU-MIMO), Extended TDMA (E-TDMA), General Packet Radio Service (GPRS), extended GPRS, Code-Division Multiple Access (CDMA), Wideband CDMA (WCDMA), CDMA 2000, single-carrier CDMA, multi-carrier CDMA, Multi-Carrier Modulation (MDM), Discrete Multi-Tone (DMT), Bluetooth, Global Positioning System (GPS), Wi-Fi, Wi-Max, ZigBee™, Ultra-Wideband (UWB), Global System for Mobile communication (GSM), 2G, 2.5G, 3G, 3.5G, 4G, Fifth Generation (5G) mobile networks, 3GPP, Long Term Evolution (LTE), LTE advanced, Enhanced Data rates for GSM Evolution (EDGE), or the like. Other aspects may be used in various other devices, systems and/or networks.

The term “wireless device”, as used herein, includes, for example, a device capable of wireless communication, a communication device capable of wireless communication, a communication station capable of wireless communication, a portable or non-portable device capable of wireless communication, or the like. In some demonstrative aspects, a wireless device may be or may include a peripheral that is integrated with a computer, or a peripheral that is attached to a computer. In some demonstrative aspects, the term “wireless device” may optionally include a wireless service.

The term “communicating” as used herein with respect to a communication signal includes transmitting the communication signal and/or receiving the communication signal. For example, a communication unit, which is capable of communicating a communication signal, may include a transmitter to transmit the communication signal to at least one other communication unit, and/or a communication receiver to receive the communication signal from at least one other communication unit. The verb communicating may be used to refer to the action of transmitting and/or the action of receiving. In one example, the phrase “communicating a signal” may refer to the action of transmitting the signal by a first device, and may not necessarily include the action of receiving the signal by a second device. In another example, the phrase “communicating a signal” may refer to the action of receiving the signal by a first device, and may not necessarily include the action of transmitting the signal by a second device.

Some demonstrative aspects may be used in conjunction with a WLAN, e.g., a WiFi network. Other aspects may be used in conjunction with any other suitable wireless communication network, for example, a wireless area network, a “piconet”, a WPAN, a WVAN and the like.

Some demonstrative aspects may be used in conjunction with a wireless communication network communicating over a frequency band above 45 Gigahertz (GHz), e.g., 60 GHz. However, other aspects may be implemented utilizing any other suitable wireless communication frequency bands, for example, an Extremely High Frequency (EHF) band (the millimeter wave (mmWave) frequency band), e.g., a frequency band within the frequency band of between 20 GHz and 300 GHz, a frequency band above 45 GHz, a frequency band below 20 GHz, e.g., a Sub 1 GHz (S1G) band, a 2.4 GHz band, a 5 GHz band, a WLAN frequency band, a WPAN frequency band, a frequency band according to the WGA specification, and the like.

As used herein, the term “circuitry” may, for example, refer to, be part of, or include, an Application Specific Integrated Circuit (ASIC), an integrated circuit, an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group), that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In some aspects, circuitry may include logic, at least partially operable in hardware. In some aspects, the circuitry may be implemented as part of and/or in the form of a radio virtual machine (RVM), for example, as part of a Radio processor (RP) configured to execute code to configured one or more operations and/or functionalities of one or more radio components.

The term “logic” may refer, for example, to computing logic embedded in circuitry of a computing apparatus and/or computing logic stored in a memory of a computing apparatus. For example, the logic may be accessible by a processor of the computing apparatus to execute the computing logic to perform computing functions and/or operations. In one example, logic may be embedded in various types of memory and/or firmware, e.g., silicon blocks of various chips and/or processors. Logic may be included in, and/or implemented as part of, various circuitry, e.g., radio circuitry, receiver circuitry, control circuitry, transmitter circuitry, transceiver circuitry, processor circuitry, and/or the like. In one example, logic may be embedded in volatile memory and/or non-volatile memory, including random access memory, read only memory, programmable memory, magnetic memory, flash memory, persistent memory, and/or the like. Logic may be executed by one or more processors using memory, e.g., registers, buffers, stacks, and the like, coupled to the one or more processors, e.g., as necessary to execute the logic.

The term “antenna”, as used herein, may include any suitable configuration, structure and/or arrangement of one or more antenna elements, components, units, assemblies and/or arrays. In some aspects, the antenna may implement transmit and receive functionalities using separate transmit and receive antenna elements. In some aspects, the antenna may implement transmit and receive functionalities using common and/or integrated transmit/receive elements. The antenna may include, for example, a phased array antenna, a single element antenna, a set of switched beam antennas, and/or the like.

The phrase “peer to peer (PTP) communication”, as used herein, may relate to device-to-device communication over a wireless link (“peer-to-peer link”) between devices. The PTP communication may include, for example, a WiFi Direct (WFD) communication, e.g., a WFD Peer to Peer (P2P) communication, wireless communication over a direct link within a Quality of Service (QoS) basic service set (BSS), a tunneled direct-link setup (TDLS) link, a STA-to-STA communication in an independent basic service set (IBSS), or the like.

Some demonstrative aspects are described herein with respect to WiFi communication. However, other aspects may be implemented with respect to any other communication scheme, network, standard and/or protocol.

In some demonstrative aspects, a wireless communication device may implement a millimeter wave (mmWave) radio front end module (RFEM), e.g., as described below.

Millimeter wave may be defined as a frequency range spanning about 30 GHz to about 300 GHz, and in practice currently covers several discrete licensed and unlicensed frequency bands.

The unlicensed mmWave frequency band currently available is in the vicinity of 60 GHz. Licensed frequency bands are likely to include 28 GHz, 39 GHz, 73 GHz and 120 GHz. The availability of these bands and the specific frequency range of each varies by regulatory jurisdiction, and in some cases (specifically for licensed band operation) there is still significant uncertainty as to regulations in some countries. Challenges associated with mmWave-based cellular communications include limited range, directionality of antennas of the range, signal loss because of use of regular cables instead of traces, and challenges with integrating multiple antennas for beamforming. These challenges are addressed in this patent as discussed below in accordance with some aspects, and may include use of polarization innovations, trace and other line use to avoid signal loss, and an improved ability for use in beamforming.

FIG. 1 illustrates an exemplary user device according to some aspects. The user device 100 may be a mobile device in some aspects and includes an application processor 105 , baseband processor 110 (also referred to as a baseband sub-system), radio front end module (RFEM) 115 , memory 120 , connectivity sub-system 125 , near field communication (NFC) controller 130 , audio driver 135 , camera driver 140 , touch screen 145 , display driver 150 , sensors 155 , removable memory 160 , power management integrated circuit (PMIC) 165 , and smart battery 170 .

In some aspects, application processor 105 may include, for example, one or more central processing unit (CPU) cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface sub-system, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose IO, memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces, and/or Joint Test Access Group (JTAG) test access ports.

In some aspects, baseband processor 110 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module including two or more integrated circuits.

Applications of mmWave technology can include, for example, WiGig and future 5G, but the mmWave technology can be applicable to a variety of telecommunications systems. The mmWave technology can be especially attractive for short-range telecommunications systems. WiGig devices operate in the unlicensed 60 GHz band, whereas 5G mmWave is expected to operate initially in the licensed 28 GHz and 39 GHz bands. A block diagram of an example baseband sub-system 110 and RFEM 115 in a mmWave system is shown in FIG. 1 A .

FIG. 1 A illustrates a mmWave system 100 A, which can be used in connection with the device 100 of FIG. 1 according to some aspects of the present disclosure. The system 100 A includes two components: a baseband sub-system 110 and one or more radio front end modules (RFEMs) 115 . The RFEM 115 can be connected to the baseband sub-system 110 by a single coaxial cable 190 , which supplies a modulated intermediate frequency (IF) signal, DC power, clocking signals and control signals.

The baseband sub-system 110 is not shown in its entirety, but FIG. 1 A rather shows an implementation of analog front end. This includes a transmitter (TX) section 191 A with an upconverter 173 to intermediate frequency (IF) (around 10 GHz in current implementations), a receiver (RX) section 191 B with downconversion 175 from IF to baseband, control and multiplexing circuitry 177 including a combiner to multiplex/demultiplex transmit and receive signals onto a single cable 190 . In addition, power tee circuitry 192 (which includes discrete components) is included on the baseband circuit board to provide DC power for the RFEM 115 . In some aspects, the combination of the TX section and RX section may be referred to as a transceiver, to which may be coupled one or more antennas or antenna arrays of the types described herein.

The RFEM 115 can be a small circuit board including a number of printed antennas and one or more RF devices containing multiple radio chains, including upconversion/downconversion 174 to millimeter wave frequencies, power combiner/divider 176 , programmable phase shifting 178 and power amplifiers (PA) 180 , low noise amplifiers (LNA) 182 , as well as control and power management circuitry 184 A and 184 B. This arrangement can be different from Wi-Fi or cellular implementations, which generally have all RF and baseband functionality integrated into a single unit and only antennas connected remotely via coaxial cables.

This architectural difference can be driven by the very large power losses in coaxial cables at millimeter wave frequencies. These power losses can reduce the transmit power at the antenna and reduce receive sensitivity. In order to avoid this issue, in some aspects, PAs 180 and LNAs 182 may be moved to the RFEM 115 with integrated antennas. In addition, the RFEM 115 may include upconversion/downconversion 174 so that the IF signals over the coaxial cable 190 can be at a lower frequency. Additional system context for mmWave 5G apparatuses, techniques and features is discussed herein below.

FIG. 2 illustrates an exemplary base station or infrastructure equipment radio head according to some aspects. The base station radio head 200 may include one or more of application processor 205 , baseband processors 210 , one or more radio front end modules 215 , memory 220 , power management integrated circuitry (PMIC) 225 , power tee circuitry 230 , network controller 235 , network interface connector 240 , satellite navigation receiver (e.g., GPS receiver) 245 , and user interface 250 .

In some aspects, application processor 205 may include one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I 2 C or universal programmable serial interface, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose 10 , memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and Joint Test Access Group (JTAG) test access ports.

In some aspects, baseband processor 210 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip sub-system including two or more integrated circuits.

In some aspects, memory 220 may include one or more of volatile memory including dynamic random access memory (DRAM) and/or synchronous DRAM (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), and/or a three-dimensional crosspoint memory. Memory 220 may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

In some aspects, power management integrated circuitry 225 may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.

In some aspects, power tee circuitry 230 may provide for electrical power drawn from a network cable. Power tee circuitry 230 may provide both power supply and data connectivity to the base station radio head 200 using a single cable.

In some aspects, network controller 235 may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

In some aspects, satellite navigation receiver 245 may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the global positioning system (GPS), Globalnaya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver 245 may provide, to application processor 205 , data which may include one or more of position data or time data. Time data may be used by application processor 205 to synchronize operations with other radio base stations or infrastructure equipment.

In some aspects, user interface 250 may include one or more of buttons. The buttons may include a reset button. User interface 250 may also include one or more indicators such as LEDs and a display screen.

FIG. 3 A illustrates exemplary mmWave communication circuitry according to some aspects; FIGS. 3 B and 3 C illustrate aspects of transmit circuitry shown in FIG. 3 A according to some aspects; FIG. 3 D illustrates aspects of radio frequency circuitry shown in FIG. 3 A according to some aspects; FIG. 3 E illustrates aspects of receive circuitry in FIG. 3 A according to some aspects. Millimeter wave communication circuitry 300 shown in FIG. 3 A may be alternatively grouped according to functions. Components illustrated in FIG. 3 A are provided here for illustrative purposes and may include other components not shown in FIG. 3 A .

Millimeter wave communication circuitry 300 may include protocol processing circuitry 305 (or processor) or other means for processing. Protocol processing circuitry 305 may implement one or more of medium access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), radio resource control (RRC) and non-access stratum (NAS) functions, among others. Protocol processing circuitry 305 may include one or more processing cores to execute instructions and one or more memory structures to store program and data information.

Millimeter wave communication circuitry 300 may further include digital baseband circuitry 310 . Digital baseband circuitry 310 may implement physical layer (PHY) functions including one or more of hybrid automatic repeat request (HARQ) functions, scrambling and/or descrambling, coding and/or decoding, layer mapping and/or de-mapping, modulation symbol mapping, received symbol and/or bit metric determination, multi-antenna port pre-coding and/or decoding which may include one or more of space-time, space-frequency or spatial coding, reference signal generation and/or detection, preamble sequence generation and/or decoding, synchronization sequence generation and/or detection, control channel signal blind decoding, and other related functions.

Millimeter wave communication circuitry 300 may further include transmit circuitry 315 , receive circuitry 320 and/or antenna array circuitry 330 . Millimeter wave communication circuitry 300 may further include RF circuitry 325 . In some aspects, RF circuitry 325 may include one or multiple parallel RF chains for transmission and/or reception. Each of the RF chains may be connected to one or more antennas of antenna array circuitry 330 .

In some aspects, protocol processing circuitry 305 may include one or more instances of control circuitry. The control circuitry may provide control functions for one or more of digital baseband circuitry 310 , transmit circuitry 315 , receive circuitry 320 , and/or RF circuitry 325 .

FIGS. 3 B and 3 C illustrate aspects of transmit circuitry shown in FIG. 3 A according to some aspects. Transmit circuitry 315 shown in FIG. 3 B may include one or more of digital to analog converters (DACs) 340 , analog baseband circuitry 345 , up-conversion circuitry 350 and/or filtering and amplification circuitry 355 . DACs 340 may convert digital signals into analog signals. Analog baseband circuitry 345 may perform multiple functions as indicated below. Up-conversion circuitry 350 may up-convert baseband signals from analog baseband circuitry 345 to RF frequencies (e.g., mmWave frequencies). Filtering and amplification circuitry 355 may filter and amplify analog signals. Control signals may be supplied between protocol processing circuitry 305 and one or more of DACs 340 , analog baseband circuitry 345 , up-conversion circuitry 350 and/or filtering and amplification circuitry 355 .

Transmit circuitry 315 shown in FIG. 3 C may include digital transmit circuitry 365 and RF circuitry 370 . In some aspects, signals from filtering and amplification circuitry 355 may be provided to digital transmit circuitry 365 . As above, control signals may be supplied between protocol processing circuitry 305 and one or more of digital transmit circuitry 365 and RF circuitry 370 .

FIG. 3 D illustrates aspects of radio frequency circuitry shown in FIG. 3 A according to some aspects. Radio frequency circuitry 325 may include one or more instances of radio chain circuitry 372 , which in some aspects may include one or more filters, power amplifiers, low noise amplifiers, programmable phase shifters and power supplies.

Radio frequency circuitry 325 may also in some aspects include power combining and dividing circuitry 374 . In some aspects, power combining and dividing circuitry 374 may operate bidirectionally, such that the same physical circuitry may be configured to operate as a power divider when the device is transmitting, and as a power combiner when the device is receiving. In some aspects, power combining and dividing circuitry 374 may include one or more wholly or partially separate circuitries to perform power dividing when the device is transmitting and power combining when the device is receiving. In some aspects, power combining and dividing circuitry 374 may include passive circuitry including one or more two-way power divider/combiners arranged in a tree. In some aspects, power combining and dividing circuitry 374 may include active circuitry including amplifier circuits.

In some aspects, radio frequency circuitry 325 may connect to transmit circuitry 315 and receive circuitry 320 in FIG. 3 A . Radio frequency circuitry 325 may connect to transmit circuitry 315 and receive circuitry 320 via one or more radio chain interfaces 376 and/or a combined radio chain interface 378 . In some aspects, one or more radio chain interfaces 376 may provide one or more interfaces to one or more receive or transmit signals, each associated with a single antenna structure. In some aspects, the combined radio chain interface 378 may provide a single interface to one or more receive or transmit signals, each associated with a group of antenna structures.

FIG. 3 E illustrates aspects of receive circuitry in FIG. 3 A according to some aspects. Receive circuitry 320 may include one or more of parallel receive circuitry 382 and/or one or more of combined receive circuitry 384 . In some aspects, the one or more parallel receive circuitry 382 and one or more combined receive circuitry 384 may include one or more Intermediate Frequency (IF) down-conversion circuitry 386 , IF processing circuitry 388 , baseband down-conversion circuitry 390 , baseband processing circuitry 392 and analog-to-digital converter (ADC) circuitry 394 . As used herein, the term “intermediate frequency” refers to a frequency to which a carrier frequency (or a frequency signal) is shifted as in intermediate step in transmission, reception, and/or signal processing. IF down-conversion circuitry 386 may convert received RF signals to IF. IF processing circuitry 388 may process the IF signals, e.g., via filtering and amplification. Baseband down-conversion circuitry 390 may convert the signals from IF processing circuitry 388 to baseband. Baseband processing circuitry 392 may process the baseband signals, e.g., via filtering and amplification. ADC circuitry 394 may convert the processed analog baseband signals to digital signals.

FIG. 4 illustrates exemplary RF circuitry of FIG. 3 A according to some aspects. In an aspect, RF circuitry 325 in FIG. 3 A (depicted in FIG. 4 using reference number 425 ) may include one or more of the IF interface circuitry 405 , filtering circuitry 410 , up-conversion and down-conversion circuitry 415 , synthesizer circuitry 420 , filtering and amplification circuitry 424 , power combining and dividing circuitry 430 , and radio chain circuitry 435 .

FIG. 5 A and FIG. 5 B illustrate aspects of a radio front end module useable in the circuitry shown in FIG. 1 and FIG. 2 , according to some aspects. FIG. 5 A illustrates an aspect of a radio front end module (RFEM) according to some aspects. RFEM 500 incorporates a millimeter wave RFEM 505 and one or more above-six gigahertz radio frequency integrated circuits (RFIC) 515 and/or one or more sub-six gigahertz RFICs 522 . In this aspect, the one or more sub-six gigahertz RFICs 515 and/or one or more sub-six gigahertz RFICs 522 may be physically separated from millimeter wave RFEM 505 . RFICs 515 and 522 may include connection to one or more antennas 520 . RFEM 505 may include multiple antennas 510 .

FIG. 5 B illustrates an alternate aspect of a radio front end module, according to some aspects. In this aspect both millimeter wave and sub-six gigahertz radio functions may be implemented in the same physical radio front end module (RFEM) 530 . RFEM 530 may incorporate both millimeter wave antennas 535 and sub-six gigahertz antennas 540 .

FIG. 6 illustrates a multi-protocol baseband processor 600 useable in the system and circuitry shown in FIG. 1 or FIG. 2 , according to some aspects. In an aspect, baseband processor may contain one or more digital baseband subsystems 640 A, 640 B, 640 C, 640 D, also herein referred to collectively as digital baseband subsystems 640 .

In an aspect, the one or more digital baseband subsystems 640 A, 640 B, 640 C, 640 D may be coupled via interconnect subsystem 665 to one or more of CPU subsystem 670 , audio subsystem 675 and interface subsystem 680 . In an aspect, the one or more digital baseband subsystems 640 may be coupled via interconnect subsystem 645 to one or more of each of digital baseband interface 660 A, 660 B and mixed-signal baseband subsystem 635 A, 635 B.

In an aspect, interconnect subsystem 665 and 645 may each include one or more of each of buses point-to-point connections and network-on-chip (NOC) structures. In an aspect, audio subsystem 675 may include one or more of digital signal processing circuitry, buffer memory, program memory, speech processing accelerator circuitry, data converter circuitry such as analog-to-digital and digital-to-analog converter circuitry, and analog circuitry including one or more of amplifiers and filters.

FIG. 7 illustrates an exemplary of a mixed signal baseband subsystem 700 , according to some aspects. In an aspect, mixed signal baseband subsystem 700 may include one or more of IF interface 705 , analog IF subsystem 710 , down-converter and up-converter subsystem 720 , analog baseband subsystem 730 , data converter subsystem 735 , synthesizer 725 and control subsystem 740 .

FIG. 8 A illustrates a digital baseband processing subsystem 801 , according to some aspects. FIG. 8 B illustrates an alternate aspect of a digital baseband processing subsystem 802 , according to some aspects.

In an aspect of FIG. 8 A , the digital baseband processing subsystem 801 may include one or more of each of digital signal processor (DSP) subsystems 805 A, 805 B, . . . 805 N, interconnect subsystem 835 , boot loader subsystem 810 , shared memory subsystem 815 , digital I/O subsystem 820 , and digital baseband interface subsystem 825 .

In an aspect of FIG. 8 B , digital baseband processing subsystem 802 may include one or more of each of accelerator subsystem 845 A, 845 B, . . . 845 N, buffer memory 850 A, 850 B, . . . 850 N, interconnect subsystem 835 , shared memory subsystem 815 , digital I/O subsystem 820 , controller subsystem 840 and digital baseband interface subsystem 825 .

In an aspect, boot loader subsystem 810 may include digital logic circuitry configured to perform configuration of the program memory and running state associated with each of the one or more DSP subsystems 805 . Configuration of the program memory of each of the one or more DSP subsystems 805 may include loading executable program code from storage external to digital baseband processing subsystems 801 and 802 . Configuration of the running state associated with each of the one or more DSP subsystems 805 may include one or more of the steps of: setting the state of at least one DSP core which may be incorporated into each of the one or more DSP subsystems 805 to a state in which it is not running, and setting the state of at least one DSP core which may be incorporated into each of the one or more DSP subsystems 805 into a state in which it begins executing program code starting from a predefined memory location.

In an aspect, shared memory subsystem 815 may include one or more of read-only memory (ROM), static random access memory (SRAM), embedded dynamic random access memory (eDRAM) and/or non-volatile random access memory (NVRAM).

In an aspect, digital I/O subsystem 820 may include one or more of serial interfaces such as Inter-Integrated Circuit (I 2 C), Serial Peripheral Interface (SPI) or other 1, 2 or 3-wire serial interfaces, parallel interfaces such as general-purpose input-output (GPIO), register access interfaces and direct memory access (DMA). In an aspect, a register access interface implemented in digital I/O subsystem 820 may permit a microprocessor core external to digital baseband processing subsystem 801 to read and/or write one or more of control and data registers and memory. In an aspect, DMA logic circuitry implemented in digital I/O subsystem 820 may permit transfer of contiguous blocks of data between memory locations including memory locations internal and external to digital baseband processing subsystem 801 .

In an aspect, digital baseband interface subsystem 825 may provide for the transfer of digital baseband samples between baseband processing subsystem and mixed signal baseband or radio-frequency circuitry external to digital baseband processing subsystem 801 . In an aspect, digital baseband samples transferred by digital baseband interface subsystem 825 may include in-phase and quadrature (I/Q) samples.

In an aspect, controller subsystem 840 may include one or more of each of control and status registers and control state machines. In an aspect, control and status registers may be accessed via a register interface and may provide for one or more of: starting and stopping operation of control state machines, resetting control state machines to a default state, configuring optional processing features, and/or configuring the generation of interrupts and reporting the status of operations. In an aspect, each of the one or more control state machines may control the sequence of operation of each of the one or more accelerator subsystems 845 . There may be examples of implementations of both FIG. 8 A and FIG. 8 B in the same baseband subsystem.

FIG. 9 illustrates a digital signal processor (DSP) subsystem 900 according to some aspects.

In an aspect, DSP subsystem 900 may include one or more of each of DSP core subsystem 905 , local memory 910 , direct memory access (DMA) subsystem 915 , accelerator subsystem 920 A, 920 B . . . 920 N, external interface subsystem 925 , power management circuitry 930 and interconnect subsystem 935 .

In an aspect, local memory 910 may include one or more of each of read-only memory, static random access memory or embedded dynamic random access memory.

In an aspect, the DMA subsystem 915 may provide registers and control state machine circuitry adapted to transfer blocks of data between memory locations including memory locations internal and external to DSP subsystem 900 .

In an aspect, external interface subsystem 925 may provide for access by a microprocessor system external to DSP subsystem 900 to one or more of memory, control registers and status registers which may be implemented in DSP subsystem 900 . In an aspect, external interface subsystem 925 may provide for transfer of data between local memory 910 and storage external to DSP subsystem 900 under the control of one or more of the DMA subsystem 915 and the DSP core subsystem 905 .

FIG. 10 A illustrates an example of an accelerator subsystem 1000 according to some aspects. FIG. 10 B illustrates an example of an accelerator subsystem 1000 according to some aspects.

In an aspect, accelerator subsystem 1000 may include one or more of each of control state machine 1005 , control registers 1010 , memory interface 1020 , scratchpad memory 1025 , computation engine 1030 A . . . 1030 N and dataflow interface 1035 A, 1035 B.

In an aspect, control registers 1010 may configure and control the operation of accelerator subsystem 1000 , which may include one or more of: enabling or disabling operation by means of an enable register bit, halting an in-process operation by writing to a halt register bit, providing parameters to configure computation operations, providing memory address information to identify the location of one or more control and data structures, configuring the generation of interrupts, or other control functions.

In an aspect, control state machine 1005 may control the sequence of operation of accelerator subsystem 1000 .

FIGS. 11 A- 11 D illustrate frame formats, according to some aspects.

FIG. 11 A illustrates a periodic radio frame structure 1100 , according to some aspects. Radio frame structure 1100 has a predetermined duration and repeats in a periodic manner with a repetition interval equal to the predetermined duration. Radio frame structure 1100 is divided into two or more subframes 1105 . In an aspect, subframes 1105 may be of predetermined duration which may be unequal. In an alternative aspect, subframes 1105 may be of a duration which is determined dynamically and varies between subsequent repetitions of radio frame structure 1100 .

FIG. 11 B illustrates a periodic radio frame structure using frequency division duplexing (FDD) according to some aspects. In an aspect of FDD, downlink radio frame structure 1110 is transmitted by a base station or infrastructure equipment to one or more mobile devices, and uplink radio frame structure 1115 is transmitted by a combination of one or more mobile devices to a base station.

A further example of a radio frame structure that may be used in some aspects is shown in FIG. 11 D . In this example, radio frame 1100 has a duration of 10 ms. Radio frame 1100 is divided into slots 1125 , 1135 each of duration 0.1 ms, and numbered from 0 to 99. Additionally, each pair of adjacent slots 1125 , 1135 numbered 2i and 2i+1, where i is an integer, is referred to as a subframe.

In some aspects, time intervals may be represented in units of T s , where T s is defined as 1/(75,000×2048) seconds. In FIG. 11 D , a radio frame is defined as having duration 1,536,600×T s , and a slot is defined as having duration 15,366×T s .

In some aspects using the radio frame format of FIG. 11 D , each subframe may include a combination of one or more of downlink control information, downlink data information, uplink control information and/or uplink data information. The combination of information types and direction may be selected independently for each subframe.

An example of a radio frame structure that may be used in some aspects is shown in FIG. 11 E , illustrating downlink frame 1150 and uplink frame 1155 . According to some aspects, downlink frame 1150 and uplink frame 1155 may have a duration of 10 ms, and uplink frame 1155 may be transmitted with a timing advance 1160 with respect to downlink frame 1150 .

According to some aspects, downlink frame 1150 and uplink frame 1155 may each be divided into two or more subframes 1165 , which may be 1 ms in duration. According to some aspects, each subframe 1165 may consist of one or more slots 1170 .

In some aspects, according to the examples of FIG. 11 D and FIG. 11 E , time intervals may be represented in units of Ts.

According to some aspects of the example illustrated in FIG. 11 D , Ts may be defined as 1/(30,720×1000) seconds. According to some aspects of FIG. 11 D , a radio frame may be defined as having duration 30,720. Ts, and a slot may be defined as having duration 15,360. Ts.

According to some aspects of the example illustrated in FIG. 11 E , Ts may be defined as Ts=1/(Δfmax·Nf), where □fmax=480×103 and Nf=4,096.

According to some aspects of the example illustrated in FIG. 11 E , the number of slots may be determined based on a numerology parameter, which may be related to a frequency spacing between subcarriers of a multicarrier signal used for transmission.

FIGS. 12 A to 12 C illustrate examples of constellation designs of a single carrier modulation scheme that may be transmitted or received according to some aspects. Constellation points 1200 are shown on orthogonal in-phase and quadrature axes, representing, respectively, amplitudes of sinusoids at the carrier frequency and separated in phase from one another by 90 degrees.

FIG. 12 A represents a constellation including two points 1200 , known as binary phase shift keying (BPSK). FIG. 12 B represents a constellation including four points 1200 , known as quadrature phase shift keying (QPSK). FIG. 12 C represents a constellation including 16 points 1200 , known as quadrature amplitude modulation (QAM) with 16 points (16QAM or QAM16). Higher order modulation constellations, comprising for example 64, 256 or 1024, points may be similarly constructed.

In the constellations depicted in FIGS. 12 A- 12 C , binary codes 1220 are assigned to the points 1200 of the constellation using a scheme such that nearest-neighbor points 1200 , that is, pairs of points 1200 separated from each other by the minimum Euclidian distance, have an assigned binary code 1220 differing by only one binary digit. For example, in FIG. 12 C the point assigned code 1000 has nearest neighbor points assigned codes 1001 , 0000 , 1100 and 1010 , each of which differs from 1000 by only one bit.

FIGS. 13 A and 13 B illustrate examples of alternate constellation designs of a single carrier modulation scheme that may be transmitted and received, according to some aspects. Constellation points 1300 and 1315 of FIG. 13 A are shown on orthogonal in-phase and quadrature axes, representing, respectively, amplitudes of sinusoids at the carrier frequency and separated in phase from one another by 90 degrees.

In an aspect, the constellation points 1300 of the example illustrated in FIG. 13 A may be arranged in a square grid, and may be arranged such that there is an equal distance on the in-phase and quadrature plane between each pair of nearest-neighbor constellation points. In an aspect, the constellation points 1300 may be chosen such that there is a pre-determined maximum distance from the origin of the in-phase and quadrature plane of any of the allowed constellation points, the maximum distance represented by a circle 1310 . In an aspect, the set of allowed constellation points may exclude those that would fall within square regions 1305 at the corners of a square grid.

Constellation points 1300 and 1315 of FIG. 13 B are shown on orthogonal in-phase and quadrature axes, representing, respectively, amplitudes of sinusoids at the carrier frequency and separated in phase from one another by 90 degrees. In an aspect, constellation points 1315 are grouped into two or more sets of constellation points, the points of each set arranged to have an equal distance to the origin of the in-phase and quadrature plane, and lying on one of a set of circles 1320 centered on the origin.

FIG. 14 illustrates an example of a system for generating multicarrier baseband signals for transmission according to some aspects. In the aspect, data 1430 may be input to an encoder 1400 to generate encoded data 1435 . Encoder 1400 may perform a combination of one or more of error detecting, error correcting, rate matching, and interleaving. Encoder 1400 may further perform a step of scrambling.

In an aspect, encoded data 1435 may be input to a modulation mapper 1405 to generate complex-valued modulation symbols 1440 . Modulation mapper 1405 may map groups including one or more binary digits, selected from encoded data 1435 , to complex valued modulation symbols according to one or more mapping tables.

In an aspect, complex-valued modulation symbols 1440 may be input to layer mapper 1410 to be mapped to one or more layer mapped modulation symbol streams 1445 . Representing a stream of complex-valued modulation symbols 1440 as d(i) where i represents a sequence number index, and the one or more streams 1445 of layer mapped symbols as x (k) (i) where k represents a stream number index and i represents a sequence number index, the layer mapping function for a single layer may be expressed as:

x (0) ( i )= d ( i )

and the layer mapping for two layers may be expressed as:

x (0) ( i )= d (2 i )

x (1) ( i )= d (2 i+ 1)

Layer mapping may be similarly represented for more than two layers.

In an aspect, one or more streams of layer mapped modulation symbol streams 1445 may be input to precoder 1415 , which generates one or more streams of precoded symbols 1450 . Representing the one or more streams 1445 of layer mapped symbols as a block of vectors:

[ x (0) ( i ) . . . x (v−1) ( i )] T

where i represents a sequence number index in the range 0 to M symb layer −1 the output is represented as a block of vectors:

[ z (0) ( i ) . . . z (P−1) ( i )] T

where i represents a sequence number index in the range 0 to M symb ap −1.

The precoding operation may be configured to include one of direct mapping using a single antenna port, transmit diversity using space-time block coding, or spatial multiplexing.

In an aspect, each stream of precoded symbols 1450 may be input to a resource mapper 1420 , which generates a stream of resource mapped symbols 1455 . The resource mapper 1420 may map precoded symbols to frequency domain subcarriers and time domain symbols according to a mapping which may include contiguous block mapping, randomized mapping or sparse mapping according to a mapping code.

In an aspect, resource mapped symbols 1455 may be input to multicarrier generator 1425 which generates time domain baseband symbol 1460 . Multicarrier generator 1425 may generate time domain symbols using, for example, an inverse discrete Fourier transform (DFT), commonly implemented as an inverse fast Fourier transform (FFT) or a filter bank including one or more filters. In an aspect, where resource mapped symbols 1455 are represented as s k (i), where k is a subcarrier index and i is a symbol number index, a time domain complex baseband symbol x(t) may be represented as x(t)=Σ k s k (i)p T (t−T sym )exp[j2πf k (t−T sym −τ k )], where p T (t) is a prototype filter function, T sym is the start time of the symbol period, □ k is a subcarrier dependent time offset, and f k is the frequency of subcarrier k.

Prototype functions p T (t) may be, for example, rectangular time domain pulses, Gaussian time domain pulses or any other suitable function.

In some aspects, a sub-component of a transmitted signal including a subcarrier in the frequency domain and a symbol interval in the time domain may be termed a resource element.

FIG. 15 illustrates resource elements 1505 depicted in a grid form, according to some aspects. In some aspects, resource elements may be grouped into rectangular blocks including a plurality of subcarriers (e.g., 12 subcarriers) in the frequency domain and the number, P, of symbols contained in one slot in the time domain. The number P may be 6, 7, or any other suitable number of symbols. In the depiction of FIG. 15 , each resource element 1505 within resource block 1500 can be indexed as (k, l) where k is the index number of subcarrier, in the range 0 to N×M−1, where N is the number of subcarriers in a resource block, and M is the number of resource blocks.

FIG. 16 A , FIG. 16 B , FIG. 16 C , and FIG. 16 D illustrate example of coding, according to some aspects. FIG. 16 A illustrates an example of coding process 1600 that may be used in some aspects. Coding process 1600 may include one or more physical coding processes 1605 that may be used to provide coding for a physical channel that may encode data or control information. Coding process 1600 may also include multiplexing and interleaving 1635 that generates combined coded information by combining information from one or more sources, which may include one of more of data information and control information, and which may have been encoded by one or more physical coding processes 1605 . Combined coded information may be input to scrambler 1640 which may generate scrambled coded information.

Physical coding process 1605 may include one or more of CRC attachment block 1610 , code block segmentation 1615 , channel coding 1620 , rate matching 1625 , and code block concatenation 1630 . CRC attachment block 1610 may calculate parity bits denoted {p 0 , p 1 , . . . , p L-1 } from input bits denoted {a 0 , a 1 , . . . a A−1 } to generate a sequence of output bits {b 0 , b 1 , . . . , b A+L−1 }, such that the polynomial over the finite field GF(2) in the variable D using the output sequence bits as coefficients (i.e., polynomial b 0 D A+L−1 +b 1 D A+L−2 + . . . +b A+L−2 D 1 +b A+L−1 ), has a predetermined remainder when divided by a predetermined generator polynomial g(D) of order L. In an aspect, the predetermined remainder may be zero, L may be 24 and the predetermined polynomial g(D) may be D 24 +D 23 +D 18 +D 17 +D 14 +D 11 +D 10 +D 7 +D 6 +D 5 +D 4 +D 3 +D+1.

In some aspects, the process of code block segmentation 1615 may generate one or more segmented code blocks, each including a portion of the data input to code segmentation 1615 . Code block segmentation 1615 may have minimum and maximum block size constraints as parameters, determined according to a selected channel coding scheme. Code block segmentation 1615 may add filler bits to one or more output segmented code blocks, in order to ensure that the minimum block size constraint is met. Code block segmentation 1615 may divide data input to the process into blocks in order to ensure that the maximum block size constraint is met. In some aspects, code block segmentation 1615 may append parity bits to each segmented code block. Such appending of parity bits may be determined based on one or more of the selected coding scheme and whether the number of segmented code blocks to be generated is greater than one.

In some aspects, the process of channel coding 1620 may generate code words from segmented code blocks according to one or more of a number of coding schemes. As an example, channel coding 1620 may make use of one or more of convolutional coding, tail biting convolutional coding, parallel concatenated convolutional coding and polar coding.

An encoder 1620 that may be used to encode data according to one of a convolutional code and a tail-biting convolutional code according to some aspects is illustrated in FIG. 16 B .

According to some aspects, input data 1645 may be successively delayed by each of two or more delay elements 1650 , generating a data word consisting of elements that include the current input data and two or more copies of the current input data, each copy delayed respectively by a different number of time units. According to some aspects, encoder 1620 may generate one or more outputs 1660 , 1665 and 1670 , each generated by calculating a linear combination of the elements of a data word generated by combining input data 1645 and the outputs of two or more delay elements 1650 .

According to some aspects, the input data may be binary data and the linear combination may be calculated using one or more exclusive or functions 1655 . According to some aspects, encoder 1620 may be implemented using software running on a processor and delay elements 1650 may be implemented by storing input data 1645 in a memory.

According to some aspects, a convolutional code may be generated by using convolutional encoder 1620 and initializing delay elements 1650 to a predetermined value, which may be all zeros or any other suitable value. According to some aspects, a tail-biting convolutional code may be generated by using convolutional encoder 1620 and initializing delay elements 1650 to the last N bits of a block of data, where N is the number of delay elements 1650 .

An encoder 16 C 100 that may be used to encode data according to a parallel concatenated convolutional code (PCCC) that may be referred to as a turbo code, according to some aspects is illustrated in FIG. 16 C .

According to some aspects, encoder 16 C 100 may include an interleaver 16 C 110 , upper constituent encoder 16 C 115 and lower constituent encoder 16 C 117 . According to some aspects, upper constituent encoder 16 C 115 may generate one or more encoded data streams 16 C 140 and 16 C 145 from input data 16 C 105 . According to some aspects, interleaver 16 C 110 may generate interleaved input data 16 C 119 from input data 16 C 105 . According to some aspects, lower constituent encoder 16 C 117 may generate one or more encoded data streams 16 C 150 and 16 C 155 from interleaved input data 16 C 105 .

According to some aspects, interleaver 16 C 110 may output interleaved output data 16 C 119 that has a one to one relationship with the data contained in input data 16 C 105 , but with the data arranged in a different time order. According to some aspects, interleaver 16 C 110 may be a block interleaver, taking as input one or more blocks of input data 16 C 105 , which may be represented as {c 0 , c 1 , . . . , c K−1 }, where each ci is an input data bit and K is the number of bits in each block, and generating an output corresponding to each of the one or more such input blocks, which may be represented as {c Π(1) , c Π(2) , . . . , c Π(K−1) }. Π(i) is a permutation function, which may be of a quadratic form and which may be represented by Π(i)=(f 1 i+f 2 i 2 ) mod K, where f 1 and f 2 are constants that may be dependent on the value of the block size K.

According to some aspects, each of upper constituent encoder 16 C 115 and lower constituent encoder 16 C 117 may include input bit selector 16 C 118 which may generate a selected input bit stream 16 C 119 that may be selected from one of an encoder input bit stream during a data encoding phase and a linear combination of stored bits during a trellis termination phase. According to some aspects, each of upper constituent encoder 16 C 115 and lower constituent encoder 16 C 117 may store bits in two or more delay elements 16 C 120 arranged to function as a shift register, the input to the shift register consisting of a linear combination of a bit from a selected input bit stream 16 C 119 and previously stored bits, the stored bits being initialized to a predetermined value prior to an encoding phase, and having a predetermined value at the end of a trellis termination phase. According to some aspects, each of upper constituent encoder 16 C 115 and lower constituent encoder 16 C 117 may generate one or more outputs 16 C 140 and 16 C 145 , each of which may be one of a selected input bit stream 16 C 119 and a linear combination of stored bits.

According to some aspects, each of upper constituent encoder 16 C 115 and lower constituent encoder 16 C 117 may have a transfer function during an encoding phase that may be represented as

According to some aspects, encoder 16 C 100 may be implemented as software instructions running on a processor in combination with memory to store data input to interleaver 16 C 110 and stored bits of each of upper constituent encoder 16 C 115 and lower constituent encoder 16 C 117 .

An encoder 16 D 200 that may be used to encode data bits according to a low density parity check (LDPC) code according to some aspects is illustrated in FIG. 16 D .

According to some aspects, data bits 16 D 230 input to encoder 16 D 200 may be stored in data store 16 D 210 , stored data bits may be input to parity bit generator 16 D 220 and encoded bits 16 D 240 may be output by parity bit generator 16 D 220 .

According to some aspects, data bits input to LDPC encoder 16 D 200 may be represented as c={c 0 , c 1 , . . . , c K−1 }, encoded data bits 16 D 240 may be represented as d={c 0 , c 1 , . . . , c K−1 , p 0 , p 1 , . . . , p D−K−1 }, and parity bits pi may be selected such that H. d T =0, where H is a parity check matrix, K is the number of bits in the block to be encoded, D is the number of encoded bits and D−K is the number of parity check bits.

According to an aspect, parity check matrix H may be represented as:

H = [ p a 0 , 0 p a 0 , 1 p a 0 , 2 p a 0 , M - 2 p a 0 , M - 1 p a 1 , 0 p a 1 , 1 p a 1 , 2 ⋯ p a 1 , M - 2 p a 1 , M - 1 p a 2 , 0 p a 2 , 1 p a 2 , 2 p a 2 , M - 2 p a 1 , M - 1 ⋮ ⋱ p a N - 1 , 0 p a N - 1 , 1 p a N - 1 , 2 p a N - 1 , M - 2 p a N - 1 , M - 1 ] ,

where p a ij is one of a zero matrix or a cyclic permutation matrix obtained from the Z×Z identity matrix by cyclically shifting the columns to the right by ai,j, Z is the size of the constituent permutation matrix, the number of encoded bits D is equal to ZM and the number of bits K in the block to be encoded is equal to ZN.

Digital polar transmitters (DTxs), whose inputs may be amplitude and phase, may be a promising architecture for integrated Complementary Metal-Oxide-Semiconductor (CMOS) radios used in devices communicating through the next generation systems as such devices offer, for example, the potential for higher efficiency and system-on-a-chip (SoC) integration. DTxs may use amplitude variation and phase variation of an output signal to provide data. However, DTxs, like other transmitters, have been restricted to lower frequencies (typically <6 GHz) due to challenges of implementing wideband phase modulators at the mmWave frequencies used in the next generation systems as well as implementing DTxs at mmWave speeds. The channel bandwidth for the next generation systems may be in the order of 100 MHz-GHz and employ one or both single carrier (SC) and Orthogonal frequency-division multiplexing (OFDM)-based modulations. This is to say that while a fundamental oscillation may be produced over the various channel frequencies, adjusting the amplitude and phase at the higher frequencies is a consideration.

Additionally, with the use of mmWave frequencies, the power efficiency of the DTxs may be substantially reduced at such frequencies due to the discrepancy in amplitude variation and corresponding peak power efficiency between mmWave frequency signals and lower frequency signals. OFDM may impose additional spectral limitations on the phase modulation signals produced by the DTxs. In order to meet the link budget with the higher propagation losses at the higher mmWave frequencies, such links may rely on phased arrays and multi-user Multiple Input Multiple Output (MIMO) in order to optimize the use of spatial channels across multiple users. In practical terms, the use of phased arrays may mean that multiple transmit and receive chains are used on each device, further increasing the transmission power used in addition to encountering the above power inefficiencies. Therefore, it could be useful to improve the DTx efficiency at mmWave frequencies.

In an aspect, to help ameliorate these issues, a wideband phase modulator architecture is provided that may be suitable for both single-carrier and OFDM based-mmWave DTxs. The wideband phase modulator architecture may contain multiple parallel transmission chains for phased arrays and MIMO/MU-MIMO. Phase modulators can incorporate phase shifts for implementing the phased array.

In an aspect, the DTx may use phase and amplitude extraction that supports low operator-sum representation (OSR) polar decomposition of wide bandwidth RF signals. A digital-to-time converter (DTC)-based phase modulator may be used that is clocked in the low-GHz frequency band for practical considerations (feasibility, timing margins, power dissipation etc.). Time interleaving may be used between multiple DTCs to increase the clock frequency to up to about 10 GHz. In addition, a sub-harmonic series injection into mmWave LC oscillators may be used to up-convert the modulation to RF frequencies.

RF communication systems often times utilize sub-systems (e.g., voltage controlled oscillators (VCOs), power amplifiers) that are formed on a semiconductor die. More specifically, various electronic elements (e.g., capacitors and inductors) of such sub-systems are printed on the semiconductor die. However, the resistance that is inherent with the silicon of the semiconductor die significantly reduces the quality (Q) factor (ratio of inductance divided by resistance) of the inductors printed on the die.

FIG. 17 is a cross-sectional view 1702 and a top view 1704 of a semiconductor die with metallic pillars according to some aspects. Referring to FIG. 17 , the semiconductor die 1706 includes a plurality of pillars 1708 . The semiconductor die 1706 may be incorporated in the RF circuitry 325 of mmWave communication circuitry 300 shown in FIG. 3 A , although the semiconductor die 1706 is not limited to such.

In an aspect, the pillars 1708 can be copper pillars, which can be used for RF connections to the die. More specifically, copper pillars can be used as metallic structures to connect semiconductor die 1706 to a semiconductor die packaging (not illustrated). In some aspects, other metallic structures can be used as pillars 1708 , such as solder based bumps and balls. The copper pillars 1708 can be attached to the semiconductor die 106 via metalized contact pads (or contacts) 1710 . In some aspects, the copper pillars 1708 can be created in one continuous etching process where the unwanted copper is etched away leaving only copper pillars 1708 attached to the die metalized contacts 1710 .

FIG. 18 A provides a cross-sectional view 1802 A and a top view 1804 A of a semiconductor die 1806 with metallic pillars 1808 forming a first type of interconnect structures according to some aspects. Referring to the cross-sectional view 1802 A, metallic pillars 1808 can be formed in accordance with a multi-stage build up and etching process. More specifically, metallic pillars 1808 can be built up and etched in stages on die metallized contacts 1810 , where a separate metallized layer is created during each build up and etching stage. As seen in FIG. 18 A , during a first etching stage, a metallized layer 1812 is created. During an additional build up and etching stage, interconnect structures can be created between at least 2 of the pillars. For example, during an etching stage creating metallized layer 1814 , an interconnect structure 1822 A can be formed by the metallized material used for layer 1814 . During such etching stage, the metallized material for layer 1814 is not etched between at least two of the pillars so that an interconnect structure is formed by the layer 1814 connecting the at least two pillars.

During a subsequent build up and etching stage, a metallized layer 1816 is disposed on top of layer 1814 (no metallized interconnect structures are associated with layer 1816 ). During a subsequent build up and etching stage creating metallized layer 1818 , an interconnect structure 1824 A can be formed by the metallized material used for layer 1818 . During a final etching stage, a metallized layer 1820 is disposed on top of layer 1818 , where no metallized interconnect structures are associated with layer 1820 .

In some aspects, the interconnect structures 1822 A and 1824 A can serve as high quality (Q) factor inductive elements that are directly connected to the semiconductor die 1806 contacts and can serve RF circuitry that can benefit from such high-Q inductors. Example RF circuitry can include oscillators, power amplifiers, low noise amplifiers, and other circuitry, which can be partially or fully integrated within the semiconductor die 1806 .

In some aspects, the interconnect structure 1822 A can be located at position 1832 , away and separate from the interconnect structure 1824 A. In another example, the interconnect structure 1822 A can be located side-by-side and/or partially overlapping, as seen at position 1830 . In some aspects, selection of the interconnect structure to be at position 1830 or 1832 can be based on the resulting coupling and mutual inductance associated with interconnect structures 122 A and 1824 A. In this case, when the two interconnects are located side-by-side and/or partially overlapping, a coupling zone 1826 is created between the interconnect structures. Such coupling zone can be used in designing high-Q inductive elements implemented at least partially by the interconnect structures associated with the metallic pillars 1808 .

In some aspects, lateral parallel coupling (e.g., 1826 ) can be achieved when the interconnect structures (e.g., 1824 A and 1822 A) are created using the same pillar layer (or etching stage), or the interconnect structures are created using different pillar layers.

In some aspects, more than two interconnect structures can be formed using one or more of the layers 1812 through 1820 associated with pillars 1808 . Additionally, interconnect structures can be separated by air gaps as illustrated in FIG. 18 A . More specifically, the interconnect structure 1822 A is separated by an air gap 1807 from the semiconductor die 1806 . The interconnect structure 1822 A is also separated from the interconnect structure 1824 A by another air gap 1809 formed within layer 1816 .

In some aspects, an interconnect structure can be formed using the last layer 1820 of pillars 1808 . In this regard, when an interconnect structure is disposed on the last layer 1820 , interconnect structure will be in direct contact with the package laminate (which is illustrated as 1902 in FIG. 19 ) on which the die is attached, or the interconnect structures can be isolated from the laminate and can close a circuit directly on the die.

FIG. 18 B is a cross-sectional view 1802 B and a top view 1804 B of a semiconductor die 1806 with metallic pillars 1808 forming a second type of interconnect structures according to some aspects. The process of creating the metallized pillars illustrated in FIG. 18 B can be the same as described in reference to FIG. 18 A except the interconnect structures 1822 B and 1824 B can have different shapes and locations on the semiconductor die 1806 , in comparison with interconnect structures 1822 A and 1824 A.

Referring to FIG. 18 B , the interconnect structures 1822 B and 1824 B can form winding-like inductive elements, which can be used with various inductive implementations including transformer implementations. In some aspects, interconnect structures 1824 B and 1822 B can be elements within a primary and/or a secondary winding of a transformer. Additionally, the interconnect structures 1822 B and 1824 B can partially or completely overlap so that a coupling zone 1834 is created.

FIG. 18 C is a cross-sectional view 1802 C and a top view 1804 C of a semiconductor die 1806 with metallic pillars forming a third type of interconnect structures 1822 C and 1824 C according to some aspects. More specifically, the interconnect structures 1822 C and 1824 C can be disposed on the same layers 1814 and 1818 respectively as illustrated in FIG. 18 A . However, the interconnect structures 1822 C and 1824 C can cross over each other.

FIG. 19 is a cross-sectional view 1900 of a semiconductor die with metallic pillars forming interconnect structures where the pillars are attached to a package laminate according to some aspects. More specifically, the semiconductor die 1906 can include the metallic pillars 1908 formed by layers 1912 , 1914 , 1916 , 1918 , and 1920 . The semiconductor die 1906 can include the interconnect structures 1822 A and 1824 A formed as illustrated in FIG. 18 A . The metallic pillars 1908 can be attached to the semiconductor die 1906 using connection paths 1910 . Additionally, the metallic pillars 1808 can be attached to a package laminate 1902 using connector pads 1904 .

Physical space in mobile devices for wireless communication is at a premium because of the amount of functionality that is included within the form factor of such devices. Challenging issues arise, among other reasons, because of need to provide spatial coverage of radiated radio waves, and maintain signal strength as the mobile device is moved to different places, and also because a user may orient the mobile device differently from time to time, leading to the need, in some aspects, for varying polarities and varying spatial diversity of the radiated radio wave at varying times.

When designing packages that include antennas operating at millimeter wave (mmWave) frequencies, efficient use of space can help resolve issues such as the number of antennas needed, their direction of radiation, their polarization, and similar needs. Efficient use of a multi-layer laminate structure, such as a PCB, within the chassis of a wireless communication mobile device can be used effectively by including a cavity inside the laminate structure for placement of the RFIC transceiver die, and perhaps for placement of discrete components of the device. In some aspects, the die may be a flip-chip (FC) die. The laminate structure can include a sub-system where antennas may be embedded in the layer structure and can be implemented on top, on bottom, and on sides of the sub-system for larger spatial coverage.

FIG. 20 A is a cross-sectional, side view of a user device sub-system as described in this disclosure according to some aspects. The user device sub-system is identified as 2000 . The user device sub-system 2000 may be incorporated in the RF circuitry 325 and the antenna array circuitry 330 of mmWave communication circuitry 300 shown in FIG. 3 A , although the user device sub-system 2000 is not limited to such.

In some aspects, the laminate structure 2001 includes a cavity 2003 . The cavity, in which the RFIC and accompanying components can reside, can be formed by stacking layers of laminates with window openings on top of other laminate layers with the FC die and discreet components until the desired height clearance above the FC die and discreet components is reached. Then it may be covered with one or more full layers to close the cavity, giving the cavity a “roof.” Directional terms such as “top,” “bottom,” “sides,” and “roof” are used herein relative to the orientation of the drawing. The cavity can be large enough to enable the FC die and any discrete components to fit inside the cavity whilst also accounting for manufacturing design rules (e.g., assembly accuracies). Each assembly house may have different design rules, which may also be a function of the actual materials involved. For example, the rules for a bismaleimide triazine (BT) laminate material might be very different from those of FR4 laminate material.

In some aspects, the RFIC die 2006 is implemented within a cavity 2003 and, in some aspects, secured to the floor of the cavity by solder bumps 2005 , which may be reflow solder bumps in some aspects. Other types of bumps may be used such as thermosonic, thermocompression and adhesively bonded bumps. In some aspects, these also serve as the electrical interface of the RFIC die 2006 to the laminate printed circuitry. In some aspects, up-facing wire bonding can also be used to electrically connect the RFIC to the printed circuit in the laminate. Discrete components 2007 may also be included within the cavity if appropriate for the implementation.

In some aspects, surrounding the die and discrete components is ground cage 2008 , described in additional detail below, which may be used as a shield to protect the circuitry from radio frequency interference (RFI) and electromagnetic interference (EMI). The RFIC that is placed in the cavity would be encased in the described ground cage with the aid of the metalized ground layers, ground planes and vias running between the layers to protect from RFI/EMI. Typically RF chips and circuitry need to be shielded from an RFI/EMI point of view to meet regulatory requirements. Here the implementation takes advantage of the fact that the RF circuitry is embedded within a cavity that can be encompassed by metallization using layers of the laminate device and vias as appropriate, thus making a Faraday Cage, which is a shield.

With the components embedded within the cavity that is shielded, the antennas can be implemented around the outside of the shielded enclosure as discussed below, and thereby take advantage of the fact these antennas can be embedded/printed or assembled on or within the PCB from multiple sides to enable greater spatial coverage of the antennas. From the antenna point of view, the shield cage in the laminate structure could serve as the antenna ground or as a reflector to increase the antenna gain and create a more directed radiation pattern. In addition, the cavity serves as physical protection of the RFIC itself as well as any other circuitry inside the cavity.

Antenna elements 2011 A through 2011 G are implemented within the sub-system, according to some aspects. The antennas could be of various types. For instance, patch antennas may be implemented on the top and bottom of the structure, facing up and down, respectively, with dipole antennas on the sides, such as at 2011 G. Other antenna types are possible. In some aspects, the side antennas would be implemented on three sides since the exposed electrical contacts could be on one side, as discussed further below.

In some aspects, antenna elements 2011 A- 2011 C are implemented facing “down”. Antenna elements 2011 D- 2011 F are placed at the top of the structure facing “up.” Each of antennas 2011 A- 2011 G could be a plurality of antenna elements. For example, 2011 A 1 to 2011 AN can be used to designate antenna elements 2011 A as N antenna elements, which may be an array, in some aspects. In other words, in some aspects an antenna illustrated as, for example, 2011 A, may also be an N element antenna array such as 2011 A- 1 , . . . , 2011 AN. Further, there may be arrays 2011 D 1 - 2011 DN. Further still, the antenna elements in such arrays may be distributed on both the top and bottom surface of laminate structure 2001 in different formations, such as some of antenna elements 2011 C 1 - 2011 CN and 2011 E 1 - 2011 EN being in a single array.

In some aspects, antenna element 2011 G may be placed sideways and may be configured for edge-fire or end fire radiation. Nomenclature 2011 G 1 - 2011 GN could be used to indicate there may be N antenna elements 2011 G (looking “into” the page or out of the page, hidden by the sectioning) which may be in an array. Transmission lines 2009 A- 2009 G may be traces that provide RF connection from the RFIC die to/from the antennas. If the antenna that is fed is actually an antenna array, for example 2011 A 1 - 2011 AN, the RF traces feeding the array could be an array of RF traces which may be designated 2009 A 1 , . . . , 2009 AN, in some aspects. RF traces from the RFIC can feed the various antenna elements through the layer structure both laterally along a given layer or through vias to reach other layers. The RF traces can be micro strips, strip line, or other suitable conductors. The RF traces to the antennas can come through openings in the shielded cavity 2003 in some aspects. Some sections of these RF feeds can be inside the cavity and some outside in some aspects. While illustrated here as running outside the cavity, alternate aspects can have the RF traces first run inside the cavity 2003 , even vertically, and then pierce through an opening (via hole or lateral trace) in the shield cage at the top (or side) to reach an antenna element. This is discussed in additional detail with respect to FIGS. 20 B and 21 below.

The layer 2013 of the multi-layer laminate structure indicates a layer at which electrical contacts that connect the RFIC electrically to appropriate parts of the system to outside the cavity may be implemented, according to some aspects. These contacts are discussed below in connection with FIG. 20 B . In this instance, the electrical contacts (not shown at 2013 of FIG. 20 A ) would be into the page or out of the page (for example, hidden behind the section view).

FIG. 20 B illustrates a pedestal part of the laminate structure of FIG. 20 A , according to some aspects. FIG. 20 B illustrates pedestal 2021 discussed briefly above. The section illustration of FIG. 20 A is taken with reference to Section 20 A- 20 A illustrated in FIG. 20 B . Electrical contacts 2023 seen in FIG. 20 B are the same electrical contacts discussed as implemented at layer 2013 in FIG. 20 A , in some aspects. Other layers may be used for this implementation.

The cavity 2003 is shown in hidden line as disposed within the laminate structure, illustrated as configured within pedestal 2021 . The pedestal can serve as the surface for electrical contacts and be used as the attachment method to a motherboard (MB) to which the laminate structure may be connected. The electrical contacts 2023 may also serve as the thermal conduit from the sub-system to the MB. The MB would have the appropriate complementary contacts, placed as discussed above with respect to layer 2013 (as one example) of FIG. 20 A , according to some aspects, so that the sub-system can be easily attached to the MB and make appropriate interfaces to the MB, both electrically and thermally. The electrical contacts that would be plugged into an appropriate socket are, in some aspects, the only mechanical connection from the RFIC die to the MB. Alternatively, these could be directly solder attached to the MB with the appropriate complementary contacts. Generally, heat needs good metal to conduct, and these exposed electrical contacts 2023 can also serve as the heat sinking path pulling heat from the die inside the cavity along the metallization of the routing, in many cases using the ground layers of the multi-layer structure, in some aspects. While there is a certain amount of heat also conducted through the PCB material, this type of heat exchange is not as efficient as the metalized contacts for heat transfer.

As discussed briefly above, the RF traces that feed the antennas can come through openings in the shielded cavity 2003 . Some sections of these RF feeds can be inside the cavity and some outside. While illustrated here as running outside the cavity, alternate aspects can have the RF traces first run inside the cavity 2003 , even vertically, and then pierce through an opening (via hole or lateral trace) in the shield cage at the top (or side) to reach an antenna element, according to some aspects. This can be seen in FIGS. 21 and 22 . FIG. 21 illustrates RF feeds inside the cavity of the laminate structure of FIG. 20 A , according to some aspects. Cavity 2103 is similar to cavity 2003 in the laminate structure of FIG. 20 A . Ground plane layer 2113 that can ground the shield 2108 , is a ground layer on top of the structure illustrated in the drawing, which makes contact with vertical vias, which are not shown for purposes of clarity. Ground layer 2108 is illustrated in dotted line to indicate its presence in the laminate structure illustrated.

In some aspects, vertical ground vias 2110 are situated around the periphery of the cavity 2103 and can be part of the Faraday cage discussed above. RF traces 2109 A, 2109 B, 2109 C, 2109 D, and 2109 E are configured on electrically connected to RFIC die 2106 , which may be beneath the ground plane on another layer inside the cavity 2103 . The RF traces include RF feeds for antennas configured on or internal to the laminate structure 2001 of FIG. 20 A . The RF traces 2009 A, 2009 B and 2009 C can run internal to cavity 2003 and escape laterally out of the ground cage (described in FIG. 20 A ) between the vias to feed antenna elements 2011 A, 2011 B, and 2011 C, according to some aspects.

These antenna elements 2011 A, 2011 B, and 2011 C may be edge-fire antenna elements, illustrated as dipoles in one example. RF traces 2109 D and 2109 E pierce through the ground shield by use of vias 2112 D and 2112 E, according to some aspects. This is seen more clearly in FIG. 22 . FIG. 22 illustrates RF feed traces transitioning vertically through a ground plane layer, according to some aspects. RF traces 2209 D and 2209 E pierce through the ground plane layer by way of holes or openings 2212 D 2 , 2212 E 2 in the metallization to allow the signal via to go through to reach from die 2206 to antennas or antenna elements 2211 D and 2211 E, respectively (in some aspects by way of vias 2212 D 1 and 2212 E 1 ). Antennas, or antenna elements, 2211 D and 2211 E are shown in dotted line to indicate they can be at an appropriate level of the laminate structure 2001 , according to some aspects. Antennas, or antenna elements, 2211 D and 2211 E are illustrated as patch antennas but may be any appropriate antenna or antenna element. Vias 2212 D 1 and 2212 E 1 are shown as oversize to indicate that each can connect to the appropriate level of the laminate structure 2001 to feed antennas 2211 D and 2211 E, either directly or, in some aspects, via an additional RF trace connecting the via to the antenna.

RF communication systems oftentimes utilize sub-systems (e.g., voltage controlled oscillators (VCOs), power amplifiers, transceivers, modems, and so forth) that are formed on a semiconductor die. Oftentimes, the packaged chip has limited space to locate antenna elements, especially in instances when multiple types of signal communication systems are implemented on a single chip.

FIG. 23 illustrates multiple views of a semi-conductor package 2300 with co-located mmWave antennas and a near field communication (NFC) antenna according to some aspects. The semi-conductor package 2300 may be incorporated in the antenna array circuitry 330 of mmWave communication circuitry 300 shown in FIG. 3 A , although the semi-conductor package 2300 is not limited to such.

Referring to FIG. 23 , the semi-conductor package 2300 can be implemented on a PCB substrate 2302 . The PCB substrate can include a component side 2302 A and a printed side 2302 B. In some aspects, the component side 2302 A can include one or more circuits (or sub-systems) performing signal processing functionalities. For example, the component side 2302 A can include an RF front-end module (RFEM) 2310 and a baseband sub-system (BBS) 2312 . The RFEM 2310 and the BBS 2312 are illustrated in greater detail in FIG. 26 and FIG. 27 , respectively. In some aspects, The PCB substrate can also include near-field communication (NFC) sub-system 2318 , which can be configured to receive and transmit NFC signals.

In some aspects, the RFEM 2310 may include suitable circuitry, logic, interfaces and/or code and can be configured to process one or more intermediate frequency (IF) signals generated by the BBS 2312 for transmission using a phased antenna array. The RFEM 2310 can also be configured to receive one or more RF signals via the phased antenna array, and convert the RF signals into IF signals for further processing by the BBS 2312 .

In some aspects, the RFEM 2310 can be configured to process mmWave signals in one or more mmWave bands. Additionally, the phased antenna array (or a subset of the phased antenna array) can be implemented as antenna array 2316 on the printed side 2302 B of the PCB substrate 2302 . Even though four patch antennas are illustrated as the phased antenna array 2316 , the disclosure is not limited in this regard, and other types (and a different number) of antennas can be used as the phased antenna array 2316 . Additionally, the phased antenna array 2316 can be used to transmit and receive mmWave signals or other types of wireless signals.

In some aspects, the phased antenna array 2316 can be co-located with a Near Field Communication (NFC) antenna 2314 . As seen in FIG. 23 , the NFC antenna 2314 can be implemented as an inductor element, disposed around the phased antenna array 2316 , on the printed side 2302 B of the PCB substrate 2302 . In some aspects, the NFC antenna 2314 can include multiple inductor elements (e.g., a multi-layer inductor), which can be co-located with the phased antenna array 2316 .

In some aspects, the RFEM 2310 and the BBS 2312 can be used for processing wireless signals in connection with one or more wireless standards or protocols in one or more communication networks. Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., networks using Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16 family of standards known as WiMax®, IEEE 802.15.4 family of standards, a Long Term Evolution (LTE) family of standards, 5G wireless communications standards or protocols (including communications in the 28 GHz, 37 GHz, and 39 GHz communication bands), a Universal Mobile Telecommunications System (UMTS) family of standards, peer-to-peer (P2P) networks, among others.

FIG. 24 illustrates a radio frequency front-end module (RFEM) with a phased antenna array according to some aspects. Referring to FIG. 24 , there is illustrated the RFEM 2310 using an example phased antenna array implemented on both sides of the PCB substrate 2302 . More specifically, the phased antenna array 2400 can include a first plurality of antennas 2402 - 2408 , a second plurality of antennas 2410 - 2414 , a third plurality of antennas 2416 - 2422 , a fourth plurality of antennas 2424 - 2428 , a fifth plurality of antennas 2432 , and a sixth plurality of antennas 2434 .

In some aspects, the antennas 2402 through 2428 and 2432 can be disposed on one side of the PCB substrate 2302 . The sixth plurality of antennas 2434 can be disposed on an opposite side of the PCB substrate 2302 (e.g., similarly to antenna array 2316 illustrated in FIG. 23 ). In some aspects, the first, second, third, and fourth plurality of antennas 2402 - 2428 can be disposed along the four corresponding edges of the PCB substrate 2302 (as seen in FIG. 24 ). The fifth plurality of antennas 2432 can be disposed at an area that is remote from the edges of the PCB substrate 2302 . The PCB substrate 2302 can also include a connection terminal 2430 , which can be used as a feed line for the phased antenna array 2400 . In this regard, the phased antenna array that includes antennas 2402 - 2428 , 2432 , and 2434 can provide signal coverage in a North, South, West, East, upwards, and downward direction relative to the PCB substrate 2302 .

In some aspects, the phased antenna array that includes antennas 2402 - 2428 , 2432 , and 2434 can include different types of antennas, such as dipole antennas and patch antennas. In some aspects, the phased antenna array can be implemented using other types of antennas as well. In some aspects, one or more of the antennas of the phased antenna array 2400 can be implemented as part of the RFEM 2310 . Additionally, the PCB substrate 2302 can include a NFC antenna (not illustrated in FIG. 24 ), which can be co-located with one or more of the antennas of the phased antenna array 2400 . For example, the NFC antenna can be co-located with antennas 2434 on the same side of the PCB substrate 2302 .

FIG. 25 illustrates exemplary locations of a RFEM in a mobile device according to some aspects. Referring to FIG. 25 , there is illustrated a mobile device 2500 which includes multiple RFEMs 2502 . Each RFEM 2502 can include co-located NFC antenna and mmWave phased array antenna, e.g., as illustrated in FIG. 23 . As seen in FIG. 25 , each RFEM 2502 can be away from the screen area (e.g., in a bezel area) so that antenna coverage is provided from one RFEM in instances when another RFEM is covered by a human hand.

FIG. 26 is a block diagram of an exemplary RFEM according to some aspects. Referring to FIG. 26 , the RFEM 2310 is coupled to the BBS 2612 via a coax cable 2612 . The RFEM 2610 can include a phased antenna array 2602 , a RF receiver 2604 , a RF transmitter 2606 , a LO generator 2608 , a triplexer 2610 , and a switch 2603 . The RF receiver 2604 can include a plurality of power amplifiers 2616 , a plurality of phase shifters 2618 , and adder 2620 , and amplifier 2622 , and amplifier 2626 , and a multiplier 2624 . The RF transmitter 2606 can include a multiplier 2638 , amplifiers 2636 and 2640 , an adder 2634 , a plurality of phase shifters 2632 , and a plurality of amplifiers 2630 . The RFEM 2310 can further include intermediate frequency (IF) amplifiers 2627 and 2641 .

In an example receive operation, the switch 2603 can activate receiver chain processing. The phased antenna array 2602 can be used for receiving a plurality of signals 2614 . The receive signals 2614 can be amplified by amplifiers 2616 and the phase can be adjusted by corresponding phase shifters 2618 . Each of the phase shifters 2618 can receive a separate phase adjustment signal (not illustrated in FIG. 26 ) from a control circuitry, where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 2602 . The phase adjusted signals at the output of the phase shifters 2618 can be summed by the adder 2620 and then amplified by the amplifier 2622 . The LO generator 2608 can generate a LO signal, which can be amplified by the amplifier 2626 and then multiplied with the output of amplifier 2622 using the multiplier 2624 in order to generate an IF output signal. The IF output signal can be amplified by amplifier 2627 and they communicated to the BBS 2312 via the triplexer 2610 and the coax cable 2612 .

In an example transmit operation, the switch 2603 can activate transmitter chain processing. The RFEM 2310 can receive an IAF signal from the BBS 2312 via the coax cable 2612 and the triplexer 2610 . The IAF signal can be amplified by amplifier 2641 and then communicated to multiplier 2638 . The multiplier 2638 can receive an up-conversion LO signal from the LO generator 2608 and the amplifier 2640 . The amplified LO signal is multiplied with the received IF signal by the multiplier 2638 . The multiplied signal is then amplified by amplifier 2636 and communicated to adder 2634 . The adder 2634 generates multiple copies of the amplified signal and communicates signal copies to the plurality of phase shifters 2632 . The plurality of phase shifters 2632 can apply different phase adjustment signals to generate a plurality of phase adjusted signals which can be amplified by the plurality of amplifiers 2630 . The plurality of amplifiers 2630 generates a plurality of signals 2628 for transmission by the phased antenna array 2602 .

In some aspects, the LO generator 2608 can be shared between processing mmWave wireless signals (or other types of signals) by the RFEM 2310 and processing NFC signals by the NFC sub-system 2318 . For example, the NFC sub-system 2318 can use this LO generation signal at the output of the LO generator 2608 (after dividing it) for up-conversion or down-conversion, as needed. In another example, the NFC sub-system 2318 can use the LO generation signal for direct generation of the NFC data by using the LO signal (e.g., by multiplying the LO signal by the NFC data).

In some aspects, other circuits/sub-systems within the RFEM 2310 or the BBS 2312 can be shared with the NFC sub-system 2318 . For example, the RFEM 2310 or the BBS 2312 can include a power management unit (PMU) (not illustrated), which can be shared with the NFC sub-system 2318 . In some aspects, the PMU can include DC-to-DC sub-systems (e.g., DC regulators), voltage regulators, bandgap voltage reference and current sources, and so forth, which can be shared with the NFC sub-system 2318 .

Even though the RF receiver 2604 and the RF transmitter 2606 are illustrated as outputting and receiving, respectively, intermediate frequency (IF) signals, the disclosure is not limited in this regard. More specifically, the RF receiver 2604 and the RF transmitter 2606 can be configured to output and receive, respectively, RF signals (e.g., super-heterodyne or direct conversion architecture).

FIG. 27 is a block diagram of a media access control (MAC)/baseband (BB) sub-system according to some aspects. Referring to FIG. 27 , the BBS 2312 can include a triplexer 2702 , an IF receiver 2704 , an, a modem 2724 , a crystal oscillator 2730 , a synthesizer 2728 , and a divider 2726 . The synthesizer 2728 can use a signal from the crystal oscillator 2730 generate a clock signal which can be divided by divider 2726 to generate an output clock signal for communication to the RFEM 2310 . In some aspects, the generated clock signal can have a frequency of 1.32 GHz.

The IF receiver 2704 can include an amplifier 2708 , mixers 2710 , filters 2712 , and ADC blocks 2714 . The IF transmitter 2706 can include DAC blocks 2722 , low-pass filters 2720 , mixers 2718 , and IF amplifier 2716 .

In an example receive operation, an IF signal is received from the RFEM 2310 via the triplexer 2702 and is amplified by amplifier 2708 . The amplified IF signal can be down-converted to baseband signals by the mixers 2710 , then filtered by low-pass filters 2712 , and converted to a digital signal by the ADC blocks 2714 before being processed by the modem 2724 .

In an example transmit operation, a digital signal output by the modem 2724 can be converted to analog signals by the DAC blocks 2722 . The analog signals are then filtered by the low-pass filters 2720 and then up convert it to an IF signal by the mixers 2718 . The IF signal is then amplified by IF amplifier 2716 and then transmitted to the RFEM 2310 via the triplexer 2702 and the coax cable 2612 .

In some aspects, the coax cable may be used to communicate IF signals or RF signals (e.g., RF-over-Coax, or RFoC communications). In this regard, one or more other sub-systems for processing IF or RF signals can be disposed between the RFEM 2310 and the BBS 2312 for additional signal processing.

In some aspects, the RFEM 2310 , the BBS 2312 , the NFC sub-system 2318 , the phased antenna array 2316 and the NFC antenna 2314 can be located within the same package, or a distributed approach may be used where one or more sub-systems can be implemented on a separate package.

FIG. 28 is a diagram of an exemplary NFC antenna implementation according to some aspects. Referring to FIG. 23 and FIG. 28 , the RFEM 2310 as implemented with the co-located antenna array 2316 and NFC antenna 2314 can also include a signal shielding cover 2802 . In some aspects, the NFC antenna 2314 can be disposed on the signal shielding cover 2802 . As seen in FIG. 28 , the NFC antenna 2314 can be implemented as an inductive coil 2808 . More specifically, the following stack can be applied to the signal shielding cover 2802 : a polyester tape 2814 , a magnetic sheeting 2812 , and adhesive tape 2810 , the inductive coil 2808 , a base film 2806 , and an adhesive tape 2804 . Even though FIG. 28 illustrates a specific tape stack including the coil 2808 , the disclosure is not limited in this regard and other aspects of a co-located NFC antenna with a millimeter wave phased antenna array are also possible, and other types of layers/sheeting and layer ordering can also be used in lieu of the layers and ordering illustrated in FIG. 28 .

FIG. 29 illustrates multiple views of a semiconductor package with co-located mmWave antennas and a near field communication (NFC) antenna on multiple PCB substrates according to some aspects. Referring to FIG. 29 , the semiconductor package 2902 can include multiple PCB substrates. For example, the semiconductor package 2902 can include a first substrate 2904 and a second substrate 2906 . The first substrate 2904 can include a first side 2904 A (e.g., a printed side) and a second side 2904 B (e.g., a component side). The component side 2904 B can include one or more components 2908 , such as an RFEM (e.g., 2310 ), a BBS (e.g., 2312 ), and an NFC sub-system (e.g., 2318 ). The printed side 2904 A can include a phased antenna array 2910 . For example, the phased antenna array 2910 can be used by the RFEM implemented on the component side 2904 B. In some aspects, the printed side 2904 A can include a co-located NFC antenna 2914 . The NFC antenna 2914 can be implemented as NFC antenna 2914 A (next to the phased antenna array 2910 ) or as NFC antenna 2914 B disposed around the phased antenna array 2910 .

In some aspects, a subset of the phased antenna array used by the RFEM implemented on the substrate 2904 can be disposed on the second substrate 2906 . For example, as seen in FIG. 29 , the substrate 2906 can include a phased antenna array 2912 . Both the phased antenna array 2910 and the phase antenna array 2912 can include antennas with horizontal and/or vertical polarization. In some aspects, the second substrate 2906 can include a co-located NFC antenna 2914 C, which can be disposed next to the phased antenna array 2912 . Alternatively, the NFC antenna can be implemented as antenna 2914 D which is an inductor disposed around the phased antenna array 2912 .

In some aspects, the first substrate 2904 can include solder balls 2916 , which can be used for coupling between the first substrate 2904 and the second substrate 2906 .

Phased array radio transceivers can be used in millimeter wave radio communications circuits to increase antenna gain, in order to address the significant path loss associated with smaller antenna aperture at these frequencies. However, phased array radio transceivers utilize a recombination point where the sum of all the phased array receivers (or transmitters) signals are combined together. This combination node is often a bottleneck in phased array receivers in terms of performance and complexity. Additionally, in applications where a different size of phased array is desired, the combination node may need to be redesigned, which significantly increasing the design complexity and is an obstacle to the scalability of phased arrays.

FIG. 30 is a block diagram of an RF phased array system that implements beamforming by phase-shifting and combining the signals at RF according to some aspects. The illustrated RF phased array system may be incorporated in the RF circuitry 325 of mmWave communication circuitry 300 shown in FIG. 3 A , although the RF phased array system is not limited to such.

Referring to FIG. 30 , there is illustrated a phased array radio transceiver 3000 . The transceiver operates by modifying the gain and a phase of each received element in such a way that a transmitted (or received) signal is formed from the coherent vector sum of several weaker (in amplitude) signals. The transceiver 3000 operates as an RF phased array system. More specifically, the transceiver 3000 includes N number of receiver/transmitter chains including antennas 3002 _ 1 - 3002 _N, amplifiers 3004 _ 1 - 3004 _N, phase shifters 3006 _ 1 - 3006 _N, variable gain amplifiers 3008 _ 1 - 3008 _N, an adder (or combiner) 3010 , a mixer 3012 , a filter 3016 , and an analog-to-digital converter (ADC) 3018 . In instances when signals are processed for transmission, block 3018 can be a digital-to-analog converter.

In operation, the phase shifters 3006 _ 1 - 3006 _N as well as the variable gain amplifiers 3008 _ 1 - 3008 _N are used to adjust each transmitted or received signal. The advantages of the RF phased array system in FIG. 30 are simplicity since only one mixer and baseband chain may be needed. Drawbacks of the RF phased array system in FIG. 30 can include the lack of scalability (adding several paths at RF frequencies forms a bandwidth bottleneck), added noise figure in the receiver (since noisy phased array and variable gain amplifiers are added near to the antennas), and added power consumption (the phase and gain adjustments blocks operate at millimeter wave frequencies and can add extra signal loss).

FIG. 31 is a block diagram of a phased array system that implements beamforming by phase-shifting the local oscillator (LO) and combining the analog signals at IF/baseband according to some aspects. Referring to FIG. 31 , there is illustrated a phased array radio transceiver 3100 , which is configured as a local oscillator (LO) phase shifting phased array system. The transceiver 3100 can include antennas 3102 _ 1 - 3102 _N, amplifiers 3104 _ 1 - 3104 _N, variable gain amplifiers 3106 _ 1 - 3106 _N, mixers 3108 _ 1 - 3108 _N, phase shifters 3110 _ 1 - 3110 _N, an adder (or combiner) 3114 , a filter 3116 , and an ADC 3118 . As seen in FIG. 31 , the LO phased array system 3100 uses variable gain amplifiers in the signal path, however, the phase shifters 3110 are used within the local oscillator path to shift the phase of the LO signal 3112 . The advantage of this topology over the RF phased array system of FIG. 30 is a reduced noise profile. However, the LO phased array system 3100 uses more mixers. Additionally, routing LO signals operating at millimeter wave frequencies can be challenging.

In some aspects, the LO phased array system 3100 can be configured to perform the phase shifting using all digital PLLs (ADPLLs) and the phase shifting can be accomplished digitally within the ADPLL loop. This can eliminate the need for RF phase shifters, which are costly in terms of power consumption and introduce distortion and insertion loss in the signal path. Phase shifting within the ADPLL also removes the needs for explicit phase shifter added on the LO signal path.

FIG. 32 is a block diagram of a phased array system with digital phase shifting and combining according to some aspects. Referring to FIG. 32 , there is illustrated a digital phased array system 3200 . The transceiver 3200 can include antennas 3202 A- 3202 N, amplifiers 3204 A- 3204 N, variable gain amplifiers 3206 A- 3206 N, mixers 3208 A- 3208 N, filters 3212 A- 3212 N, ADCs 3214 A- 3214 N and an adder 3216 .

As seen in FIG. 32 , the entire transceiver chain is replicated for each antenna, including the data converters 3214 A- 3214 N. The signal phase adjustment and the signal combination can be performed on the digital signal output 3218 after the adder 3216 . Performing phased array combination in digital domain, however, can result in increased complexity and power consumption. A benefit of the digital phased array system 3200 is its ability to support multiple user simultaneously, with each user taking advantage of the full antenna array gain, by creating separate digital streams each generated with a different set of beamforming coefficients (both gain and phase).

In the example transceivers illustrated in FIGS. 30 - 32 , a recombination point is used where the sum of all the phased array receivers (or transmitters) signals are combined together with different amplitude weights and/or phase shifts. This combination node can oftentimes be a bottleneck in phased array receivers in terms of performance and complexity. Additionally, if a different size of phased array is desired, the combination node may be redesigned, which can significantly increase the design complexity of the transceiver and substantially limits the array scalability.

In some aspects, a scalable phased array radio transceiver architecture can be used, as discussed herein, which alleviates the scalability and complexity issues associated with the transceivers illustrated in FIGS. 30 - 32 . The scalable phased array radio transceiver architecture can use multiple transceiver tiles (or cells), which aids in the reusability of this architecture for multiple applications and products and reduces time-to-market. Additionally, the proposed scalable phased array radio transceiver architecture is self-configurable, easing the programmability of the transceiver device. The scalable phased array radio transceiver architecture can support multiple modes of operation that enable better phased array gain or low power consumption optimized for the specific use case, as discussed herein below.

FIG. 33 is a block diagram of a transceiver cell element which can be used in a scalable phased array radio transceiver architecture according to some aspects. Referring to FIG. 33 , the transceiver cell (TRX) 3300 can include transmitter (TX) circuitry 3302 , receiver (RX) circuitry 3304 , a local oscillator (LO) circuitry 3306 , digital circuitry (DIG) 3308 , input/output (I/O) circuitry 3310 , and phase adjustment circuitry 3312 . In some aspects, a set of multiplexers and de-multiplexers can be tiled on the four edges 3320 - 3326 of the transceiver cell 3300 to allow communication with adjacent cells. The four edges of the transceiver cell 3300 can be designated as a North (N) edge 3320 , an East (E) edge 3322 , a South (S) edge 3324 , and a West (W) edge 3326 . The I/O circuitry 3310 can include both analog and digital parallel buses that connect the transceiver cell 3300 to neighboring cells, which allows tiling of the cells into a transceiver array. In some aspects, the TX circuitry 3302 and the RX circuitry 3304 can have either single or multiple transmitters and receivers respectively, allowing multiple receiver and transmitter chains to share a single local oscillator signal in order to save power consumption. In some aspects, a crystal oscillator signal, which can be used to generate the local oscillator signal within each transceiver cell, can be buffered and shared between multiple transceiver cells. In some aspects, a loopback can be used to measure and calibrate out a delay introduced by the crystal oscillator buffers in each transceiver cell. The transceiver cell 3300 can also include control circuitry (not illustrated in FIG. 33 ), which can be used to process control signals connecting the transceiver cell 3300 to other neighboring cells as well as global control signals that are static. In some aspects, the control circuitry can be included as part of the digital circuitry 3308 .

In some aspects, the TX circuitry 3302 and the RX circuitry 3304 can include amplifiers, variable gain amplifiers, mixers, baseband filters, analog-to-digital converters, digital-to-analog converters, and other signal processing circuitry. In some aspects, the digital circuitry 3308 can include circuitry performing digital signal processing, filtering, as well as digital signal combination and phase adjustment. In some aspects, phase adjustment and signal combination can be performed by the phase adjustment circuitry 3312 , both in analog or digital domain.

FIG. 34 is a block diagram of a phased array radio transceiver architecture using multiple transceiver cells according to some aspects. Referring to FIG. 34 , the transceiver array 3400 can include multiple transceiver cells tiled together in an array. More specifically, each of the transceiver cells 3402 - 3412 can be a copy exact of each other, and each of the transceiver cells 3402 - 3412 can include functional blocks as described in reference to FIG. 33 . The communication between the individual transceiver cells 3402 - 3412 can include analog and digital buses. In some aspects, the width of the buses can be equal to the number of simultaneous users that the phased array system can support, as further explained herein below. As seen in FIG. 34 , each transceiver cell can be connected to only adjacent transceiver cells, which ensures the scalability of the transceiver architecture using multiple transceiver tiles.

In some aspects, the transceiver architecture using multiple transceiver tiles can be implemented on a single semiconductor die, which can enable dicing of the semiconductor wafer into different shapes and array sizes for different applications, as illustrated in FIG. 35 .

FIG. 35 illustrates dicing of semiconductor die into individual transceiver cells forming phased array radio transceivers according to some aspects. Referring to FIG. 35 , semiconductor wafers 3500 and 3502 are illustrated. The wafers 3500 and 3502 can be fabricated to include multiple transceiver tiles (or cells) connected to each other during the fabrication process. In connection with the wafer 3500 , different phased array radio transceivers can be diced out of the wafer 3500 for different applications. For example, a 10×3 array 3510 , multiple 1×2 arrays 3512 , a single 3×18 array 3514 , multiple 3×3 arrays 3516 , multiple 3×9 arrays 3518 , multiple 1×4 arrays 3520 , and a single 2×10 array 3522 can be diced out of the semiconductor wafer 3500 and used for different low-power applications with varying system-level requirements.

In some aspects, in high-performance systems (e.g., base station applications), the single semiconductor die 3502 can be diced so that a single transceiver array 3530 is obtained. In this regard, the same semiconductor wafer can be filled with multiple copies of the same transceiver cell (e.g., 3300 ) and then the semiconductor wafer can be diced to obtain transceiver arrays with different form factors.

FIG. 36 is a block diagram of a phased array radio transceiver architecture packaged with a phased array antenna according to some aspects. Referring to FIG. 36 , the phased array radio transceiver architecture package 3600 can include transceiver array 3610 with tiled transceiver cells disposed on a semiconductor die 3602 . The transceiver array 3610 can be combined with antenna layer 3604 of antennas in an antenna array 3612 , which can be integrated with the transceiver array 3610 to form the phased array radio transceiver architecture package 3600 . In some aspects, a pitch of individual transceiver cells within the transceiver array 3610 can equal to a pitch of the individual antennas in the antenna array 3612 .

In some aspects, a configurable phased array transceiver system including a plurality of identical transceiver cells (e.g., transceiver array 3400 with multiple transceiver cells such as cell 3300 ) can include self-aware configurable structures for performing self-configuration. More specifically, a processor circuitry associated with the transceiver array 3400 (or processes circuitry within one or more of the individual transceiver cell 3300 ) can perform self-configuration upon power up. For example, identification numbers (IDs) for each of the transceiver cells within the transceiver array 3400 can be determined at power up, e.g., by an ID assignment algorithm. By having associated ID numbers for each transceiver cell, the transceiver array 3400 can provide configuration information indicating the number and/or location of individual transceiver cells that are activated within the transceiver array 3400 so that each identical cell can be individually addressed for control and configuration.

The four sides of the transceiver array chip can be referred to as North (N), South (S), West (W), and East (E). Upon power up, ID #1 can be assigned to the NW corner cell, e.g., transceiver cell 3402 . The NW corner of the transceiver array 3400 can be determined by location connection ports that can detect whether the port is open or shorted with another port.

For example, the processor circuitry can determine that both the N and W ports of transceiver cell 3402 are open and, therefore, the initial ID #1 is assigned to that cell. The transceiver cell 3402 can then initiate the numbering sequence, where the ID number can be incremented by one and passed to the neighboring transceiver cell to the east. If a current cell has no E port connection (e.g., cell 3406 ) and it received its ID number from the west cell, then it passes the ID number to the south cell. If the current cell has no E port connection and it received its ID number from the north cell, then it passes the ID number to the west cell (if connected, otherwise it also passes the ID number to the south cell). Similar process can be used for the west boundary of the array. This is continued until a SE or SW corner cell is reached. At that point, the ID numbering is complete. Additionally, when the ID number of a cell is assigned, the cell can undergo a local amplitude and phase calibration of both transmit and receive amplitude and phase values. Once the self-calibration process is complete and each transceiver cell within the transceiver array has an assigned ID number, the ID numbers can be used to further configure the array for processing signals associated with different number of users. In the example array 3400 in FIG. 34 , the ID assignment/numbering can start at cell 3402 , then continue sequentially to the right until cell 3406 , then go down and continue to the left until cell 3408 , then go down and continue to the right, and so forth.

In some aspects, a scalable phased array radio transceiver architecture, such as transceiver array 3400 , can support multiple modes of operation. Example modes of operation include LO phased array (or beamforming) operation mode, digital phased array (or beamforming) operation mode, analog phased array (or beamforming) operation mode, and hybrid phased array (or beamforming) operation mode. Each of the operation modes can be implemented using the transceiver cell (e.g., 3402 or 3300 ) discussed above, allowing size scalable operation and configuration of the array 3400 .

FIG. 37 is a block diagram of a transceiver cell with communication busses according to some aspects. Referring to FIG. 37 , the transceiver cell 3700 can be the same as transceiver cell 3300 discussed above in reference to FIG. 33 .

During an example digital beamforming operation mode, transceiver related elements within the transceiver cell 3700 can be used. For example, in a receive mode, the receive signal can be converted to digital signal, then a vector summed within the transceiver cell 3700 with a digital signal received from a neighboring transceiver cell with the previous ID number. To maintain scalability, the summation between each stage can be pipelined in order to limit the loading on the data bus lines. Additionally, in order to support a total of K users (or equivalently K independent beams for the phased array), K number of bus lines can be used, one for each user.

In some aspects, the number of bus lines can be fixed in hardware, and each transceiver cell can therefore be designed with the hardware to support the maximum number of users (or beams) during digital phased array operation. Since the data lines are pipelined, an internal pipeline register of depth ND may be maintained. The pipelined depth ND can limit the maximum transceiver array size where the individual transceiver cells are connected for a digital phased array mode of operation. Larger array size (or number of identical transceiver cells) requires larger pipeline register depth ND.

As seen in FIG. 37 , the transceiver cell 3700 is configured for digital beamforming operation mode using K digital buses to communicate with neighboring cells. For example, K number of digital buses 3702 , 3704 , 3706 , and 3708 can be used to communicate with transceiver cells located to the west, north, east, and south, respectively. The transceiver cell 3700 can include a transmitter block 3722 and a receiver block 3724 . The transmitter block 3722 and receiver block 3724 can be coupled to the K number of digital buses via digital multiplexers 3710 - 3712 , 3714 - 3716 , and 3718 - 3720 , which can be used for selection of digital inputs from a specific neighboring transceiver cell. Receive digital signals from a neighboring cell can be added and then passed on to the subsequent neighboring cell in a pipelined fashion.

FIG. 38 is a block diagram of a phased array transceiver architecture with transceiver tiles in LO phase shifting operating mode using a single analog-to-digital converter (ADC) according to some aspects. Referring to FIG. 38 , the phased array transceiver 3800 can include a plurality of transceiver cells 3802 - 3818 . The transceiver cells 3802 - 3818 can be the same as the transceiver cell 3300 illustrated in FIG. 33 .

In an example LO phased array operation mode, each transceiver cell 3802 - 3818 can receive a phase shift signal from a central control unit (not illustrated in FIG. 38 ). The central control unit can be a processor used by the transceiver array 3800 or it can be one or more processors within an individual transceiver cell. In the receive path, the phase shift signals can be applied to a local oscillator signal to generate a phase shifted LO signal. The outputs of all mixer stages can be summed in the analog domain, bypassing any analog-to-digital conversion. More specifically, after a received wireless signal is down-converted using the phase shifted LO signal, the resulting signal can be summed with a signal received from a neighboring cell (e.g., a transceiver cell along the west edge) and then passed to another neighboring transceiver cell (e.g., a transceiver cell along an east edge).

In reference to the transceiver array 3800 in FIG. 38 , the analog down-converted signals are summed as they are passed between neighboring cells, and a final summed analog signal is communicated to transceiver cell 3806 . An analog-to-digital converter 3820 within transceiver cell 3806 can be used to convert the analog signal to a digital signal, which can then be communicated for processing to the baseband circuit 3822 . In this regard, only a single ADC would take the combined analog signal outputs of all transceiver cells 3802 - 3818 and translate the combined analog signal output into a digital signal. The combination of the multiple analog signals from each of the transceiver cells 3802 - 3818 can be performed through an analog bus line that interfaces between the adjacent transceiver cells. By using a single ADC within the transceiver array 3800 , a significant power reduction can be achieved since the ADC is one of the largest power consuming blocks in a phase shifted array system.

FIG. 39 is a block diagram of a phased array transceiver architecture with transceiver tiles in LO phase shifting operating mode using multiple ADCs according to some aspects. Referring to FIG. 39 , the transceiver array 3900 can include a plurality of transceiver cells 3902 - 3918 . The transceiver cells 3902 - 3918 can be the same as the transceiver cell 3300 illustrated in FIG. 33 . In an example LO phased array operation mode with multiple subarrays, each transceiver cell 3902 - 3918 can receive a phase shift signal from a central control unit (not illustrated in FIG. 39 ). The central control unit can be a processor used by the transceiver array 3900 or it can be one or more processors within an individual transceiver cell.

As seen in FIG. 39 , multiple neighboring transceiver cells within a row of the transceiver array 3900 can form a subarray. For example, transceiver cells 3902 - 3906 can form a transceiver subarray. Similar subarrays can be formed by transceiver cells 3908 - 3912 and 3914 - 3918 . In the receive path for each of the subarrays, the phase shift signals can be applied to a local oscillator signal to generate a phase shifted LO signal. The outputs of all mixer stages within a subarray can be summed in the analog domain, bypassing any analog-to-digital conversion and then communicated to a single ADC associated with the subarray. More specifically, after a received wireless signal is down-converted using the phase shifted LO signal, the resulting signal can be summed with a signal received from a neighboring cell (e.g., a transceiver cell along the west edge) within the subarray of cells 3902 - 3906 , and then passed to another neighboring transceiver cell (e.g., a transceiver cell along an east edge) within the subarray.

In reference to the transceiver subarray of cells 3902 - 3906 , the analog down-converted signals are summed as they are passed between neighboring cells, and a final summed analog signal is communicated to transceiver cell 3906 . An analog-to-digital converter 3920 within transceiver cell 3906 can be used to convert the analog signal to a digital signal, which can then be communicated for processing to the baseband circuit 3926 .

In reference to the transceiver subarray of cells 3908 - 3912 , the analog down-converted signals are summed as they are passed between neighboring cells, and a final summed analog signal is communicated to transceiver cell 3912 . An analog-to-digital converter 3922 within transceiver cell 3912 can be used to convert the analog signal to a digital signal, which can then be communicated for processing to the baseband circuit 3928 .

In reference to the transceiver subarray of cells 3914 - 3918 , the analog down-converted signals are summed as they are passed between neighboring cells, and a final summed analog signal is communicated to transceiver cell 3918 . An analog-to-digital converter 3924 within transceiver cell 3918 can be used to convert the analog signal to a digital signal, which can then be communicated for processing to the baseband circuit 3930 .

In comparison to the transceiver array 3800 of FIG. 38 where all transceiver cell elements within the array are used to generate analog signals and a single ADC within the array is used to generate an output digital signal, the transceiver array 3900 in FIG. 39 uses one ADC per subarray, which allows for generation of multiple digital signals serving multiple users (e.g., M users can be served if transceiver array 3900 is divided into M subarrays, each with its own digital signal output). However, each user will be using only a fraction (1/M) of the total array aperture.

FIG. 40 is a block diagram of a phased array transceiver architecture with transceiver tiles in hybrid operating mode (LO and digital phase-shifting and combining) using multiple ADCs to generate multiple digital signals according to some aspects. Referring to FIG. 40 , the phased array transceiver 4000 can include a plurality of transceiver cells 4002 - 4018 . The transceiver cells 4002 - 4018 can be the same as the transceiver cell 3300 illustrated in FIG. 33 . In an example hybrid operation mode, each of the transceiver cells 4002 - 4018 can receive a phase shift signal from a central control unit (not illustrated in FIG. 40 ). The central control unit can be a processor used by the transceiver array 4000 or it can be one or more processors within an individual transceiver cell.

As seen in FIG. 40 , multiple neighboring transceiver cells within a row of the array 4000 can form a subarray. For example, transceiver cells 4002 - 4006 can form a transceiver subarray. Similar subarrays can be formed by transceiver cells 4008 - 4012 and 4014 - 4018 . In the receive path for each of the subarrays, the phase shift signals can be applied to a local oscillator signal to generate a phase shifted LO signal. The outputs of all mixer stages within a subarray can be summed in the analog domain, bypassing any analog-to-digital conversion and then communicated to a single ADC associated with the subarray. More specifically, after a received wireless signal is down-converted using the phase shifted LO signal, the resulting signal can be summed with a signal received from a neighboring cell (e.g., a transceiver cell along the west edge) within the subarray of cells 4002 - 1106 , and then passed to another neighboring transceiver cell (e.g., a transceiver cell along an east edge) within the subarray. In reference to the transceiver subarray of cells 4002 - 4006 , the analog down-converted signals are summed as they are passed between neighboring cells, and a final summed analog signal is communicated to transceiver cell 4006 . An analog-to-digital converter (ADC) circuit 4020 within transceiver cell 4006 can be used to convert the analog signal to a digital signal, which can then be communicated for processing to the baseband circuit 4026 .

In reference to the transceiver subarray of cells 4008 - 4012 , the analog down-converted signals are summed as they are passed between neighboring cells, and a final summed analog signal is communicated to transceiver cell 4012 . An analog-to-digital converter 4022 within transceiver cell 4012 can be used to convert the analog signal to a digital signal, which can then be communicated for processing to the baseband circuit 4028 .

In reference to the transceiver subarray of cells 4014 - 4018 , the analog down-converted signals are summed as they are passed between neighboring cells, and a final summed analog signal is communicated to transceiver cell 4018 . An analog-to-digital converter (ADC) circuit 4024 within transceiver cell 4018 can be used to convert the analog signal to a digital signal, which can then be communicated for processing to the baseband circuit 4030 .

In an example hybrid operation mode, each of the baseband circuits 4026 , 4028 , and 4030 can apply one or more weight values (or coefficients) for purposes of generating beamforming signals. More specifically, coefficients H 1 , H 2 , . . . , H N can be associated with a desired beam 4037 . Similarly, coefficients W 1 , W 2 , . . . , W N can be associated with a desired beam 4033 . Baseband circuits 4026 , 4028 , and 4030 can apply coefficients H 1 , H 2 , . . . , H N to the digital signals received from ADC circuits 4020 , 4022 , and 4024 . The weighted signals can be summed by adder 4036 to generate the desired beam 4037 .

Similarly, baseband circuits 4026 , 4028 , and 4030 can apply coefficients W 1 , W 2 , . . . , W N to the digital signals received from ADC circuits 4020 , 4022 , and 4024 . The weighted signals can be summed by adder 4032 to generate the desired beam 4033 . Beams 4037 and 4032 can be further processed by baseband circuitry 4038 and 4034 , respectively.

Even though FIG. 40 illustrates generation of two beams using two adders in digital domain, the disclosure is not limited in this regard. In some aspects, only a single set of weights can be applied to the digital outputs of the ADC circuits and only a single adder can be used to generate a single beam for a single user.

FIG. 41 is a block diagram of a phased array transceiver architecture with transceiver tiles in analog IF/baseband phase shifting and combining operating mode using a single ADC according to some aspects. Referring to FIG. 41 , the transceiver array 4100 can be configured to operate in an analog phase shifting (beamforming) operation mode. As seen in FIG. 41 , each of the transceiver cells 4102 A, 4102 B, 4102 C, and 4102 D includes local oscillators 4106 , mixers 4104 , and phase shifters 4108 . After a received wireless signal is down-converted by the mixers 4104 , the phase shifters 4108 can apply a phase shift, which can be specified by control circuit within the transceiver array 4100 . Phase shifted analog signals can be communicated to neighboring transceiver cells where they can be summed, resulting in a final combined signal 4110 . The combined phase shifted baseband analog signal can be converted to a digital signal by a single ADC within the transceiver array 4100 . For example, the combined signal 4110 can be communicated to ADC 4112 B within transceiver cell 4102 B, which can generate a digital signal 4114 for further processing by the baseband circuitry 4116 .

FIG. 42 is a block diagram of a phased array transceiver architecture with transceiver tiles in analog IF/baseband phase shifting operating mode using multiple ADCs to generate multiple digital signals according to some aspects. Referring to FIG. 42 , the transceiver array 4200 can include transceiver cells 4202 A, 4202 B, 4202 C, and 4202 D. Each of the transceiver cells 4202 can include corresponding mixers 4204 ( 4204 A- 4204 D) and local oscillator generators 4206 ( 4206 A- 4206 D).

In some aspects, the analog baseband signals at the output of the mixers 4204 can be used to generate multiple output signals. More specifically, an analog coefficients set can be applied using an analog multiplier, and the output of each mixer to generate a weighted signal from each transceiver cell, which can be summed and converted to a digital signal by an ADC sub-system. As seen in FIG. 42 , a first analog coefficients set A 1 (S) ( 4208 A- 4208 D) can be applied at the output of mixers 4204 A- 4204 D, respectively. The weighted signals can be summed to generate a combined signal 4214 , which can be communicated to ADC 4212 B within the transceiver cell 4202 B. The ADC 4212 B can generate an output digital signal 4216 for subsequent processing by the digital baseband circuit 4218 .

Similarly, a second analog coefficients set A 2 (S) ( 4210 A- 4210 D) can be applied at the output of mixers 4204 A- 4204 D, respectively. The weighted signals can be summed to generate a combined signal 4220 , which can be communicated to ADC 4212 D within the transceiver cell 4202 D. The ADC 4212 D can generate an output digital signal 4222 for subsequent processing by the digital baseband circuit 4224 . In this regard, by applying two separate parallel analog coefficients sets to each output of a transceiver cell mixer, two separate digital output signals corresponding to two separate beams can be used for two separate users. Even though only two output digital signals are illustrated in FIG. 42 , the disclosure is not limited in this regard and a different number of parallel analog coefficients sets can be used as well.

FIG. 43 illustrates example operation modes of a phased array transceiver architecture with transceiver tiles according to some aspects. Referring to FIG. 43 , table 4300 provides a summary of the number of parallel analog coefficients sets, data convergence, and parallel digital coefficients sets, which can be used for various operation modes of a scalable phased array radio transceiver architecture using multiple transceiver cells as described herein.

Referring to the first row in table 4300 , a full aperture (e.g., a full array size) can be used for LO beamforming operation mode in a transceiver array. This mode is seen in FIG. 38 , where the entire array is used (full aperture), no analog coefficients sets are used (as phase shifting is implemented with LO phase shifting and not in the analog baseband signal after the mixer), and a single ADC is used to generate a single digital output signal without any parallel digital coefficient sets used for subsequent processing.

Referring to the second row in table 4300 , the full transceiver array can be used for digital beamforming operation mode. The analog outputs of each transceiver cell can be summed and N number of digital converters within the array can be used to generate N digital signals without the use of any parallel analog coefficients sets. The N digital outputs of the data converters can be used with M number of parallel digital coefficient sets to generate a final M number of output beams serving M users. The application of digital coefficient sets is illustrated in FIG. 40 , where two digital coefficient sets are used for the output of N digital converters, to generate two final output beams serving two users.

Referring to the third row in table 4300 , 1 /M of the transceiver array aperture is used to serve M users. This example is illustrated in FIG. 39 where subarray processing is used with M number of analog-to-digital converters (assuming the array 3900 has M rows). The M digital outputs from the analog-to-digital converters can be subsequently processed (e.g., as seen in FIG. 40 ) using up to M number of parallel digital coefficient sets.

Referring to the fourth row in table 4300 , a full aperture of the transceiver array can be used with analog phased array operation mode. For example and as seen in FIG. 42 , and M number of parallel analog coefficients sets can be used along with M number of digital converters to generate an M number of output signals. In reference to FIG. 42 , M equals two so that to parallel analog coefficients sets are used per transceiver cell, with two digital converters, generating to output beam signals. Up to M parallel digital coefficient sets can be subsequently used with the beam signal outputs of the data converters.

Previous wireless user device antenna array designs have raised at least three issues. One issue is that previous designs incorporated a shielded silicon die that feeds antenna arrays, where the shield is a discreet metal shield, and where the arrays may be on one or more levels of, or one or more sides of, a substrate that includes the shielded silicon die. This required a relatively large area substrate for the shielded die, discrete circuitry, and antenna arrays on one or more levels, or on one or more sides, of the substrate. A design that requires a large area substrate implies more expensive substrates. In designs of the above type, it is not unusual for the substrate to approach being twice as expensive as the silicon die from which the antenna arrays are fed. In some aspects, the substrate may be a laminate structure. While laminate structures will be described herein, other substrates may also be used in other aspects.

A second issue encountered in designs of the above type is the routing of long feed lines from the die to some of the antenna elements because of the large areas involved. This leads to power loss, in some instances as much as a 3 dB loss, or a loss of nearly half the power, in feeding some of the antenna elements.

Third, while such designs may provide good phased array radiation in some areas of the substrate, in other areas the radiation from antenna elements or from entire antenna arrays could be blocked because of the shielding that covers the die and the discreet components to protect them from radio frequency interference (RFI) and electromagnetic interference (EMI).

Therefore, it is desirable to find solutions to the above three issues. One solution involves a design using a plurality of packages such as substrates or laminate structures. Described herein is a solution using two packages, as described in FIGS. 44 A to 44 D , in a package-on-package (POP) implementation, according to some aspects.

FIG. 44 A illustrates a top view of one package of a two-package system, according to some aspects. One package indicated generally at 4400 and specifically at 4401 , may be a substrate which, in some aspects, has parallel metallized layers with a metallized top layer and a metallized bottom layer. The package 4400 may be incorporated in the RF circuitry 325 and the antenna array circuitry 330 of mmWave communication circuitry 300 shown in FIG. 3 A , although the package 4400 is not limited to such. Parts or all of one or more of the metallized layers may be processed to be free of metallization as needed, in some aspects.

In some aspects, substrate 4401 includes an array of six patch antennas 4403 , 4404 . The designation 4403 represents patch antennas with a single match point, indicated by a single dot, and which may be a single patch antenna. The designation 4404 represents patch elements with two match points, indicated by two dots, and which may be a dual stacked patch antenna element. This design is but one of a number of configurations and types of antenna elements that might be used and is representative of only some aspects. Around the periphery of substrate 4501 are six antenna elements 4505 , according to some aspects. These may be printed antenna elements situated for end fire operation according to some aspects. While dipole antenna elements are illustrated at 4505 , other types of antenna elements may be used. In the description herein, some or all of the antenna arrays may be called intelligent antenna arrays.

The terms “intelligent antenna” or “intelligent antenna arrays” find meaning in the manner in which the antennas or the antenna arrays are controlled. In some aspects antenna arrays may be implemented with various types of polarities, such as vertical, horizontal and circular polarizations. As an example, when antenna arrays are implemented for vertical polarity and horizontal polarity, the transmitted polarity at a given time, and therefore which antenna or array is firing at a given time, may be algorithmically controlled based on an indication of the polarity of the signal received with greatest strength at the wireless user device, hence intelligent. This information can be continually fed back to a wireless transmitter such as a cell tower transceiver from the user device in some aspects. This operation may then be implemented to achieve transmitted polarization that matches the polarization at the receiver of the user device which may be a mobile phone. The user device antennas are also similarly algorithmically controlled in some aspects. Similar algorithmic control obtains for spatial diversity in some aspects.

FIG. 44 B illustrates a bottom view of the substrate 4401 of FIG. 44 A , according to some aspects. In FIG. 44 B , the structure is illustrated generally at 4402 , and includes silicon die 4409 and discrete components, one of which is designated as 4411 . The discrete components may be capacitors, resistors and/or inductors in some aspects. Surrounding the die are contacts 4407 which in some aspects may be solder balls.

FIG. 44 B illustrates a bottom view of the substrate of FIG. 44 A , according to some aspects. FIG. 44 C illustrates a bottom view of a substrate of a second package of the two package system of FIGS. 44 A and 44 B , according to some aspects. Structure 4419 of FIG. 44 C may be a substrate such as a PCB board, as may be substrate 4401 of FIG. 44 A , according to some aspects. Structure 4419 is of length L, which is essentially the same length of the line of contacts 4407 of FIG. 44 B , in some aspects, which contacts are discussed below. Illustrated on structure 4419 are four antenna elements 4421 shown here as dual stacked patch antennas each with two match points indicated by the two dots on each antenna element. As with the substrate 4401 , this design of antennas on or within substrate 4401 is one of a number of configurations and types of antenna elements that might be used and is representative of only some aspects.

FIG. 44 D illustrates the packages of FIGS. 44 A and 44 C mounted one to the other, according to some aspects. The first package 4401 and the second package 4419 are mounted, or stacked, one upon the other as a package-on-package implementation. The mounting can be done using various mounting processes. As can be seen by the POP aspect 4406 , the antenna elements 4421 are on or within substrate 4419 on the “top” substrate, or “top package,” of the POP aspect, and are pointing “upward.” The antennas 4403 , 4404 are on or within the “bottom” of substrate 4401 , or “bottom package,” of the POP aspect and are pointing “downward,” according to some aspects. Connector 4417 and components 4413 may be secured and made robust by mold, or encapsulate, 4414 , discussed below. Level 4423 includes metallized layers which in some aspects may be multiple metallized layers used for antennas and for feed lines.

Generally speaking, the concept of POP relates to vertically stacking packages that were not able to be stacked in previous aspects, and encompasses 3-dimensional (3D) stacking of antennas, dies, and components in packages. Some factors to be considered in 3-D stacking include antenna volume and antenna size. Previous designs were planar, which resulted in the shielded die design with the X-dimension and Y-dimension (e.g., width and length) being of dimensions that led to the large substrate area discussed above, with the issues of substrate cost, feed line power loss and loss of available space and blockage of radiation by the shield and other discreet components. Previous designs were based primarily on the assumption that volume of the package is more important than the X-dimension and the Y-dimension of the package, because of the importance of the Z-height dimension of the volume, there being a certain Z-height or “headroom” limitation for user device packages. But this assumption led to larger and larger X-Y area in order to decrease the Z-dimension, leading to the above issues. It has been discovered, however, that stacking package-on-package can lead to resolutions of these issues, resulting in less expensive substrates, a reduction in power loss through the routing of feed lines (very important, for example in 5G mmWave operation), and less radiation blockage. The aspects described herein focus on volume as opposed to focusing on area. In other words, it has been discovered by stacking that decreased X-dimension and the Y-dimension are important, and Z-height is somewhat less critical than previously believed.

Aspects may initially appear to increase Z-height somewhat because the aspects may, in fact, stack more components one on top of the other. But the result is a large reduction in the X-dimension and the Y-dimension, leading to solution of, or reduction of, the negative effects of the above issues of substrate cost, power lost through long feed lines, and radiation blocked by shields and other device obstructions.

Further, it is believed that the Z-height of POP stacking will, in fact, meet the requirements of current and future wireless user devices. Further still, the net area underneath or above the silicon that is used for intelligent antenna arrays, such as antenna elements 4403 , 4404 , and 4405 , seen in top view in FIGS. 44 A and 44 C , and in side view in FIG. 44 D take up significantly less room and require less overall feedline routing than in previous designs, according to some aspects. In other words, in the aspects of FIG. 44 D , antennas 4403 , 4404 are “under” and in close proximity to die 4409 , and antennas 4421 are “above” and in close proximity to the die. The proximity is such that the feed lines that transmit the signals have traversed a very small distance, which means less, and in some aspects significantly less, power loss that was due to the routing of long feed lines in previous designs.

Further, some discreet components, one of which is enumerated 4413 , and the connector 4417 , that are not needed in the antenna feed process and can be placed laterally to the antennas, which in the aspect of FIGS. 44 B and 44 D , is out to the left of the antennas and die, so that with the entire POP implementation, the feed lines that connect the die to the antennas on the top and bottom of the package traverse a shorter distance to the antennas. Substrate 4401 is illustrated as coextensive with the length of contacts 4407 of FIG. 44 B for purposes of illustrating the antenna elements but, as seen in FIG. 44 D , substrate 4401 extends over the entirety of the components and connector.

As mentioned above, in previous designs, the die and the discreet components were placed under a metal shield so that the discrete components would be co-located at the die with the metal shield on top of both. That combination is actually taller than the POP aspects disclosed herein due to the fact that in package-on-package, the larger discreet components such as 4413 can in some aspects be offset from the die, and also because some of the volume of the Z-dimension that was useless in previous designs becomes useable space. This is seen as the usable space 4425 in FIG. 44 D which is now available for placement of intelligent antennas or intelligent antenna arrays, such as antennas 4421 and the antenna arrays they form part of.

As mentioned above, surrounding the die are contacts 4407 in FIG. 44 B and in FIG. 44 D , which in some aspects may be solder balls. These contacts, for example solder balls as mentioned, contact at least one metallized layer of the substrate 4401 . This is seen at FIGS. 44 B and 44 D . In the cut-away of FIG. 44 D , the solder balls 4407 are seen to be also contacting both a metallized layer of substrate 4401 and a metallized layer of substrate 4419 . Therefore, in some aspects, if the solder balls surrounding the die are spaced at high density, the combination of the solder balls and these two metallized layers, top and bottom, act as a Faraday cage, becoming a shield for die 4409 , without the need for the bulk and height of the discreet metal shield used in previous designs. In some aspects, the contacts can be metallized vias and, if spaced at high density, can also act, in contact with an upper and a lower metallized layer, as a Faraday cage.

In some aspects the vias may be normal to the substrates. In some aspects the vias may be in pitched direction with respect to the substrates. In either case, the density of the spacing of the contacts, such as vias, or the density of the pitches between contacts are approximately λ/20 or less, where λ is the wavelength of the frequency of operation. In view of the described Faraday cage, the mechanical shield of previous designs can be absent in the described aspects, making the Z-height smaller still.

In addition, antenna elements 4403 , 4404 and antenna elements 4421 of packages 4401 and 4419 , respectively, need not be in the same transceiver. An important advantage of stacked packages is to allow multiple radios and multiple systems to be stacked on top of each other or alongside each other. In some aspects, antennas 4403 , 4404 may be coupled to a radio in a Wi-Fi system operating within a Wi-Fi frequency band, and antennas 4421 may be coupled to a radio in a mmWave Wireless Gigabit (WiGig) system, with the die 4409 having a Wi-Fi system configuration and a mmWave WiGig system configuration, in some aspects.

In some aspects, die 4409 may actually include a plurality of dies, for example one die configured for Wi-Fi operation connected to one group of antennas such as 4403 , 4404 and a second die configured for mmWave WiGig operation connected to another group of antennas, such as 4421 . Further, if antenna arrays such as patch elements 4403 , 4404 and 4421 are electrically opposite each other because of the overlay of antenna elements such as in the POP configuration of FIG. 44 D , and if the antennas are controlled to fire together, the radiation can be sideways in edge-fire operation such as indicated generally at 4420 in FIG. 44 D , in some aspects.

Further still, in some aspects, firing of the antenna arrays on opposing sides of the package can be algorithmically controlled to fire in opposing directions, even at a one hundred-eighty degree (180°) angle opposition; and in some aspects, firing of the antenna arrays on opposing sides of the package can be in the same direction.

As seen in FIGS. 45 A through 45 D and FIGS. 46 A through 46 D , the number of antennas can vary in different aspects due to stacking, in some aspects. In previous designs antenna placement was limited to only specific places of the package due to the room taken up by the discreet metal shield. However, because of improvements due to stacking technology described herein there is usually no such limitation. Further, as mentioned above, the metal shield of previous designs causes radiation blockage, additionally limiting placement of the antennas. This limitation is largely eliminated in POP designs. Consequently, in some aspects, the number of antennas and the size and the shape of the antenna array can be customized according to the requirements of the device into which as particular package will be incorporated.

The aspect illustrated in FIGS. 45 A through 45 D illustrates a variation of the aspect of FIG. 44 A through 44 D , with similar reference numerals referring to similar drawing items in both sets of figures. FIG. 45 A illustrates a top view of a substrate of one package of another two-package system, according to some aspects. FIG. 44 B illustrates a bottom view of the substrate of FIG. 44 A , according to some aspects. FIG. 44 C illustrates a bottom view of a substrate of a second package of the two package system of FIGS. 44 A and 44 B , according to some aspects.

FIG. 45 A illustrates package 4500 which includes substrate 4501 and antennas, one of which is identified as 4504 . The antennas are illustrated as dual patch antennas by the two matching points which are indicated by two dots on each antenna element. Substrate 4501 is illustrated in top view. FIG. 45 B is the bottom side of the substrate 4501 illustrated in FIG. 45 A . Illustrated in FIG. 45 B is RFIC die 4509 and discreet components, one of which is indicated as 4511 . Contacts 4507 , which in some aspects are solder balls, surround the periphery of the die and discreet components and contact at least one layer of substrate 4501 . The horizontal dimension L 2 of package 4504 is of substantially the same horizontal length as the contacts 4507 that form a Faraday cage, in some aspects.

In FIGS. 45 A through 45 D , antennas, such as patch antennas 4504 that may make up an antenna array on substrate 4501 and, patch antennas 4521 that may make up an array antenna on substrate 4519 may be placed symmetrically and vertically opposite each other as may be desired in some aspects. This will enable the antenna elements to be controlled to fire together and provide radiation in one or more desired directions, such as to provide radiation in opposing directions, normal to substrate 4519 by the array including antenna elements 4521 , and normal to substrate 4501 by the array including antenna elements 4504 . In some cases, depending on firing sequence, radiation of the two afore-mentioned arrays can be sideways in edge-fire operation as illustrated at 4520 .

FIG. 45 D illustrates the first package and the second package of FIGS. 45 A through 45 C , stacked in a package-on-package implementation, according to some aspects. The aspect 4506 of FIG. 45 D is much the same as that of FIG. 44 D . Like in FIG. 44 D , stacking is not only advantageous for Z-height improvement, there are advantages in being able to use the X-Y area to provide better antenna radiation. Such advantages were not available in some previous designs as explained above.

The aspect illustrated in FIGS. 46 A through 46 D is another variation of the aspect of FIG. 44 A through 44 D , with similar reference numerals referring to similar drawing items in both sets of figures. The horizontal dimension L 3 of package 3604 of FIG. 46 C is, as in FIG. 45 C , of substantially the same horizontal length as the horizontal length of densely packed contacts 4607 that form part of a Faraday cage to shield die 4609 . Discreet components 4611 have been placed laterally separated from die 4609 and are protected by an encapsulate 4614 in the package-on-package configuration of FIG. 46 D in some aspects. The use of an encapsulate within packages, or in a package-on-package aspect, are explained in greater detail below with respect to FIG. 47 D .

FIGS. 47 A through 47 D illustrate an example of an encapsulated POP implementation, according to some aspects. FIG. 47 A illustrates a top view of a substrate of one package of still another two-package system, according to some aspects. FIG. 47 B illustrates a bottom view of the substrate of FIG. 46 A , according to some aspects. The antenna elements 4704 , 4721 , which are patch antennas in some aspects, are essentially the same type of antenna elements as in FIGS. 44 A through 44 D , except that there are eight antenna elements 4704 and four antenna elements 4721 . The number and type of antenna elements are not critical, inasmuch as several types and number of antenna elements can be used in accordance with the needs and specification of the package at hand.

In some aspects, the antenna elements 4704 and 4721 may form two arrays, as indicated in FIGS. 47 A and 47 C , at different placements on the respective packages, according to some aspects. FIG. 47 C illustrates a bottom view of a substrate of a second package of the two package system of FIGS. 47 A and 47 B , according to some aspects. Noteworthy is the fact that antenna elements 4721 are located laterally from their position in the earlier figures, illustrating again the versatility of antenna placement enabled by the stacked package technology, which versatility was not available in earlier designs with a discreet metal shield that interferes with placement and radiation of the antenna elements. FIG. 47 D illustrates the first package and the second package of FIGS. 44 A through 44 C , stacked in a package-on-package implementation, according to some aspects.

Noteworthy in FIG. 47 D is the encapsulation, or mold, 4724 that covers the die 4709 and discreet components 4711 . The encapsulation can be mold, resin, adhesive, and the like. Through-mold vias 4715 connect the antenna elements of substrate 4701 and the antenna elements of substrate 4719 to die 4709 and function in some aspects as antenna feeds such as by way of strip lines 4712 , 4714 . Through-mold vias can be of various types, for example copper studs, solder balls, via holes plated with conductive epoxy, or any other suitable conductor. The encapsulation can be a fully definable material such as epoxy that can be a laser mechanically drillable material. Alternately, the mold can be a fluid material that actually molds around the studs, according to some aspects. As an example, the through-mold vias could be vertical pillar-like posts or studs, and the encapsulation can be so fluid that it can envelop all the posts (or studs). Therefore, the stud type through-mold vias could be placed first and then the encapsulation added after that. Alternately, the encapsulation can be added first and the through-mold vias can be added by way of drilling through the encapsulation and adding the conductive vias after drilling through the encapsulation. An advantage of encapsulation is that while the antenna elements remain close to the die as discussed above, the mold gives significant additional protection to the die, adding increased reliability and robustness without significantly increasing distance from the antenna elements to the die, other than increased distance due to placement of the antennas that might be part of the requirements for the package solution at hand.

An additional significant use of both X and Y space, and also Z-height, in mobile devices is the use of a connector, often a snap-on connector. Therefore maintaining the needed electrical connection from the electronics to the outside world, but at the same time removing the need for a connector, would save substantial and valuable X-Y real estate and Z-height in a package for a mobile device. Some have considered soldering the flexible coaxial cable, or other technology cable, that provides the electrical connection, and thereby avoiding using a connector. In some aspects the flexible cable be soldered in place and then molded into the package, much the same way molding of components by use of an encapsulation as described above. In some aspects coaxial cable 4722 of FIG. 47 D may be soldered, such as at 4720 , to the appropriate connection points, and is also secured by encapsulation 4724 in some aspects. An encapsulation, such as a mold, epoxy, or other encapsulation allows the coaxial cable to be connected to the substrate as a sealed solution, which can then be sputtered with some type of conductive material to make the overall combination shielded. Coaxial cables soldered and molded in this manner should have sufficient strength to maintain electrical connection without the need for the usual connector, the encapsulation making the coaxial cable connection sufficiently robust in the package to provide a solution for the need for electrical connection from the internal of the package to the outside world without need for an actual connector. In some aspects, the soldering as at 4720 may not be needed, and the encapsulation will be sufficient for needed robustness. This results in substantial XYZ space saving discussed briefly above. In some aspects the flexible cable may provide the needed connection by using a board to board connector.

In some aspects there is a need to have antennas on both top and bottom of a substrate that includes a die, and also to both reduce the Z-height and reduce the Y-dimension of the package. A solution that provides the above need uses two packages side-by-side. FIG. 48 A illustrates a top view of two packages of a two-package, side-by-side package system, according to some aspects. FIG. 48 A illustrates two different packages, 4800 , 4802 , in a side-by-side configuration, according to some aspects. Package 4800 seen generally in FIG. 48 A includes substrate 4801 . In a top view (“TOP”) of package 4801 is seen item 4808 which is a partial top view of metal shield that covers RFIC die 4809 and related components for RFI/EMI protection. Offset to either side of the shield 4808 are discreet components of the type that do not need shielding, one of which is designated at 4811 , and contacts, such as solder balls, 4810 . FIG. 48 B illustrates a bottom view of the two packages of FIG. 48 A , according to some aspects. On the bottom side of substrate 4801 of the package 4800 are antenna elements illustrated as dual patch antennas, one of which is designated as 4804 . Also illustrated are end fire antennas such as dipoles 4805 . While the current aspect illustrates patch antenna and dipole antennas, other aspects may use different antenna types, depending on the solution needed.

A second package is illustrated generally at 4802 of FIG. 48 A . Illustrated is a top view (“TOP”) of package 4819 , according to some aspects. Package 4819 includes contacts 4810 ′ which in some aspects are solder balls, discreet components, one of which is designated as 4813 , and soldered, and/or encapsulated, cable 4817 , discussed in further detail below. Bottom view (“BOTTOM”) of package 4819 illustrated in FIG. 48 B includes, according to some aspects, dual patch antenna elements, one of which is designated at 4821 , arranged in an array. Printed dipole antennas, one of which is designated as 4820 are configured for end fire operation, according to some aspects.

FIG. 48 C illustrates packages 4800 , 4802 configured side-by-side. The cable 4817 and discreet components 4813 of package 4802 are encapsulated by an encapsulation 4824 . The discreet components, one at 4811 , and the shield 4808 (not shown in the drawing for space-saving purposes) and die 4809 , are also encapsulated by an encapsulation 4814 . Noteworthy is the fact that package 4800 has been “flipped.” In other words, while package 4802 resides with its top (“TOP”) at the top of FIG. 48 C and its bottom (“BOTTOM”) at the bottom of FIG. 48 C , package 4800 is juxtaposed with package 4802 , with package 4800 residing with its top (“TOP) at the bottom of FIG. 48 C and its bottom (“BOTTOM”) at the top of FIG. 48 C . The two packages are secured by contacts such as solder balls at 4810 - 4810 ′ which are bonded together. This results in antennas 4821 (that are on the BOTTOM side of package 4819 ) facing downwardly and antennas 4804 , which are on the BOTTOM side of package 4819 , actually facing upwardly, to provide the solution needed, namely to reduce the Z-height and reduce the Y-dimension of the package, as noted above.

Reduction of the Z-height can be seen from the fact that the side-by-side design does not use vertical stacking in the manner of the above POP designs. The reduction of the Y-dimension can be seen from FIGS. 48 C and 48 D . In both figures, the dimensions of the antennas 4804 and 4821 are extremely small. Further, in FIG. 48 A the dimensions of the die are also extremely small. Both these factors lead to a smaller Y-dimension, enabling the design to be placed closes to the edge (the Y-dimension) of the user device, leaving additional X-Y space for the display of a mobile user device to reach nearly to the edge of the mobile device in the Y-dimension, in some aspects. Both sets of antennas 4821 , 4804 are fed by die 4809 . Antennas 4804 will have the desired extremely short feed lines from die 4809 because of the proximity of those antennas to the die. Antennas 4821 will have somewhat longer feedlines due to the offset, which in the present case is acceptable in order to fit in a specific mechanical design of the mobile device, in this example lowering the Y and Z dimensions in a very narrow space between the display screen and the end of the lid of a mobile device.

At least some of the needs described above, for varying polarities and varying spatial diversity of radiated radio waves at varying times, can be met by repurposing the standard Micro SD form factor card to include an mmWave antenna and transceiver device or other die, for wireless communication user devices such as mobile devices, in some aspects. The advantage of this repurposing is that this form factor may be used in mobile devices. Because the Micro SD format is the right size to incorporate a number from one to a few mmWave antennas, and for an RIFIC to be placed into an already existing form factor, there is no need to design a new form factor. Rather, the recognition that this existing form factor can quickly implement a solution that is accepted in hand-held/phone solutions, offers a tremendous cost savings and probable operational advantage. Further, the fact that the Micro SD form factor card is pluggable into a user device provides a form factor marketing advantage because it can be installed at will, or withheld from installation, as appropriate for an aspect.

The Micro SD form factor card can enable a population/depopulation of antennas and radio technology as needed with interchangeable frequency ranges to support different geographies. For example, different geographies may make different frequency bands available for use from a regulatory point of view. If the Micro SD cards are frequency band defined, then they can be swapped in and swapped out of a user device as needed to operate in the desired frequency band suitable for that particular geography.

Such form factor cards can be easily placed near the mobile platform extremities so the antennas are facing out. The form factor card already has an area that is RF exposed and not covered by socket metallization that is often found on substrates. This exposed area can be used for an antenna or small array to be embedded within the card. Given the ultra-small size of antennas that operate at mmWave frequencies, small antennas and/or small antenna arrays that fit in such areas are very effective.

In some aspects, multiple instances of such a card can be arranged to form a massive antenna array (MAA). Further, multiple sockets (placed outside the RF exposed area of the card) can also enable support of different frequency range sub-systems. Antennas could be end-fire type antennas in some aspects, but the exposed section outside of the socket metal structure could enable other types of antennas that radiate in other directions. Stated another way, and as will be discussed below with respect to FIG. 50 , the Micro SD card has an exposed area that is not covered by metallization associated with the socket that the Micro SD card is plugged into. Antennas of different types can be placed in this area to enable radiation in different directions. In some aspects end-fire antennas can be used because the end-fire radiation pattern direction would be lateral with the Micro SD card orientation. But other antenna types with other radiation pattern coverage can also be used.

As used in the disclosure, such terms as “front,” “back,” “up,” “down,” “side,” and the like, are used relative to the orientation of the drawing. FIG. 49 is an illustration of the various sizes of SD flash memory cards. The SD flash memory cards may be incorporated in the transmit circuitry 315 , the receive circuitry 320 , the RF circuitry 325 , and the antenna array circuitry 330 of mmWave communication circuitry 300 shown in FIG. 3 A , although the SD flash memory cards are not limited to such. The various sizes of the SD form factor are seen generally at 4900 . The Standard SD form factor card is seen in front view 4901 A and rear view 4901 B. Electrical contacts are seen at 4903 . Dimensions of the Standard SD form factor are illustrated in millimeters. The Mini SD form factor is seen at 4905 , in front and rear view also with dimensions indicated in millimeters. The Micro SD form factor and its dimensions are seen at 4907 , also in front and rear view.

In some aspects, the Micro SD form factor card can be used effectively for mmWave communications with a change in content and functionality to adapt the card for mmWave operation in wireless communication devices. One reason for this is that, as discussed briefly above, the size of the Micro SD card format enables it to be used for mmWave operation, particularly since space in a wireless communication device is at a premium and the size of the Micro SD format provides a space advantage for use in mobile devices where space is scarce. Further, given that the Micro SD card has electronic contacts at a “rear” area 4909 , the “front” area 4911 A, 4911 B is the section of the Micro SD card which is exposed and not covered by metallization of the socket which the Micro SD card is plugged into. This makes it attractive for millimeter wave frequency sub-systems with antennas because the antennas can be in the exposed region while other parts like the transceiver can be covered by metallization acting as a shield. In some aspects, antennas are placed in the internal region of the card at 4911 A and 4911 B, discussed in greater detail below. Antennas require un-metalized regions where they can radiate out of the wireless sub-system. Being un-metalized, the internal region of 4911 A and 4911 B are ideal for placement of antennas.

FIG. 50 illustrates a three dimensional view of a Micro SD card with content and functionality changed to repurpose the card for mmWave wireless communication operation, according to some aspects. The Micro SD card form factor card includes card 5001 seen in a three dimensional view with the front 5001 of the card in full view. Electrical contacts 5003 on the back of the card are illustrated in hidden view. As part of the change in content and functionality alluded to above, RFIC 5005 is illustrated within the Micro SD card, therefore also shown in hidden view. The internal part of the card, if viewed along section XX-XX, shows antennas, which are illustrated in the figure as dipole antennas 5107 A, 5107 B, is also in hidden view inasmuch as they are internal to the front of the card at 5009 according to some aspects. In other words, the antennas need to be exposed to radiate outward from the platform in which they are placed.

The metalized connector for these types of SD cards being at the back 5003 , leaves the thick section 5009 of the Micro SD card 5001 without metal covering it so that the thick section is ideal for antenna placement. Being so small, the card is also well-suited for mmWave frequencies since the antennas would be smaller than the available area and thus more than one antenna can be included to form an array, and/or antenna diversity may be included. This fact offers an additional advantage that the antennas can be used for Multiple-In Multiple-Out (MIMO) operation. Stated another way, multiple antennas can be used in different ways in radio systems. They can be simply combined, they can be used to electrically steer a beam, and they can be used to support MIMO whereby different antennas support a separate radio chain that can be used to transmit/receive as separate stream of information independent of the other antennas in the solution, and additional functions can be implemented as well.

As an example of MIMO operation, antenna 5107 A may be used to support one MIMO stream and antenna 5107 B may be used to support a second MIMO stream according to some aspects. This can also be implemented using antennas of different polarization. The RFIC 5005 would be designed to support these configurations and the number of streams. In this aspect two antennas 5107 A and 5107 B are illustrated, but this scheme is not limited to only two.

The RFIC 5005 and the antennas 5107 A, 5107 B, may be etched, printed, or otherwise configured on or within a PCB inside the sub-system at 5009 , which may be over-molded into the desired Micro SD card shape, according to some aspects. The thickness of section 5009 can be used in some aspects to also incorporate taller antenna structures like those needed for vertical polarization antennas. The bottom of the PCB would have the edge card contacts at the bottom that make contact to the spring contacts in the Micro SD socket. The antennas illustrated at 5107 A, 5107 B, as mentioned above, are dipole antennas and could radiate out a hemispherical pattern, while other types of antennas could be more sectorial in pattern. The dipole antennas could be considered edge-fire inasmuch as they also radiate out on the same plane as the PCB and Micro SD card, even though they also radiate up and down. Since the exposed part 5009 of the card 5001 is at the edge, edge-fire antennas are more likely to be used in this form factor, as seen in FIG. 52 , discussed below. This form factor also coincides with the type of platform this could be integrated into, such as phones. In other words, Micro SD cards are already the current standard memory module form factor for phones because they are relatively small but have the ability to also support high capacity memory storage.

Further, when arranged in array formation with multiple instances of such Micro SD cards, then more options come into play and different antenna types radiating in different directions may be used. Being a very small card means the card can support antennas of the same order of magnitude of size that equates to frequencies in the mmWave range. Just as an example, there are WiFi wireless solutions in the Mini SD card form factor because this size is larger and can support larger antennas that coincide with the frequency range as that of the WiFi frequency range (centimeter waves). The Micro SD being smaller can support a smaller antenna usable at mmWave frequencies, or a few of such antennas, which means that the antennas can be used to from arrays when placed at appropriate distances one from another, the distances being a function of frequency.

FIG. 51 A illustrates a Micro SD card of FIG. 50 showing the radiation pattern for the dipole antennas of FIG. 50 , according to some aspects. The radiation out of the dipoles 5107 A, 5107 B is a sort of half doughnut that radiates laterally but also radiates up and down. The other half of the radiation pattern may be blocked by the phone/hand-held device or the metallization of the Micro SD socket. FIG. 51 B illustrates the Micro SD card of FIG. 50 with vertically polarized monopole antenna elements standing vertically in the exposed area 5109 B that is limited in Z-height, according to some aspects. Other semi wrapped around vertical polarized elements may also be used. Folded dipoles may also be used. FIG. 51 C illustrates the Micro SD card of FIG. 50 with folded back dipole antennas 5107 AC, 5107 BC, according to some aspects. FIGS. 51 A, 51 B, and 51 C illustrate only some of the various types of antenna elements that may be used in various aspects, both singly and in arrays.

FIG. 52 illustrates three Micro SD cards modified as discussed above to provide multiple instances of such a card, each of which may have a plurality of antennas per card, according to some aspects. Seen generally in FIG. 52 is a combination of a mother board 5201 , having attached thereto three Micro SD cards, 5203 , 5205 , 5207 , the cards being modified from the usual flash memory function, as discussed above. The antennas may be dipole antennas 5107 A, 5107 B, in each card, as discussed above, and radiate in end fire direction as illustrated by the arrows proceeding from each card, in some aspects. As illustrated in, and as discussed with respect to, other figures herein different types of antennas may be used in some aspects to implement antennas that fulfill various needs, according to the solution at hand. While three arrays are illustrated, this can be extended in either direction by adding additional cards along the X-axis to increase the array size. In fact this can also be stacked in the Z direction to expand the array in both the X and Z dimensions, as illustrated by the coordinate system of FIG. 50 , depending on available volume. By adding many Micro SD cards next to each other or stacked atop each other, with the proper antenna to antenna distances and available volume, a massive antenna array (MAA) can be configured. The number of antennas on each card can be from one antenna to a plurality of antennas on each card, depending on the frequency of operation, and therefore the wavelength A.

Space in mobile devices for wireless communication is usually at a premium because of the amount of functionality that is included within the form factor of such devices. Challenging issues arise, among other reasons, because of needs for spatial coverage of radiated radio waves, and of maintaining signal strength as the mobile device is moved to different places, or because a user may orient the mobile device differently from time to time. This can lead to the need, in some aspects, for varying polarities and varying spatial diversity of the radiated radio waves at varying times. When designing packages that include antennas operating at millimeter wave (mmWave) frequencies, efficient use of space can help resolve issues such as the number of antennas needed, their direction of radiation, their polarization, and similar needs. At least some of these needs can be met by a ball grid array (BGA) or land grid array (LGA) PCB with an area that is specially cleared of balls or LGA pads, as the case may be, to enable antenna elements to radiate out from various sides of the PCB that has an attached millimeter wave (mmWave) transceiver in some aspects.

FIG. 53 A is a side view of a separated BGA or LGA pattern package PCB with an attached transceiver sub-system, according to some aspects. The separated BGA or LGA pattern package PCB may be incorporated in the RF circuitry 325 of mmWave communication circuitry 300 shown in FIG. 3 A , although the separated BGA or LGA pattern package PCB is not limited to such. The BGA or LGA PCB has the usual layers that are substantially parallel. Typically, BGA and LGA packages populate the balls and pads in a relatively uniform spreading across the entire sub-system in order to attach the sub-system onto a mother board (MB). BGA balls 5305 , 5306 are illustrated. An area 5303 , free of balls and/or LGA pads, is intentionally created so that this free area can be used for an antenna section wherein the antenna elements can radiate outward if an appropriate opening is made on the MB to which the PCB 5301 is attached. In other words, area 5303 , sometimes referred to as a “gap,” should be “contact free,” so as to place the antenna elements to enable the antennas to radiate out freely. Stated another way, gap 5303 in the BGA/LGA attach points enables antenna elements to be placed in the gap and radiate out through the gap, or laterally if the antenna elements are edge-fire type

As used in this patent, the term “top,” “bottom,” “upward,” “downward,” “sideways,” are used with reference to the orientation of the drawing and are not meant to restrict the direction of radiation when the package is implemented in a mobile or other device, which may be oriented in any direction. Hence, the radiation described herein is, in practice, in an outward direction, regardless of the orientation of the package in a user device.

In one aspect, downward (outward) facing antenna elements 5315 , 5316 , 5319 and 5321 , here illustrated as patch antennas, which, in some aspects, may be an array of patch antennas or other antennas, radiate downwardly. This is illustrated in the drawing by wave patterns 5316 , 5318 , 5320 and 5322 . An RFIC transceiver 5307 may be affixed to the top of the sub-system, and is protected from radio frequency radiation (RFI) and electromagnetic interference (EMI) by shield 5309 sub sine aspects. Antenna elements 5311 , 5313 that are upwardly facing in the drawing may radiate in the upward (outward) direction 5312 , 5314 , respectively. The ability to radiate out of multiple directions out from a platform provides advantages.

For example, while radiation is illustrated in opposing directions, the illustrated patch antennas could be replaced with other antenna types that radiate sideways, such as end-fire or edge-fire antennas, and can be placed at the edges of the sub-system. Thus the described sub-system can make use of different types of antennas that have different types of advantages including direction of radiation and polarization.

As one example, the patch antennas illustrated have an advantage that each can have two orthogonal feed points to create two polarizations, but their radiation is broadside in nature, so they would work well in the configuration illustrated. Many antenna elements arranged on the module can be used for beam steering in an array in some aspects. Further, this type of sub-system arrangement may find use in multiple-in multiple-out (MIMO) antenna arrays, and arrays configured for spatial diversity. Spatial diversity can be achieved by having antennas that have radiation patterns in different directions. For example patch antennas on the top radiate upward and patches on the bottom radiate downward. Other antenna types can be introduced to radiate sideways like edge-fire antenna types, thus achieving spatial diversity in some aspects.

While illustrated in side view as antenna elements 5311 , 5313 in FIG. 53 A , FIG. 53 C will show that there can be a plurality of such antennas, such as 5330 , 5331 and 5332 , 5333 , as discussed below. While a particular number of antennas is described, the number of antenna elements can vary from aspect to aspect, as would be understood by one of ordinary skill in the art. Frequency of operation and antenna size determine how many antennas can actually fit in the given area/space to be effective in an array. Also, the type (monopole or stacked patch antennas, dipole antennas, and other types) and their arrangement, for example, in arrays, can also vary. Further, in many small form factor devices, because area/space is so precious, a sub-system that can radiate in multiple directions, as discussed above, will have a high effective usage of area/space with great (or perhaps greatest, in some aspects) coverage.

FIG. 53 B is a side view cross section of the sub-system of FIG. 53 A , according to some aspects. FIG. 53 B illustrates MB 5323 , with a cutout 5304 that is implemented to enable the antenna elements 5315 , 5317 , 5319 , 5321 to be exposed outwardly for radiation. In other words, the separated pattern 5303 in the package enables antenna radiation out from the attachment side of a mmWave antenna and transceiver sub-system. Because of the cutout in this area, the antenna elements 5315 , 5317 , 5319 and 5321 can radiate freely with essentially nothing blocking them, and this enables another direction of radiation in the limited area/volume of the solution. The antenna elements 5315 , 5317 , 5319 and 5321 are on the same side as the BGA/LGA 5301 attachment side (the side where the BGA/LGA attaches to the MB) in some aspects. In some aspects the cutout is implemented as an outlined, machined cutout made by router that runs along the PCB outline.

Also illustrated are antennas 5311 and 5313 on the top side of the sub-system. In some aspects, discrete electronic components that require Z-height can fit in cutout 5304 in the PCB. In some aspects the shielded RFIC itself, can be placed in the cutout at the contact free area for operation, and save on overall Z-height of the solution. Stated another way, integrated circuit chips such as RFICs are typically accompanied with some discrete components that complement the chips, for example, decoupling capacitors, and other functions as well. These components could be placed in gap 5304 , instead of the antenna elements being in the gap, in some aspects. However, if the components are part of the radio transceiver circuitry positioned in the gap, appropriate RFI/EMI shielding should be implemented, as alluded to above.

FIG. 53 C is a top view of the sub-system 5301 illustrating a top view of shield 5309 and further illustrating cutout or gap 5304 . As can be seen, and as discussed briefly above, the upwardly facing antennas 5330 , 5331 and 5332 , 5333 are, in some aspects, two arrays of two antenna elements each. Other configurations of antenna elements are possible, in accordance with a given design by one of ordinary skill in the art to implement a solution that is appropriate to the needs of a given situation.

While the description above discusses use of the sub-system in a mobile device, the sub-system can also be used in a base station, although a base station implementation might not benefit from having radiation in both or multiple directions. While a base station array size may be limited in one axis, modularity can help to arrange the sub-systems in desired directions including arranged circularly around a pole. FIG. 53 E shows an arrangement of sub-systems arranged circularly around a pole, for radiation coverage in substantially all directions, according to some aspects. Sub-systems 5341 , 5342 , 5343 , 5344 , 5345 , 5346 , 5347 , 5348 are attached to pole 5341 . Each sub-system could be as illustrated in FIG. 53 A , with the BGA/LGA laminate 5301 attached to the motherboard 5323 . Direction of radiation would then be as indicated by the arrows in all, or substantially all, directions.

While a rectangular shaped sub-system is shown, other shapes are possible, such as, for example, a square or corner shape. FIG. 53 D shows a U-shaped cutout in the PCB to enable the antennas to radiate out through the cutout, in accordance with some aspects. The array of pads 5324 , 5326 , which in some aspects are gold pads, are the electrical contacts used for the signaling to the sub-system and also serve as the mechanical attachment when the sub-system is soldered onto them.

FIG. 53 F illustrates a sub-system in a corner shape, according to some aspects. Illustrated in the Top view is sub-system 5350 with four antenna elements 5351 . One of the four antenna elements is shown in dash line for purposes of illustrating that there could be antenna elements on both sides of the sub-system. Sub-system 5350 is illustrated as being λ×λ in size in the illustrated aspect because if the antenna element itself is λ/2 (as discussed further below), then with overhead and grounding all around the elements, the realistic size of a sub-system with a 2×2 antenna array, as illustrated, would be approximately λ×λ. The Bottom view illustrates the shielded RFIC, with shield 5356 and RFIC 5355 illustrated in full line view for purposes of clarity of illustration, sitting in gap 5304 E. BGA balls or LGA balls are illustrated at 5354 . Antenna elements 5351 are shown as broadside elements, such as patch antennas, but could be replaced with end fire elements, such as dipoles, for end fire coverage in some aspects.

FIG. 53 G illustrates the sub-system of FIG. 53 A placed in a corner of motherboard 5323 , with 5361 in hidden view being the RFIC shield and the antenna elements being as 5362 , with only one antenna element numbered in the interest of space saving in the drawing. FIG. 53 H illustrates a side view of the sub-system 5364 attached to motherboard 5323 by BGA balls 5306 , illustrating the antenna elements 5362 , 5263 in side view looking into the page, and the shielded RFIC 5367 with discreet components also within the shield 5368 .

FIG. 53 I is a top view of a configuration of a dual-shield sub-system 5370 having a shape for use in a corner, according to some aspects. Sub-system 5370 is illustrated with a cutoff corner edge 5376 . Four broadside antenna elements 5371 are placed adjacent sides of shield 5374 which shields RFIC or other integrated circuitry 5375 , which is shown in solid line for purposes of illustration but in fact is within shield 5374 . End fire antenna elements 5372 are placed around the periphery of the sub-system. Dimensions are as illustrated for the antenna elements 5377 , similarly to antenna elements 5371 , and with reference thereto. FIG. 53 J illustrates a slide view of the sub-system of FIG. 531 A , according to some aspects. Illustrated is a top shield 5383 with integrated circuitry 5382 , and bottom shield 5384 with integrated circuitry 5385 . Antenna elements 5386 , 5387 and 535388 , 5389 appear on opposite sides of the sub-system 5300 . The sub-system is attached to MB 5323 by solder or other suitable attachments as illustrated.

The BGA balls (or LGA pads), at the two ends of the arrangement have an additional advantage during assembly because no extra support is needed when the sub-system is soldered to the MB. Observing the case where the sub-system is soldered or otherwise attached at the corner of a PCB, as at FIGS. 3 C and 4 E , there is nothing to actually hold the sub-system up in space while the balls or LGA pads get soldered along the corner “L”. The sub-system would fall from its own weight during the process. However, with a rectangular sub-system with the balls or LGA pads at the far ends, such as at FIG. 53 B , there is no fear that the sub-system would fall anywhere other than to the place it is supposed to be in because of gravity.

In a PCB assembly process the PCB may be placed on a conveyor belt. It may then be solder pasted and then by pick-and-place (or manually), components are placed in their positions over the solder pasted pads. Then the PCB goes through an oven and the solder melts beneath the components soldering them to the PCB. The PCB is then cooled and cleaned yielding an assembled PCB. In some cases, some components are also glued in place prior to the soldering process so they don't move. In the case of a corner, however, that may not help significantly because gravity may pull the sub-system off the PCB before it gets soldered. In such cases a special mechanism should be added to support the part that is likely to “fall off”, and hold it in place.

60 GHz system-in-package SIP production testing is likely to be very expensive or possibly unaffordable for wide deployment of 60 GHz or 5G technology. Signals would be radiated and received at a millimeter wave (mmWave) frequency range such as 60 GHz for some aspects, but 28 GHz, 73 GHz, or other mmWave bands are also available, for other aspects. Generally speaking, testing should include antenna testing due to the complexity of the SIP and any associated assembly. Therefore the test would be a radiative test. On-chip “built in self-test” (BIST) can be used to help with this testing, but BIST will likely not include the antenna element testing.

Typically, the device under test, here a SIP, includes a phased antenna array so multiple antennas and transceiver elements would need to be tested. These requirements render conventional testers unsuitable since their operating frequencies are much lower than mmWave frequencies, and typically such testers do not include radiative tests. Instead, conductive or contact testing, like probing, is typically used. However, 60 GHz systems are extremely sensitive to even very small non-idealities. For example, if a 60 GHz probe is used to test the gain of an amplifier, the repeatability of the landing, and the aging of the probe, can introduce many dBs of gain variation, making probe-based 60 GHz production testing very difficult.

Further, 60 GHz systems typically integrate the 60 GHz antennas on the package of a Radio Frequency Integrated Circuit (RFIC), including the SIP. This eliminates cable losses which would be very high at 60 GHz and allows convenient implementation of phased arrays that achieve desired coverage. Such package configurations would also have to be tested, which is an expensive proposition. In addition, high-volume manufacturing (HVM) testing needs to comprehend antenna and assembly failure modes, e.g., misprocessing of the antenna substrate, or imperfect assembly of the RFIC on the substrate. Experiments have shown that 60 GHz systems are much more sensitive to assembly imperfections compared to 2.5 GHz-6 GHz systems. For these reasons, it is desirable to include the antennas in the 60 GHz HVM testing. Therefore, it is usually thought that nearly prohibitively expensive 60 GHz equipment would need to be added on testers to perform 60 GHz tests.

Disclosed is a practical way to do HVM production self-testing of 60 GHz systems by addressing the issues discussed above by use of a loopback test. A loopback test refers to the routing of electronic signals, digital data streams, or flows of items from their source through the system and back to their source without intentional processing or modification. This is primarily a way of testing the transmission or transportation infrastructure of an SIP.

Various examples exist. As one example, a communication channel with only one communication endpoint may be tested. Any message transmitted by such a channel is immediately and ideally only received by that same channel. In telecommunications, loopback devices perform transmission tests of access lines from the serving switching center, which usually does not require the assistance of personnel at the served terminal. In telecommunications, loopback, or a loop, is a hardware or software method which feeds a received signal or data from the sender back to the sender. It is used as an aid in debugging physical connection issues. As a test, many data communication devices can be configured to send specific patterns (such as all ones) on an interface and can detect the reception of this signal on the same port. This is called a loopback test and can be performed within a modem or transceiver by connecting its output to its own input. A circuit between two points in different locations may be tested by applying a test signal on the circuit in one location, and having the network device at the other location send a signal back through the circuit. If this device receives its own signal back, this indicates that the circuit is functioning.

Using 60 GHz equipment as an alternative to the above 60 GHz system test can either be well characterized/stable using expensive equipment (e.g., vector Network Analyzer (VNA)) or a custom-made sub-system with third party components. Both approaches have limitations in terms of cost, stability of measurements, and/or aging of the custom-made sub-systems. The disclosed, self-contained, self-test solution uses the 60 GHz system to test itself. This obviates the need for expensive/sensitive 60 GHz equipment. It also naturally includes the antennas in the testing, which is key for the 60 GHz System-in-Package, and also addresses inevitable on-chip and on-package crosstalk issues. A reflector on the tester enables baseband-to-baseband loopback that includes the antennas. Loopback self-test schemes are sometimes used to test RFICs at lower frequencies but without testing antennas. The disclosed system extends the loopback to include the antennas, which are components of the 60 GHz system, according to some aspects.

FIG. 54 A illustrates a top view of a 60 GHz phased array System-in-Package (SIP), according to some aspects. The SIP 5400 may be incorporated in the RF circuitry 325 of mmWave communication circuitry 300 shown in FIG. 3 A , although the SIP 5400 is not limited to such. SIP 5400 includes antenna array 5401 and a 60 GHz RFIC 5403 on or within substrate 5405 , which may be a low temperature co-fired ceramic (LTCC), according to some aspects. RFIC 5403 receives input signals via connector 5406 . Antenna array 5401 includes a 542-element array seen in greater detail at 5402 . The array is fed by RFIC 5403 via a series of micro-strip feed lines, according to some aspects. One antenna element of the array, seen at 5407 , is fed by feed line 5409 , according to some aspects. A second antenna element of the array, seen at 5407 ′, is fed by feed line 5409 ′. Feed line 5409 ′ is structured in such a way as to slow the RF signal from the RFIC. In other words the feed line lengths are matched so that group RF signal delay to the antennas are matched. This helps with beamforming calibration (e.g., less static mismatch, reduced sensitivity of calibration to channel frequency). The series of balls 5413 are bumps for signal connections to the package when the chip is flipped onto the package, according to some aspects. While a 542-antenna array is illustrated, in some aspects more than 542 antennas or fewer than 542 antennas may be used.

FIG. 54 B illustrates a side perspective view of the SIP of FIG. 54 B , according to some aspects. FIG. 54 B illustrates stepped platform 5404 including three step-like levels, 5408 , 5410 , 5412 , according to some aspects. Antennas 5412 are on the highest level because antennas usually require additional substrate layers for proper operation. Level 5410 which includes RFIC 5403 does not include vias, which may not helpful for mmWave signals. So feed lines are routed directly on the top layer 5412 , in some aspects. In other aspects, the feed lines go “inside” the dielectric to reach the antennas at level 5410 . Level 5408 is thinner to provide room for the connector 5406 .

FIG. 55 illustrates a 60 GHz SIP placed on a self-tester, according to some aspects. The SIP placed on the tester is seen generally at 5500 . A tester useful for the tests such as those described herein, generally includes at least one computer, power, software, computer-readable hardware storage that includes computer instructions which, when executed by the computer, tests a system under test according to predetermined tests, and docking capabilities including a test bed for receiving and securing the systems under test. SIP 5400 may be the type of SIP illustrated at 5400 of FIG. 54 A that includes 542 antennas (one of which is enumerated as 5401 ) and RFIC 5403 on substrate 5405 . RFIC 5403 may include power amplifier 5416 configured to drive the antennas of SIP 5400 and low noise amplifier 5420 configured to receive from the antennas of SIP 5400 . Phase shifters 5414 , 5418 may be included to aid in beamforming as needed. One of the antenna elements T of the phased array is set in transmit mode. The transmit (TX) antenna 5422 transmits a 60 GHz signal. A reflector 5502 is fitted on the tester and reflects the 60 GHz signal back to the SIP, where it is collected by a receive (RX) antenna 5424 . The reflector in some aspects would be on top of the IC being tested, hence on top of the tester discussed above, and discussed in further detail below. Some current testers have an arm with a mmWave horn antenna and down-converter/up-converter to receive or transmit the reference signals for calibration. In the disclosed system, the reference radio at the end of the arm of current testers would be replaced by a simple reflector 5502 . This should allow an easy fit for today's testers (which typically test circuits designed for less than 60 GHz) to be adapted for mmWave testing.

The signal of the receive-antenna 5424 is amplified and down-converted in the RFIC in some aspects. The arrangement of FIG. 55 establishes a loopback around the entire 60 GHz system which can be used to measure certain key performance metrics (e.g., gain), determine if the part is good or should be discarded, and/or calibrate the part against manufacturing variations such as mismatches discussed in greater detail below. This arrangement solves two important issues of 60 GHz HVM testing:

1. It establishes a baseband-to-baseband loopback on the tester. Therefore, the tester does not need an expensive 60 GHz upgrade. Only an inexpensive reflector (e.g., metal fixture) may be needed to be fitted on the tester in some aspects.

2. The loopback includes the 60 GHz antennas. The loopback test can therefore pinpoint antenna-related issues, (e.g., substrate misprocessing), or assembly imperfections. Because antennas are in the loopback test there is complete system testing, not only RFIC testing.

FIG. 56 A illustrates a test setup for a first part of a test to address undesired on-chip or on-package crosstalk in an SIP, according to some aspects. In FIG. 56 A, 5600 indicates a first setup to address crosstalk. In some aspects the elements are the same elements as those illustrated in FIGS. 54 A and 54 B , and the same reference numerals will be used for clarity.

RFIC 5403 includes power amplifier 5601 and low noise amplifier 5603 , each of which is respectively coupled to antennas 5407 , 5407 ′. Crosstalk is indicated at 5605 , 5607 . The system under test 5600 is on the tester as illustrated at FIG. 55 but with the reflector removed, which may be done automatically by an electromechanical removal/add mechanism in some aspects. In FIG. 56 B, 5602 illustrates a second test setup to address undesired on-chip or on-package crosstalk in an SIP, according to some aspects. In some aspects the elements of FIG. 56 B are the same as those illustrated in FIG. 56 A except that the reflector 5502 has been added back, which may also be done automatically by an electromechanical removal/add mechanism in some aspects.

FIG. 57 illustrates automated test equipment suitable for testing a 60 GHz phased array SIP, according to some aspects. Illustrated at 5700 is automatic test equipment to which the test setups of FIGS. 55 through 56 C may be attached. Illustrated is a Cassini™ 16™ automatic tester 5701 which, when modified as described herein, is an example of a system that may be programmed to implement the tests discussed. Those of ordinary skill in the art would recognize that the described tester model is one of a number of testers that may test at less than 60 GHz and that can be modified for 60 GHz tests as described herein. Tester 5701 includes mmWave port architecture 5703 , production waveguide interconnect 5705 , and mmWave Test Instrument Module 5707 , according to some aspects. The tester may be modified by adding the test aspects described above.

FIG. 58 illustrates a reflector that may be added to the automated test equipment of FIG. 57 , according to some aspects. Illustrated conceptually at 5800 , reflector 5502 is attached above test bed 5801 . Test bed 5801 , which may be the appropriate system test bed for mounting systems under test 5803 to the tester of FIG. 57 may include or interface with an automatic electromechanical device to place the systems on the test bed for testing, and to remove the systems after test, as is usually done in HVM. Reflector 5502 is connected to the tester, in the aspect under discussion, conceptually by mechanical arm 5805 . Those of ordinary skill in the art would recognize that although the attachment is illustrated conceptually by mechanical arm 5805 , in practice, attachment may be by electromechanical removal/adding mechanism for use in the crosstalk tests described herein, in some aspects. For example, in some aspects there may be an arm on the side of the tester, to which arm the reflector would be attached. There might also be associated motors to provided tilt for the reflector if appropriate.

Many 60 GHz systems are rather asymmetric, that is, they are meant to primarily source a high-rate signal (e.g., Blue ray player), or sink a high rate signal (e.g., HD TV). Having said this, many 60 GHz systems still include both TX and RX paths. For example, one example product solution has the following parameters:

In cases like the above, the loopback receiver can be one of the already available receivers of the system under test, resulting in minimum overhead for the scheme of FIG. 55 . The RFIC of the system under test is a phased array transceiver in some aspects, so there are multiple RXs and TXs. Therefore, one of these RX may be dedicated as the reference receiver while the TX (one TX, or all TXs with beamforming) is/are being tested. In other words, there is no need for extra mmWave receivers because the ones on the RFIC itself may be used in some aspects. However, a dedicated test-receiver can also be used if desired. 60 GHz circuits are usually small due to the high operating frequency, so even a dedicated receiver would be a small cost overhead.

The loopback test of FIG. 55 can be used to perform a host of important 60 GHz tests, according to some aspects. Tests may include:

1. Turn on the TX elements and transmit a radio signal via a TX antenna, and turn on the RX elements and receive the radio signal via a RX antenna, one by one, where the radio signal is reflected by the reflector to the RX antenna, and measure the received radio signal that is looped back via the reflector to the RX antenna. A baseband signal may be used for the radio signal. If one of the loopback measurements is lower than the rest, this would indicate a bad TX path (e.g., bad assembly). The defective path can be disabled and the part can potentially be sold as a good part (phased arrays have large redundancy, so one element less is likely to be acceptable for link-budget purposes), according to some aspects. Such a test is an attempt to make sure that all TX have same power levels and are well matched. Loopback signals can be known signals to aid measurement of TX impairments, for example, even be a simple continuous wave mmWave signal, like a single tone, with no data on it, according to some aspects.

2. Compare the loopback baseband signal strength against its expected value. If the loopback signal is correct, this indicates that the whole system (TX RFIC)-(TX antenna)-(RX antenna)-(RX RFIC) is acceptable, according to some aspects.

3. Check functionality and measure the characteristic of the phase shifter using the loopback signal. If the phase shifter characteristic is known, any phase shifter imperfections can be corrected with appropriate lookup table (LUT) mappings, according to some aspects. This test allows adjustment of the phase of each antenna element so that the beam (RX or TX) can be steered in the desired direction. As used here, characteristic of the phase shifter means a phase shifter control code versus the actual achieved phase shifting. This test can also be done across different frequencies or RF channels, according to some aspects. As an example, one RX can be selected as the reference RX, and then only one TX can be turned on, and vary the phase of the TX signal with the TX phase-shifter, such as phase-shifter 5414 of FIG. 55 , according to some aspects. The resulting TX phase can be measured at the RX by looking at the phase of the baseband signal (the demodulated baseband signal has both I and Q components, so phase can be measured). Phase measurement is always relative, so for example the TX phase shifter can be set to zero, the reference phase at the RX can be measured, and then sweep the TX phase and measure the new phase relative to the reference value. In this way, the characteristic of that TX phase shifter in terms of control versus phase shift can be measured. Once the real control code versus phase shift of the TX is measured, the look-up table referenced above can be used to map essentially every specific phase shift to the control code.

4. Turn on the TX elements one by one and measure the amplitude and phase mismatch between paths (e.g., due to manufacturing variations (RFIC, package, assembly)). For the same setting in the amplitude and phase shifter, all the TX signals should have the same amplitude and phase. However, due to process mismatch, variation of the antennas, or routing on the package, this may not be the case. So by comparing all TX measurements, mismatches between all TX elements can be extracted. By measuring the received baseband signal, in terms of amplitude and phase, one of the TX signals can be used as reference to which the other TX signals are compared.

Accurate mismatch measurements may be needed for accurate beamforming. It may appear that the tolerance of the reflector position in FIG. 55 could distort the mismatch measurements by changing the distance travelled by the waves. However, careful analysis has shown that reflector position tolerance errors are essentially immaterial as far as beamforming is concerned, according to some aspects.

All TX elements can be turned on at the same time and loop-back measurements can be used to estimate the array gain which is key parameter for a 60 GHz array, according to some aspects. If all the TX elements are on with the same power and all phases aligned, the tester should receive 20*log (N) higher power at RX, where N is the number of TX elements. The array gain of 10*log 10 (N) is from beamforming; the additional array gain of 10*log (N) is from the fact that there are N TX elements on at the same time (so N times higher TX power).

Many of the tests above have been described with an emphasis on TX testing. Similar tests can be used for RX testing. For example, one of the TX's of the system or a dedicated TX can be used to transmit the signal for loopback, according to some aspects. The tests are essentially the same for TX, with the reference RX swapped with reference TX and the TX swapped with RX for each of the antenna elements. It is conceivable that the RX test element in FIG. 55 is defective. Many practical 60 GHz systems already include more than one RX, so measurements over different RX's can be used to eliminate this risk, according to some aspects.

The above tests represent a series of tests that may be used for testing an SIP or other system that operates by transmission and reception of radio signals. Those of ordinary skill in the art would recognize that the numerical sequence in which the series of tests are run is not a prerequisite and that the tests may be run in any of various sequences depending on the needs of the system to be tested. Further, additional tests than those described may be run, again depending on the needs of the system to be tested. In practice the series of tests could be programmed into computer-readable hardware storage as instructions that when executed by a computer cause the computer to control the performance of the series of tests.

Undesired crosstalk between the TX and RX (on-chip and on-package) establishes a parasitic loopback path that does not go through the antennas as indicated by arrows 5605 , 5607 in FIG. 56 A , according to some aspects. Such parasitic loopback path can distort the loopback measurements. In the proposed scheme of FIG. 55 this can be addressed as follows, according to some aspects:

Step 1— FIG. 56 A : Remove the reflector 5502 . Take the loopback measurement. This resulting term represents the on-chip and on-package crosstalk.

Step 2— FIG. 56 B : Add the reflector 5502 . Take the loopback measurement again. Subtract the complex number of Step-1 from the resultant term of this Step 2 to eliminate crosstalk, according to some aspects.

The above crosstalk removal procedure may be incorporated into each of the above tests because each test generally operates a different number of elements.

Distributed phased array systems (e.g., WiGig and 5G cellular systems) are currently used in laptops, tablets, smart phones, docking stations and other applications. Current distributed phased array systems used for WiGig and 5G communications are either super-heterodyne (dual conversion) or sliding-IF systems. In these systems, the MAC-PHY baseband sub-system receives or transmits an intermediate frequency (IF) signal, which necessitates the use of IF amplification stages, RF−IF mixers, high selectivity bandpass filters and other circuitry necessary for communicating IF signals between circuits, as well as up-conversion and down-conversion of the IF signals. The additional circuitry for IF signal processing results in a larger front-end module, higher cost for the distributed phased array system, and lower system performance. Additionally, in instances when a communication system provides MIMO support, additional coax cables (one for each MIMO rank) and signal multiplication may be needed. However, when multiplying signals, phase synchronization between the two MIMO streams is harder to achieve and guarantee, which can degrade MIMO performance.

FIG. 59 illustrates an exemplary RF front-end module (RFEM) of a distributed phased array system 5900 according to some aspects. The distributed phased array system 5900 may be incorporated in the digital baseband circuitry 310 , the transmit circuitry 315 , and the receive circuitry 320 of mmWave communication circuitry 300 shown in FIG. 3 A , although the distributed phased array system 5900 is not limited to such.

Referring to FIG. 59 , the RFEM 5902 is coupled to a baseband sub-system (BBS) 5904 via a single coax cable 5906 . The RFEM 5902 can include a phased antenna array 5908 , a RF receiver 5910 , a RF transmitter 5912 , a local oscillator (LO) generator 5944 , a triplexer 5948 , and a transmit (TX)/receive (RX) switch 5940 . The RF receiver 5910 can include a plurality of power amplifiers 5916 , a plurality of phase shifters 5918 , a combiner 5920 , an RF amplifier 5922 , an LO amplifier 5926 , and a mixer 5924 . The RF receiver 5910 can also include an IF amplifier 5942 .

The RF transmitter 5912 can include a mixer 5938 , LO amplifier 5940 , a RF amplifier 5936 , a splitter 5934 , a plurality of phase shifters 5932 , and a plurality of amplifiers 5930 . The RF transmitter 5912 can also include an IF amplifier 5946 .

In an example receive operation, the switch 5940 can activate receiver chain processing. The antenna array 5908 can be used for receiving a plurality of signals 5914 . The received signals 5914 can be amplified by amplifiers 5916 and their phase can be adjusted by corresponding phase shifters 5918 . Each of the phase shifters 5918 can receive a separate phase adjustment signal (not illustrated in FIG. 59 ) from a control circuitry (e.g., from a modem within the BBS 5904 ), where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 5908 . The phase adjusted signals at the output of the phase shifters 5918 can be summed by the combiner 5920 and then amplified by the RF amplifier 5922 . The LO generator 5944 can generate a LO signal using a clock frequency signal 5943 received from the BBS 5904 via the coax cable 5906 . The LO signal can be amplified by the amplifier 5926 and then multiplied with the output of amplifier 5922 using the mixer 5924 in order to generate an IF input signal 5945 . The IF input signal 5945 can be amplified by amplifier 5942 and then communicated to the BBS 5904 via the triplexer 5948 and the coax cable 5906 . In some aspects, the IF input signal 5945 can be centered around 10.56 GHz signal.

In an example transmit operation, the switch 5940 can activate transmitter chain processing. The RFEM 5902 can receive an IF signal 5947 from the BBS 5904 via the coax cable 5906 and the triplexer 5948 . The IF signal 5947 can be amplified by IF amplifier 5946 and then communicated to the mixer 5938 . The mixer 5938 can receive an up-conversion LO signal from the LO generator 5944 and the LO amplifier 5940 . The amplified LO signal is multiplied with the amplified received IF signal by the mixer 5938 to generate an RF signal. The RF signal is then amplified by amplifier 5936 and communicated to the splitter 5934 . The splitter 5934 generates multiple copies of the amplified signal and communicates signal copies to the plurality of phase shifters 5932 . The plurality of phase shifters 5932 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 5930 . The plurality of amplifiers 5930 generates a plurality of signals 5928 for transmission by the phased antenna array 5908 .

FIG. 60 illustrates a baseband sub-system (BBS) of a distributed phased array system according to some aspects. Referring to FIG. 60 , the BBS 5904 can include a triplexer 6002 , an IF receiver 6004 , an IF transmitter 6006 , a modem 6024 , a crystal oscillator 6030 , a synthesizer 6028 , and a divider 6026 . The synthesizer 6028 may include suitable circuitry, logic, interfaces and/or code and can use a signal from the crystal oscillator 6030 to generate a clock signal. The generated clock signal can be divided by the divider 6026 to generate an output clock signal for communication to the RFEM 5902 . In some aspects, the generated clock signal can have a frequency of 1.32 GHz.

The IF receiver 6304 can include an IF amplifier 6008 , mixers 6010 , filters 6012 , and analog-to-digital conversion (ADC) blocks 6014 . The IF transmitter 6006 can include digital-to-analog conversion (DAC) blocks 6022 , filters 6020 , mixers 6018 , and IF amplifier 6016 .

In an example receive operation, an IF signal (e.g., 5945 ) is received from the RFEM 5902 via the triplexer 6002 and is amplified by IF amplifier 6008 . The amplified IF signal can be down-converted to baseband signals by the mixers 6010 , then filtered by low-pass filters 6012 , and converted to a digital signal by the ADC blocks 6014 before being processed by the modem 6024 .

In an example transmit operation, a digital signal output by the modem 6024 can be converted to analog signals by the DAC blocks 6022 . The analog signals are then filtered by the low-pass filters 6020 and then up-converted to an IF signal by the mixers 6018 . The IF signal can be amplified by the IF amplifier 6016 , and then communicated to the RFEM 5902 via the triplexer 6302 and the single coax cable 5906 .

In some aspects, the phased antenna array 5908 within the distributed phased array system 5900 can include a plurality of antennas, which can be configured for MIMO operation. More specifically, the antennas within the phased antenna array 5908 can be configured for horizontal and vertical polarization transmission or reception. In this regard, at least two separate data streams can be processed by using horizontal and vertical polarization within the phased antenna array 5908 in connection with a MIMO operation scheme. An example distributed phased array system configured to communicate in a MIMO mode is illustrated in reference to FIG. 61 and FIG. 62 .

FIG. 61 illustrates an exemplary distributed phased array system with MIMO support and multiple coax cables coupled to a single RFEM according to some aspects. Referring to FIG. 61 , the distributed phased array system 6100 can include an RFEM 6102 and a BBS 6104 . The RFEM 6102 can be similar to the RFEM 5902 in FIG. 59 . In some aspects, the distributed phased array system 6100 can include two separate transceivers for processing two separate streams for MIMO operation. More specifically, a first transceiver can be used to process a first data stream for transmission or reception via the first phased antenna array 6108 (using a first type of antenna polarization), and a second transceiver can be used to process a second data stream for transmission or reception via the second phased antenna array 6112 (or using a different polarization input of the same antenna array).

The first transceiver can include a first part 6122 within the BBS 6104 and a second part 6106 within the RFEM 6102 . Similarly, the second transceiver can include a first part 6124 within the BBS 6104 and a second part 6110 within the RFEM 6102 . The first transceiver parts 6122 and 6124 within the BBS 6104 can include circuitry for digitizing data signals, filtering the digital signals, and up-converting the filtered signals for communication to the RFEM 6102 for further processing and subsequent transmission by the phased antenna arrays 6108 and 6112 .

The first transceiver parts 6122 and 6124 within the BBS 6104 can also include circuitry for processing intermediate frequency or radio frequency signals received via the phased antenna arrays 6108 and 6112 and processed by the RFEM, and for converting such signals into baseband and digital signals for processing. In some aspects, the first transceiver parts 6122 and 6124 can include one or more of the circuitry within the receiver block 6004 and the transmitter block 6006 in FIG. 60 . The BBS 6104 can further include an LO generator 6126 , which can be configured to generate a LO signal 6128 . The LO signal 6128 can be used by the first transceiver parts 6122 and 6124 for up-converting a baseband signal for communication to the RFEM 6102 or for down converting an IF or RF signal received from the RFEM 6102 into a baseband signal.

The second transceiver parts 6106 and 6110 within the RFEM 6102 can include circuitry for amplifying IF or RF signals received from the BBS 6104 , up-converting the amplified signals, replicating the signals, performing phase and/or amplitude adjustment of the signals prior to transmission via the phased antenna arrays 6108 or 6112 . The second transceiver parts 6106 and 6110 within the RFEM 6102 can also include circuitry for processing radio frequency signals received via the phased antenna arrays 6108 and 6112 , phase and/or amplitude adjusting the signals, down-converting the signals into IF signals and communicating the IF signals (or RF signals in instances when IF processing is not performed by the distributed phased array system 6100 ) to the BBS 6104 for processing. In some aspects, the second transceiver parts 6106 and 6110 can include one or more of the circuitry within the receiver block 5910 and the transmitter block 5912 in FIG. 59 . The RFEM 6102 can further include an LO generator 6114 , which can be configured to generate a LO signal 6116 . The LO signal 6116 can be used by the second transceiver parts 6106 and 6110 for down-converting a RF signal for communication to the BBS 6104 or for up-converting a signal received from the BBS 6104 into a RF signal for transmission.

In some aspects, the distributed phased array system 6100 can be configured for MIMO operation so that a first data stream is communicated via the coax cable 6130 and triplexers 6120 and 6118 for transmission or reception via the phased antenna array 6108 that uses a first type of polarization. A second data stream can be communicated via the coax cable 6132 and triplexers 6120 and 6118 for transmission or reception via the second phased antenna array 6112 that uses a second type of polarization. In this regard, the distributed phased array system 6100 uses to coax cables 6130 and 6132 two communicate two independent data streams (e.g., for transmission or reception using vertical and horizontal antenna polarization) between the BBS 6104 and the RFEM 6102 .

FIG. 62 illustrates an exemplary distributed phased array system with MIMO support where each RFEM transceiver is coupled to a separate coax cable according to some aspects. Referring to FIG. 62 , the distributed phased array system 6200 is similar to the distributed phased array system 6100 except that the second transceiver parts are each located in a separate RFEM. The separate transceiver part configuration in FIG. 62 can be used in instances when the RFEMs are available as separate modules (e.g., each RFEM is on a single chip).

The distributed phased array system 6200 can include an RFEM 6202 , RFEM 6204 , and a BBS 6226 . The RFEMs 6202 and 6204 can be similar to the RFEM 5902 in FIG. 59 . In some aspects, the distributed phased array system 6200 can include two separate transceivers for processing two separate streams for MIMO operation. More specifically, a first transceiver can be used to process a first data stream for transmission or reception via the first phased array 6208 (using a first type of antenna polarization), and a second transceiver can be used to process a second data stream for transmission or reception via the second phased array 6222 (using a second type of antenna polarization).

The first transceiver can include a first part 6230 within the BBS 6226 and a second part 6206 within the RFEM 6202 . Similarly, the second transceiver can include a first part 6232 within the BBS 6226 and a second part 6220 within the RFEM 6204 . The first transceiver parts 6230 and 6232 can have functionalities similar to the functionalities of the first transceiver parts 6122 and 6124 . Additionally the second transceiver parts 6206 and 6220 can have functionalities similar to the functionalities of the second transceiver parts 6106 and 6110 .

The BBS 6226 can include an LO generator 6234 , which can be configured to generate a LO signal 6236 . The LO signal 6236 can be used by the first transceiver parts 6230 and 6232 for up-converting a baseband signal for communication to the RFEMs 6202 and 6204 , or for down converting an IF or RF signal received from the RFEMs 6202 and 6204 into a baseband signal.

The RFEM 6202 can include an LO generator 6210 , which can be configured to generate a LO signal 6212 . The LO signal 6212 can be used by the second transceiver part 6206 for down-converting a RF signal for communication to the BBS 6226 or for up-converting a signal received from the BBS 6226 into a RF signal for transmission via the array 6208 .

The RFEM 6204 can include an LO generator 6216 , which can be configured to generate a LO signal 6218 . The LO signal 6218 can be used by the second transceiver part 6220 for down-converting a RF signal for communication to the BBS 6226 or for up-converting a signal received from the BBS 6226 into a RF signal for transmission via the array 6222 .

During an example MIMO operation, a first data stream may be communicated between the BBS 6226 and the RFEM 6202 via the triplexers 6228 and 6214 , and the coax cable 6238 . The first data stream can be transmitted via the phased antenna array 6208 , which can include vertically polarized antennas. A second data stream may be communicated between the BBS 6226 and the RFEM 6204 via the triplexer's 6228 and 6224 , and the coax cable 6240 . The second data stream can be transmitted via the phased antenna array 6222 , which can include horizontally polarized antennas. In some aspects, the phased antenna array 6208 can include horizontally polarized antennas, and the phased antenna array 6222 can include vertically polarized antennas.

As seen in FIG. 61 and FIG. 62 , in some distributed phased array communication systems configured for MIMO operation, a separate coax cable is used for each MIMO stream communicated between a BBS and a RFEM. Additionally and as seen in FIG. 62 , in order to improve the operation of the MIMO system, phase noise synchronization may be needed (the LO generator's 6210 and 6216 can be synchronized via the LO synchronization signal as seen in FIG. 62 ). Using multiple coax cables however can be challenging in mobile devices due to limited space and added cost of implementation.

In some aspects, a distributed phased array communication system can be configured for MIMO operation where two independent MIMO data streams can be communicated over a single coax cable coupling a BBS and a RFEM. More specifically, the two separate MIMO data streams can be configured so they are at non-overlapping frequencies. For example, a LO generator within a BBS can generate one or more LO signals, which can be used for up converting two separate data streams into different RF frequencies. The LO generator can also generate an additional LO signal, which can be used for conversion of the two separate data streams into a desired frequency at the RFEM. The two separate data streams can be communicated together (e.g., as RF signals with non-overlapping frequencies) with the additional LO signal via the single coax cable, where the additional LO signal can be used to up convert or down-convert one or more of the MIMO streams to a desired transmit or receive frequency. By using a single LO generator to generate the LO signal's used to process the two MIMO streams as well as the LO signal communicated together with the MIMO streams via the single coax cable, synchronization of the phase noise and phase noise correlation between the MIMO streams is achieved. The phase noise correlation can be when the signals are at the original LO frequencies or at a multiplied or divided value of the LO frequencies.

FIG. 63 illustrates an exemplary distributed phased array system with MIMO support and a single coax cable coupled to a single RFEM according to some aspects. Referring to FIG. 63 , the distributed phased array system 6300 can include an RFEM 6302 and a BBS 6304 . The RFEM 6302 and the BBS 6322 can be similar to the RFEM 5902 and BBS 5904 in FIGS. 59 - 60 .

In some aspects, the distributed phased array system 6300 can include two separate transceivers for processing two separate streams for MIMO operation. More specifically, a first transceiver can be used to process a first data stream for transmission or reception via the first phased antenna array 6306 (using a first type of antenna polarization), and a second transceiver can be used to process a second data stream for transmission or reception via the second phased array 6310 (using a second type of antenna polarization).

The first transceiver can include a first part 6326 within the BBS 6322 and a second part 6304 within the RFEM 6302 . Similarly, the second transceiver can include a first part 6328 within the BBS 6322 and a second part 6308 within the RFEM 6302 . The first transceiver parts 6326 and 6328 within the BBS 6322 can include circuitry for digitizing data signals, filtering the digital signals, and up converting the filtered signals for communication to the RFEM 6302 for further processing and subsequent transmission by the phased antenna arrays 6306 and 6310 . The first transceiver parts 6326 and 6328 within the BBS 6322 can also include circuitry for processing intermediate frequency or radio frequency signals received via the phased antenna arrays 6306 and 6310 and processed by the RFEM 6302 , and for converting such signals into baseband and digital signals for processing. In some aspects, the first transceiver parts 6326 and 6328 can include one or more of the circuitry within the receiver block 6004 and the transmitter block 6006 in FIG. 60 .

The BBS 6322 can further include an LO generator 6330 , which can be configured to generate LO signals 6332 , 6334 and 6320 . The LO signals 6332 and 6334 can be used by the first transceiver parts 6326 and 6328 , respectively, for up-converting a baseband signal (to IF or RF signal) for communication to the RFEM 6302 or for down converting an IF or RF signal received from the RFEM 6302 into a baseband signal.

The second transceiver parts 6304 and 6308 within the RFEM 6302 can include circuitry for amplifying IF or RF signals received from the BBS 6322 , up-converting the amplified signals, replicating the signals, performing phase and/or amplitude adjustment of the signals prior to transmission via the phased antenna arrays 6306 and 6310 .

The second transceiver parts 6304 and 6308 within the RFEM 6302 can also include circuitry for (1) processing radio frequency signals received via the phased antenna arrays 6306 and 6310 , (2) phase and/or amplitude adjusting the signals, and/or (3) down-converting the signals into IF signals and communicating the IF signals (or RF signals in instances when IF processing is not performed by the communication system 6300 ) to the BBS 6322 for processing. In some aspects, the second transceiver parts 6304 and 6308 can include one or more of the circuitry within the receiver block 5910 and the transmitter block 5912 in FIG. 59 .

The RFEM 6302 can further include an LO generator 6312 , which can be configured to generate LO signal used by the second transceiver parts 6304 and 6308 for up-converting or down-converting signals. In some aspects, the LO generator 6312 can include frequency manipulation circuitry such as frequency dividers and multipliers, can be configured to generate a LO signal using another LO signal generated by the LO generator 6330 and received from the BBS 6322 via the triplexers 6324 , 6314 , and the single coax cable 6336 .

In some aspects, the distributed phased array communication system 6300 can be configured for MIMO operation with two data streams be communicated simultaneously via the triplexers 6324 , 6314 , and the coax cable 6336 . More specifically, two independent data streams can be generated at baseband frequencies at the BBS 6322 . The LO generator 6330 can include a single frequency source within the communication system 6300 , and is configured to generate LO frequencies for two distinct up conversion schemes performed by the first transceiver parts 6326 and 6328 respectively. For each of the two schemes, one LO frequency is used for up conversion of the baseband stream to a desired IF frequency within the BBS 6322 .

For example, the LO generator 6330 can generate a first LO signal 6332 , which can be used by first transceiver part 6326 to up convert a first MIMO stream 6316 to a desired frequency f 1 (e.g., a transmission frequency). The LO generator 6330 can generate a second LO signal 6334 , which can be used by the first transceiver report 6328 to up convert a second MIMO stream 6318 to a second frequency f 2 . The LO generator 6330 additionally generates a third LO signal 6320 , which can be used (either directly or by simple manipulation) to up convert one or both of the MIMO data streams to a desired RF frequency. In the example illustrated in FIG. 63 , the first MIMO stream 6316 is already unconverted, and is at the desired frequency f 1 within the BBS 6322 . In this regard, the third LO signal 6320 can be communicated to the RFEM 6302 via a single coax cable 6336 , and used by the second transceiver part 6308 to up convert the second MIMO stream 6318 to the desired frequency f 1 prior to transmission by the phased antenna array 6310 .

In some aspects, the two MIMO streams 6316 and 6318 can be generated at IF or RF frequencies, and can be communicated together with the third LO signal 6320 to the RFEM 6302 via the single coax cable 6336 . In this regard, RF-over-cable (RFoC) communication techniques can be used to communicate the two MIMO streams together with the LO signal via a single coax cable between the BBS and the RFEM within the communication system 6300 . The two up-conversion schemes for generating the MIMO streams 6316 and 6318 can be designed such that the four signal frequencies associated with the two MIMO streams 6316 , 6318 , and the frequencies of the LO signals 6332 and 6334 will not overlap. In some aspects, one of the two up-conversion schemes (e.g., generating the MIMO stream 6316 ) can be a direct conversion scheme such that no LO signal is needed to generate the corresponding MIMO stream (e.g., 6316 ).

As seen in FIG. 63 , the first MIMO data stream 6316 is communicated (at the desired frequency f 1 ) via the coax cable 6336 and triplexers 6324 and 6314 for transmission or reception via the phased antenna array 6306 that uses a first type of polarization. A second MIMO data stream 6318 is communicated (at frequency f 2 ) via the coax cable 6336 and triplexers 6324 and 6314 for transmission or reception via the second phased antenna array 6310 that uses a second type of polarization.

Additionally, the LO generator 6312 receives the third LO signal 6320 together with the two MIMO streams via the coax cable 6336 , and communicates the LO signal 6320 (or generates another LO signal by frequency manipulation of LO signal 6320 ) to the second transceiver part 6308 . Since the second MIMO stream 6318 is at frequency f 2 (which is not the desired frequency f 1 ), the second transceiver part 6308 can use the LO signal received from the LO generator 6312 to up-convert or down-convert the second MIMO stream 6318 so that it is also at the desired frequency f 1 prior to transmission by the phased antenna array 6310 .

In this regard, the distributed phased array system 6300 uses coax cables 6130 and 6132 to communicate two independent data streams and at least one LO signal (e.g., for transmission or reception using vertical and horizontal antenna polarization) between the BBS 6322 and the RFEM 6302 .

In some aspects, the first MIMO stream 6316 and the second MIMO stream 6318 can be generated at frequencies that are not overlapping and are not a desired frequency. In this case, the LO generator 6330 can generate two separate LO signals, which can be communicated together with the MIMO streams 6316 and 6318 via the single coax cable 6336 to the RFEM 6302 . The two separate LO signals can be used within the RFEM 6302 for converting the two MIMO streams 6316 and 6318 into a desired transmit frequency.

In some aspects, the first MIMO stream 6316 and the second MIMO stream 6318 can be generated at frequencies that are not overlapping and are not a desired frequency. In this case, the LO generator 6330 can generate one separate LO signal, which can be communicated together with the MIMO streams 6316 and 6318 via the single coax cable 6336 to the RFEM 6302 . The one separate LO signal can be used within the RFEM 6302 for converting one of the two MIMO streams into a desired transmit frequency. The LO generator 6312 can use the one separate LO signal to generate another LO signal (e.g., by frequency manipulation), which can be used to convert the remaining MIMO stream into the desired transmit frequency. In this case, the two MIMO streams are communicated with a single LO signal between the BBS 6322 and RFEM 6302 via the single coax cable 6336 .

In an example and as seen in FIG. 63 , one of the MIMO streams (e.g., 6316 ) is generated at the desired frequency f 1 . The second MIMO stream 6318 is generated at a different (not overlapping) frequency f 2 , which can be higher or lower than f 1 . The two MIMO streams 6316 and 6318 can be communicated via the single coax cable 6336 together with the third LO signal 6320 . The third LO signal 6320 can be at a frequency that is a difference between the frequencies f 1 and f 2 associated with MIMO streams 6316 and 6318 respectively.

Since the various frequency signals are generated from a single frequency synthesizer source within the system 6300 (e.g., LO generator 6330 ), and since only simple frequency manipulation (e.g., division or multiplication) is utilized to manipulate LO signals within the RFEM 6302 , phase relationship between the resulting RF streams (e.g., 6316 and 6318 ) can be maintained regardless of the number of RFEMs used or the RFEM location. Put another way, by using the same two up-conversion schemes to generate IF or RF MIMO streams and transmit them over a single coax with one or more LO signals, a phase relationship between the MIMO streams can be maintained even if the streams are received for processing by remote RFEMs (a multiple RFEM processing scenario is illustrated in FIG. 65 ).

Even though FIG. 63 illustrates generation of the MIMO streams at the BBS 6322 and then communication for processing and transmission by the RFEM 6302 , the disclose techniques can also be used for MIMO streams that are received by the phased antenna arrays 6306 and 6310 and then communicated for processing to the BBS 6322 .

FIG. 64 illustrates spectral content of various signals communicated on the single coax cable of FIG. 63 according to some aspects. Referring to FIG. 64 , signal diagram 6402 illustrates the frequency of the spectral content communicated over the single coax cable 6336 . More specifically, signal diagram 6402 illustrates the frequencies of a first MIMO stream 6402 , a second MIMO stream 6406 , and a LO signal 6408 . In some aspects, the first MIMO stream 6404 can be at a desired frequency f 1 , and the second MIMO stream 6406 can be at a frequency f 2 , which is a fraction of frequency f 1 (e.g., f 2 is M/K times frequency f 1 , where M and K are integers higher than 1). The frequency of the LO signal 6408 can be lower than the frequency of the second MIMO stream 6406 , and can be determined based on the same fraction associated with the second MIMO stream 6406 . For example, the frequency of the LO signal 6408 can be designated as f LO and can be determined based on the equation

f L ⁢ O = f 1 × ( 1 - M K ) .

In this regard, the second MIMO stream 6406 with frequency f 2 can be converted to the desired frequency f 1 by mixing it with the LO signal at frequency f LO .

Referring to FIG. 64 , signal diagram 6410 illustrates the frequencies of a first MIMO stream 6412 , a second MIMO stream 6416 , and a LO signal 6414 . In some aspects, the first MIMO stream 6412 can be at a desired frequency f 1 , and the LO signal 6414 can be at a frequency f 2 , which is a fraction of frequency f 1 (e.g., f 2 is M/K times frequency f 1 , where M and K are integers higher than 1). The frequency of the second MIMO stream 6416 can be lower than the frequency of the LO signal 6414 , and can be determined based on the same fraction associated with the LO signal 6414 . For example, the frequency of the LO signal 6414 can be

f L ⁢ O = f 1 × M K .

The frequency of the second MIMO stream 6416 can be designated as f 2 and can be determined based on the equation

Referring to FIG. 64 , signal diagram 6418 illustrates the frequency of the spectral content communicated over the single coax cable 6336 . More specifically, signal diagram 6418 illustrates the frequencies of a first MIMO stream 6420 , a second MIMO stream 6422 , and a LO signal 6424 . In some aspects, the first MIMO stream 6420 can be at a desired frequency of 28 GHz, and the second MIMO stream 6422 can be at a frequency 18.66 GHz, which is a fraction of 28 GHz (e.g., ⅔ of 28 GHz). The frequency of the LO signal 6424 can be lower than the frequency of the second MIMO stream 6422 , and can be determined based on the same fraction associated with the second MIMO stream 6406 (e.g., f LO can be 9.33 GHz, which is ⅓ of 28 GHz).

FIG. 65 illustrates an exemplary distributed phased array system with a single BBS and multiple RFEMs with MIMO support and a single coax cable between the BBS and each of the RFEMs according to some aspects. Referring to FIG. 65 , the distributed phased array system 6500 can include RFEMs 6502 , 6504 , and a BBS 6506 . The RFEMs 6502 and 6504 and the BBS 6506 can be similar to the RFEM 6302 and BBS 6322 in FIG. 63 . In some aspects, the distributed phased array system 6500 can include four separate transceivers for processing four separate streams for MIMO operation. More specifically, a first transceiver can be used to process a first data stream for transmission or reception via the first phased array 6548 (using a first type of antenna polarization), and a second transceiver can be used to process a second data stream for transmission or reception via the second phased array 6550 (using a second type of antenna polarization). A third transceiver can be used to process a third data stream for transmission or reception via the third phased array 6560 (using the first type of antenna polarization), and a fourth transceiver can be used to process a fourth data stream for transmission or reception via the fourth phased array 6562 (using the second type of antenna polarization).

The first transceiver can include a first part 6508 within the BBS 6506 and a second part 6540 within the RFEM 6502 . The second transceiver can include a first part 6510 within the BBS 6506 and a second part 6542 within the RFEM 6502 . The third transceiver can include a first part 6516 within the BBS 6506 and a second part 6552 within the RFEM 6504 . The fourth transceiver can include a first part 6518 within the BBS 6506 and a second part 6554 within the RFEM 6504 .

The first transceiver parts 6508 , 6510 , 6516 , and 6518 within the BBS 6506 may include circuitry for digitizing data signals, filtering the digital signals, and up converting the filtered signals for communication to the RFEMs 6502 and 6504 for further processing and subsequent transmission by the phased antenna arrays 6548 , 6550 , 6560 , and 6562 . The first transceiver parts 6508 , 6510 , 6516 , and 6518 within the BBS 6506 can also include circuitry for processing intermediate frequency (IF) or RF signals received via the phased antenna arrays 6548 , 6550 , 6560 , and 6562 , and processed by the RFEMs 6502 , 6504 , and for converting such signals into baseband and digital signals for processing.

The BBS 6506 can further include an LO generator 6514 , which can be configured to generate LO signals 6522 , 6524 , and 6526 . The LO signals 6522 and 6524 can be used by the first transceiver parts 6508 , 6510 , 6516 , and 6518 for up-converting a baseband signal (to IF or RF signal) to generate MIMO streams 6528 , 6530 , 6532 and 6534 for communication to the RFEMs 6502 and 6504 , or for down converting IF or RF signals received from the RFEMs 6502 and 6504 into baseband signals.

The second transceiver parts 6540 and 6542 (within the RFEM 6502 ) and 6552 and 6554 (within the RFEM 6504 ) can include circuitry for amplifying IF or RF signals received from the BBS 6506 , up-converting the amplified signals, replicating the signals, performing phase and/or amplitude adjustment of the signals prior to transmission via the phased antenna arrays 6548 , 6550 , 6560 , and 6562 . The second transceiver parts 6540 and 6542 (within the RFEM 6502 ) and 6552 and 6554 (within the RFEM 6504 ) can also include circuitry for processing radio frequency signals received via the phased antenna arrays 6548 , 6550 , 6560 , and 6562 , phase and/or amplitude adjusting the signals, down-converting the signals into IF signals and communicating the IF signals (or RF signals in instances when IF processing is not performed by the distributed phased array system 6500 ) to the BBS 6506 for processing. In some aspects, the second transceiver parts 6540 and 6542 (within the RFEM 6502 ) and 6552 and 6554 (within the RFEM 6504 ) can include one or more of the circuitry within the receiver block 5910 and the transmitter block 5912 in FIG. 59 .

The RFEM 6502 can include an LO generator 6544 , which can be configured to generate LO signals used by the second transceiver parts 6540 and 6542 for up-converting or down-converting signals. In some aspects, the LO generator 6544 can include frequency manipulation circuitry such as frequency dividers, adders and multipliers, and can be configured to generate a LO signal using another LO signal generated by the LO generator 6514 and received from the BBS 6506 via the triplexers 6512 , 6546 , and the single coax cable 6536 .

The RFEM 6504 can include an LO generator 6556 , which can be configured to generate LO signals used by the second transceiver parts 6552 and 6554 for up-converting or down-converting signals. In some aspects, the LO generator 6556 can include frequency manipulation circuitry such as frequency dividers, adders and multipliers, and can be configured to generate a LO signal using another LO signal generated by the LO generator 6514 and received from the BBS 6506 via the triplexers 6520 , 6558 , and the single coax cable 6538 .

In some aspects, the distributed phased array system 6500 can be configured for MIMO operation with four data streams communicated simultaneously via the triplexers 6512 , 6520 , 6546 , 6558 , and the coax cables 6536 and 6538 . More specifically, four independent data streams can be generated at baseband frequencies at the BBS 6506 . The LO generator 6514 can include a single frequency source within the distributed phased array system 6500 , and is configured to generate LO frequencies (e.g., 6522 and 6524 ) for two distinct up-conversion schemes performed by the first transceiver parts 6508 , 6510 , 6516 , and 6518 . For each of the two schemes, one LO frequency is used for up conversion of the baseband stream to a desired IF (or RF) frequency within the BBS 6506 .

As seen in FIG. 65 , LO signals 6522 and 6524 can be used to generate MIMO streams 6528 and 6530 (for processing by RFEM 6502 ), as well as MIMO streams 6532 and 6534 (for processing by RFEM 6504 ). MIMO streams 6528 and 6532 can be generated at a desired frequency f 1 (e.g., a desire to transmit frequency). MIMO streams 6530 and 6534 can be generated at a different frequency f 2 , which can be higher or lower than f 1 .

The signal frequencies of the LO signals 6522 , 6524 , and 6526 , as well as the frequencies f 1 and f 2 of the four generated MIMO streams, can all be non-overlapping frequencies. In this regard, any combination of the LO signals and the MIMO streams can be communicated via a single communication medium (e.g., a single coax cable) without mutual signal interference. The third LO signal 6526 can be communicated together with MIMO streams 6528 and 6530 along the coax cable 6536 for processing by the RFEM 6502 . More specifically, the first MIMO stream 6528 is already at the desired frequency f 1 so no further up-conversion may be required prior to transmission by the phased antenna array 6548 . The LO generator 6544 can receive the third LO signal 6526 and can forward that signal to the second transceiver part 6542 for up-conversion or down-conversion of the second MIMO stream 6530 to the desired frequency f 1 . In some aspects, the LO signal 6526 can be used as received from the BBS 6506 , or the LO generator 6544 may perform frequency manipulation to generate a new LO signal, which can be used for the conversion of the second MIMO stream 6530 to the desired frequency f 1 prior to transmission by the phased antenna array 6550 .

Similarly, the third LO signal 6526 can be communicated together with MIMO streams 6532 and 6534 along the coax cable 6538 for processing by the RFEM 6504 . More specifically, the third MIMO stream 6532 is already at the desired frequency f 1 so no further up-conversion may be required prior to transmission by the phased antenna array 6560 . The LO generator 6556 can receive the third LO signal 6526 and can forward that signal to the second transceiver part 6554 for up-conversion or down-conversion of the fourth MIMO stream 6534 to the desired frequency f 1 . In some aspects, the LO signal 6526 can be used as received from the BBS 6506 , or the LO generator 6556 may perform frequency manipulation to generate a new LO signal, which can be used for the conversion of the fourth MIMO stream 6534 to the desired frequency f 1 prior to transmission by the phased antenna array 6562 .

Even though FIG. 63 and FIG. 65 disclose the use of a single coax cable to connect the BBS with the RFEM for transmission and reception of multiple data streams, the disclosure is not limited in this regard and other types of connections can be used as well. For example, another type of a millimeter wave connection or cable can be used instead of the single coax cable. Other types of connections that can be used include semi-rigid cables, flexible cables of a flexible substrate, printed RF transmission lines on PCB, rigid flex board, and so forth.

Distributed phased array systems (e.g., WiGig and 5G cellular systems) are currently used in laptops, tablets, smart phones, docking stations and other applications. Current distributed phased array systems used for WiGig and 5G communications are either super-heterodyne (dual conversion) or sliding-IF systems. In these systems, the MAC-PHY baseband sub-system receives or transmits an intermediate frequency (IF) signal, which necessitates the use of IF amplification stages, RF-IF mixers, high selectivity bandpass filters and other circuitry necessary for communicating IF signals between circuits, as well as up-conversion and down-conversion of the IF signals. The additional circuitry four IF signal processing results in a larger front-end module, higher cost for the distributed phased array system, and lower system performance.

FIG. 66 illustrates an exemplary RF front-end module (RFEM) of a distributed phased array system 6600 according to some aspects. The distributed phased array system 6600 may be incorporated in the digital baseband circuitry 310 , the transmit circuitry 315 , and the receive circuitry 320 of mmWave communication circuitry 300 shown in FIG. 3 A , although the distributed phased array system 6600 is not limited to such.

Referring to FIG. 66 , the RFEM 6602 is coupled to a baseband sub-system (BBS) 6604 via a single coax cable 6606 . The RFEM 6602 can include a phased antenna array 6608 , a RF receiver 6610 , a RF transmitter 6612 , a local oscillator (LO) generator 6644 , a triplexer 6648 , and a transmit (TX)/receive (RX) switch 6640 . The RF receiver 6610 can include a plurality of power amplifiers 6616 , a plurality of phase shifters 6618 , and adder 6620 , an RF amplifier 6622 , an LO amplifier 6626 , and a multiplier 6624 . The RF receiver 6610 can also include an IF amplifier 6642 . In some aspects, the IF amplifier 6642 can be part of the receiver 6610 or it can be implemented outside of the receiver 6610 .

The RF transmitter 6612 can include a multiplier 6638 , LO amplifier 6640 , a RF amplifier 6636 , an adder 6634 , a plurality of phase shifters 6632 , and a plurality of amplifiers 6630 . The RF transmitter 6612 can also include an IF amplifier 6646 . In some aspects, the IF amplifier 6646 can be part of the transmitter 6612 or it can be implemented outside of the transmitter 6612 .

In an example receive operation, the switch 6640 can activate receiver chain processing. The antenna array 6608 can be used for receiving a plurality of signals 6614 . The received signals 6614 can be amplified by amplifiers 6616 and their phase can be adjusted by corresponding phase shifters 6618 . Each of the phase shifters 6618 can receive a separate phase adjustment signal (not illustrated in FIG. 66 ) from a control circuitry (e.g., from a modem within the BBS 6604 ), where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 6608 . The phase adjusted signals at the output of the phase shifters 6618 can be summed by the adder 6620 and then amplified by the RF amplifier 6622 . The LO generator 6644 can generate a LO signal using a clock frequency signal 6643 received from the BBS 6604 via the coax cable 6606 . The LO signal can be amplified by the amplifier 6626 and then multiplied with the output of amplifier 6622 using the multiplier 6624 in order to generate an IF input signal 6645 . The IF input signal 6645 can be amplified by amplifier 6642 and then communicated to the BBS 6604 via the triplexer 6648 and the coax cable 6606 . In some aspects, the IF input signal 6645 can be 10.56 GHz signal.

In an example transmit operation, the switch 6640 can activate transmitter chain processing. The RFEM 6602 can receive an IF signal 6647 from the BBS 6604 via the coax cable 6606 and the triplexer 6648 . The IF signal 6647 can be amplified by IF amplifier 6646 and then communicated to multiplier 6638 . The multiplier 6638 can receive an up-conversion LO signal from the LO generator 6644 and the LO amplifier 6640 . The amplified LO signal is multiplied with the amplified received IF signal by the multiplier 6638 to generate an RF signal. The RF signal is then amplified by amplifier 6636 and communicated to adder 6634 . The adder 6634 generates multiple copies of the amplified signal and communicates signal copies to the plurality of phase shifters 6632 . The plurality of phase shifters 6632 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 6630 . The plurality of amplifiers 6630 generates a plurality of signals 6628 for transmission by the phased antenna array 6608 .

FIG. 67 illustrates a baseband sub-system (BBS) of a distributed phased array system according to some aspects. Referring to FIG. 67 , the BBS 6604 can include a triplexer 6702 , an IF receiver 6704 , an IF transmitter 6706 , a modem 6724 , a crystal oscillator 6730 , a synthesizer 6728 , and a divider 6726 . The synthesizer 6728 may include suitable circuitry, logic, interfaces and/or code and can use a signal from the crystal oscillator 6730 to generate a clock signal. The generated clock signal can be divided by the divider 6726 to generate an output clock signal for communication to the RFEM 6602 . In some aspects, the generated clock signal can have a frequency of 1.32 GHz.

The IF receiver 7004 can include an IF amplifier 6708 , mixers 6710 , filters 6712 , and analog-to-digital conversion (ADC) blocks 6714 . The IF transmitter 6706 can include digital-to-analog conversion (DAC) blocks 6722 , filters 6720 , mixers 6718 , and IF amplifier 6716 .

In an example receive operation, an IF signal (e.g., 6645 ) is received from the RFEM 6602 via the triplexer 6702 and is amplified by IF amplifier 6708 . The amplified IF signal can be down-converted to baseband signals by the mixers 6710 , then filtered by low-pass filters 6712 , and converted to a digital signal by the ADC blocks 6714 before being processed by the modem 6724 .

In an example transmit operation, a digital signal output by the modem 6724 can be converted to analog signals by the DAC blocks 6722 . The analog signals are then filtered by the low-pass filters 6720 and then up-converted to an IF signal by the mixers 6718 . The IF signal can be amplified by the IF amplifier 6716 , and then communicated to the RFEM 6602 via the triplexer 6702 and the single coax cable 6606 .

FIG. 68 illustrates a frequency diagram of signals communicated between a RFEM and a BBS according to some aspects. Referring to FIG. 68 , the frequency diagram 6800 illustrates various signals, which can be communicated between the RFEM 6602 and the BBS 6604 via the single coax cable 6606 . For example, the BBS 6604 can communicate a DC power signal 6802 , a control signal 6804 , and the clock signal 6806 . Additionally, data signals 6810 can be communicated between the BBS 6604 and the RFEM 6602 . For example, an IF data signal 6645 can be communicated from the RFEM 6602 to the BBS 6604 , and an IF data signal 6647 can be communicated from the BBS 6604 to the RFEM 6602 . The clock signal 6806 can be the same as the LO generation clock signal 6643 received by the RFEM 6602 from the BBS 6604 . In some aspects, the clock signal 6806 can be a 1.32 GHz signal. In some aspects, the control signal 6804 can be communicated from the BBS 6604 to the RFEM 6602 and can indicate phase adjustment values for use by the phase shifters 6618 and the phase shifters 6632 . The control signal 6804 can indicate to the RFEM 6602 other control functions, such as power up, power down, increase or decrease transmit power and so forth.

As seen in FIG. 68 , the signal spectrum of signals communicated between the RFEM 6602 and the BBS 6604 can include some undesirable signals, such as the clock harmonics 6808 as well as harmonics of the control signal 6804 . Additionally, by including IF processing circuitry within the RFEM 6602 and the BBS 6604 other drawbacks within the distributed phased array system 6600 are present, as described herein below.

Signal Frequency Stability Due to Voltage Jumps of RFEM Supply Voltage

The RFEM 6602 includes LO generators (e.g., 6644 ), which can include frequency synthesizer, frequency multipliers and dividers. The frequency signals generated by these circuits are used for driving the up-conversion mixer 6638 or the down-conversion mixer 6624 . However, the LO generator 6644 can be sensitive to supply voltage stability. The RFEM 6602 supply voltage (e.g., 6802 ) is fed through the coax cable 6606 as well as associated connectors and RF chokes (not illustrated in FIG. 66 ). Consequently, the supply voltage is affected by the resistance of these components and the current flowing through the coax cable 6606 . In this regard, any instantaneous change in the current through the coax 6606 (e.g., RX to TX transitions, changing number of phased array active lanes, digital activity/processing in the RFEM, etc.) would generate an instantaneous change of LO generation circuitry, which would cause an instantaneous frequency change.

RFEM High Power Consumption

The distributed phased array system 6600 uses LO generator 6644 (synthesizer, frequency multiplier, frequency drivers, etc.), up and down conversion mixers (e.g., 6624 , 6638 ), IF amplification stages (e.g., 6642 , 6646 ), and complex triplexers (e.g., 6648 ). In an aspect of the disclosure, only RF signals can be communicated between the RFEM 6602 and the BBS 6604 . In this regard, the IF-related circuitry within the RFEM 6602 can be removed, lowering the power consumption and heat generation of the RFEM 6602 .

RFEM Cost

In distributed phased array systems (e.g., 6600 ), the RFEM cost can be significant (e.g., up to 50% of the entire system cost in some instances). While BBS cost reduction can be achieved by process migration (since much of the BBS-chip processing is digital), such cost reduction can be challenging with the RFEM as mostly analog processing is included in the RFEM. By performing only RF processing and communicating RF signals between the RFEM 6602 and the BBS 6604 via the single coax cable 6606 , RFEM implementation cost reduction can be achieved.

RFEM Form Factor (FF)

Since the RFEM 6602 includes an antenna array ( 108 ), it is located at the boundary of the communication device to allow good radiations of the phased array antennas. By using only RF processing and removing the IF conversion stage and processing from the RFEM 6602 , the RFEM form factor is reduced, which is beneficial for RFEM device placement and implementation.

Co-Running with Other Standards (WiFi, Bluetooth, LTE, etc.)

The IF frequency signals (e.g., 6645 and 6647 ) communicated over the coax cable 6606 carries the wideband (e.g., WiGig or 5G) signal and is vulnerable to harmonics of other communication systems in the same platform/device. For example, the IF frequency signals ( 6645 ) communicated from the RFEM to the BBS or the IF signals ( 6647 ) received by the RFEM from the BBS can be 10.56 GHz signals. However, the 10.6 GHz IF signals can be in the same range as one or more harmonics of a Wi-Fi band.

FCC/ETSI Regulation Violation of CLK Signal Over the Coax

In a distributed system the signals over the COAX cable (CLK, IF data) leak from the COAX (cable and connectors) and from the PCB interconnections. This leakage would cause FCC/ETSI regulation violation. In order to lower the leakage power we need to use high quality RF shielding, highly isolated COAX and in some cases even lower the level of the signals over the CAOX (this might affect the system performance).

In some aspects, the RFEM 6602 can be configured to process and communicate RF signals via the coax cable 6606 to the BBS 6604 for processing and down-conversion. Similarly, the BBS 6604 can up convert data signals to RF signals and communicate RF signals to the RFEM 6602 via the coax cable 6606 . In this regard, by removing IF processing within the RFEM 6602 , the above listed drawbacks associated with IF processing within the distributed phased array communication system can be removed. 108

FIG. 69 illustrates a RFEM coupled to a BBS via a single coax cable for communicating RF signals according to some aspects. Referring to FIG. 69 , the distributed phased array communication system 6900 can include RFEM 6902 coupled to a baseband sub-system (BBS) 6904 via a single coax cable 6906 . The RFEM 6902 can include a phased antenna array 6908 , a RF receiver 6910 , a RF transmitter 6912 , a duplexer 6936 , and a transmit (TX)/receive (RX) switch 6934 . The RF receiver 6910 can include a plurality of power amplifiers 6916 , a plurality of phase shifters 6918 , an adder 6920 , and RF amplifier 6922 . The RF transmitter 6912 can include a RF amplifier 6932 , an adder 6930 , a plurality of phase shifters 6928 , and a plurality of amplifiers 6926 .

In an example receive operation, the switch 6934 can activate receiver chain processing. The phased antenna array 6908 can be used for receiving a plurality of signals 6914 . The received signals 6914 can be amplified by amplifiers 6916 and their phase can be adjusted by corresponding phase shifters 6918 . Each of the phase shifters 6918 can receive a separate phase adjustment signal (not illustrated in FIG. 69 ) from a control circuitry (e.g., from a modem within the BBS 6904 ), where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 6908 . The phase adjusted signals at the output of the phase shifters 6918 can be summed by the adder 6920 and then amplified by the RF amplifier 6922 to generate an RF input signal 6923 . The RF input signal 6923 can be communicated to the BBS 6904 via the duplexer 6936 and the coax cable 6906 . In some aspects, the RF input signal 6923 can be a 60 GHz signal or another signal in a millimeter wave band including a 5G communication band.

In an example transmit operation, the switch 6934 can activate transmitter chain processing. The RFEM 6902 can receive a RF output signal 6931 from the BBS 6904 via the coax cable 6906 and the duplexer 6936 . The RF signal 6931 can be amplified by RF amplifier 6932 and then communicated to adder 6930 . The adder 6930 generates multiple copies of the amplified RF signal and communicates the signal copies to the plurality of phase shifters 6928 . The plurality of phase shifters 6928 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 6926 . The plurality of amplifiers 6926 generates a plurality of signals 6924 for transmission by the phased antenna array 6908 .

FIG. 70 illustrates a more detailed diagram of the BBS 6904 of FIG. 69 according to some aspects. Referring to FIG. 69 , the BBS 6904 can include a duplexer 7002 , a RF receiver 7004 , a RF transmitter 7006 , a modem 7024 , a crystal oscillator 7030 , a synthesizer 7028 , and a divider 7026 . The synthesizer 7028 may include suitable circuitry, logic, interfaces and/or code and can use a signal from the crystal oscillator 7030 to generate a clock signal, such as signal 7032 . The generated clock signal 7032 can be used by the RF receiver 7004 to down-convert a received signal using the mixers 7010 . The generated clock signal 7032 can also be used by the RF transmitter 7006 to up convert a signal using the mixers 7018 . The clock signal 7032 can also be divided by the divider 7026 to generate a second clock signal 7034 . The generated second clock signal 7034 can be used by the RF receiver 7004 to down-convert a received signal using the mixers 7010 . The generated second clock signal 7034 can also be used by the RF transmitter 7006 to up convert a signal using the mixers 7018 . As seen in FIG. 70 , two separate clock signals 7034 and 7032 can be generated by the synthesizer 7028 and divider 7026 . One or both of the two clock signals 7034 and 7032 can be used for down-conversion of RF signals into baseband using one or more intermediate IF stages or, in some instances, conversion from RF to baseband without an intermediate IF stage conversion. Similarly, one or both of the clock signal's 7034 and 7032 can be used for up conversion of a baseband signal into an RF signal using one or more intermediate IF stages or, in some instances, conversion from baseband to RF without an intermediate IF stage conversion.

The RF receiver 7004 can include an RF amplifier 7008 , mixers 7010 , filters 7012 , and analog-to-digital conversion (ADC) blocks 7014 . The RF transmitter 7006 can include digital-to-analog conversion (DAC) blocks 7022 , filters 7020 , mixers 7018 , and RF amplifier 7016 .

In an example receive operation, a RF signal (e.g., 6923 ) is received from the RFEM 6902 via the single coax 6906 and the duplexer 7002 , and is amplified by RF amplifier 7008 . The amplified RF signal can be down-converted to baseband signals by the mixers 7010 , then filtered by low-pass filters 7012 , and converted to a digital signal by the ADC blocks 7014 before being processed by the modem 7024 .

In an example transmit operation, a digital signal output by the modem 7024 can be converted to analog signals by the DAC blocks 7022 . The analog signals are then filtered by the low-pass filters 7020 and then up-converted to a RF signal by the mixers 7018 . The RF signal can be amplified by the RF amplifier 7016 , and then communicated to the RFEM 6902 via the duplexer 7002 and the single coax cable 6906 .

In some aspects, the coax cable 6906 can be used for communication of DC power signals (e.g., from the BBS 6904 to the RFEM 6902 ), control signals and RF data signals that received or transmitted by the phased antenna array 6908 . The control signal can include phase adjustment signals, power up signals, power down signals, and other control signals communicated from the BBS 6904 to the RFEM 6902 . In some aspects, control signals can include phase adjustment the request signals or other data request signals communicated from the RFEM 6902 to the BBS 6904 . In this regard, a direct conversion scheme can be used in connection with a distributed phased array system, where the RFEM and the BBS are coupled via a single coax cable.

In some aspects, the control signal can be used for controlling the RFEM operation (e.g., controlling output power levels, AGC, ON/OFF, etc.). Additionally, the control link between the RFEM and the BBS can be bi-directional, and can be used for BBS-to-RFEM commands and for RFEM-to-BBS telemetry transfer (e.g., PA power detectors reading, ACK after a control command reception, temperature detector reading, etc.).

In some aspects, different types of coax cables ( 6906 ) can be used in connection with a distributed phased array communication system that communicate RF over the coax. For example, high quality coaxial cable, a semi-rigid cable, or a flexible semi-rigid cable can be used as cable 6906 , which will allow for high frequency communication of RF signals with reasonable loss.

In another example, a lower cost coax cable can be used as coax 6906 , which can result in matching (S11) and high loss (S21) issues with high RF frequency communications. These drawbacks can be improved via system design changes, such as adaptive cable matching improvements, robust RX and TX line-ups, and RX and TX non-linearity distortion cancellation.

Adaptive Cable Matching Improvement

RF signal communication over a cable can be associated with high losses and matching issues. Due to the high frequency of associated with RF cable communication, the variation of the cable matching can be high and unexpected, which affects the power loss between the cable and the load. In an example and in order to overcome these drawbacks, an adaptive impedance matching circuitry (e.g., 6938 and 7036 ) can be used in the RFEM 6902 and the BBS 6904 , as seen in FIGS. 69 - 5 .

Robust RX and TX Line-Ups

In some aspects, higher signal loss associated with the coax cable can be addressed by adding additional gain amplification/adjustment stages (not illustrated in the figures) (e.g., before the cable 6906 and the adaptive matching 6938 within the RFEM 6902 ), which can ensure that a potential high signal loss of a coax cable would not degrade the SNR of the communicated RF signal.

RX and TX Non-Linearity Distortion Cancellation

In some aspects, additional gain stages in the RX and TX line-up may lead to non-linearity distortion. However, these signal distortions can be compensated via digital mechanisms, such as pre-distortion adjustment circuitry in the TX path or post-distortion adjustment circuitry in the RX path (not illustrated in the figures).

FIG. 71 illustrates an exemplary massive antenna array (MAA) using multiple RFEMs coupled to a single BBS according to some aspects. Referring to FIG. 71 , the distributed phased array communication system 7100 can be used to implement a massive antenna array. More specifically, multiple RFEMs ( 7102 , 7138 , . . . , 7140 ) can be used with a single BBS ( 7104 ), with each RFEM including a phased antenna array. The RFEMs 7102 , 7138 , . . . , 7140 can be coupled to the BBS 7104 via corresponding single coax cables 7106 , 7144 , . . . , 7146 .

In some aspects, a single LO source (e.g., a millimeter wave synthesizer) can be located within the BBS 7104 and used for TX and RX signals up-conversion and down-conversion, respectively. In this way, common LO signal phase can be ensured (e.g., synchronized phase of the TX or RX signals) in all of the RFEMs used in the MAA 7100 . In comparison, an IF-over-coax distributed phased array systems, synthesizers and frequency dividers located in the different RFEMs might have unsynchronized phase each time the RFEM is powered up or the operation frequency is changed. The unsynchronized phase, therefore, can necessitate preforming a new beam-forming procedure, which can be a time-consuming operation that degrades the overall link throughput and quality.

Referring to FIG. 71 , the distributed phased array communication system 7100 can include RFEM 7102 coupled to the BBS 7104 via a single coax cable 7106 . The RFEM 7102 can include a phased antenna array 7108 , a RF receiver 7110 , a RF transmitter 7112 , a duplexer 7136 , and a transmit (TX)/receive (RX) switch 7134 . The RF receiver 7110 can include a plurality of power amplifiers 7116 , a plurality of phase shifters 7118 , an adder 7120 , and RF amplifier 7122 . The RF transmitter 7112 can include a RF amplifier 7132 , an adder 7130 , a plurality of phase shifters 7128 , and a plurality of amplifiers 7126 .

In an example receive operation, the switch 7134 can activate receiver chain processing. The antenna array 7108 can be used for receiving a plurality of signals 7114 . The received signals 7114 can be amplified by amplifiers 7116 and their phase can be adjusted by corresponding phase shifters 7118 . Each of the phase shifters 7118 can receive a separate phase adjustment signal (not illustrated in FIG. 71 ) from a control circuitry (e.g., from a modem within the BBS 7104 ), where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 7108 . The phase adjusted signals at the output of the phase shifters 7118 can be summed by the adder 7120 and then amplified by the RF amplifier 7122 to generate an RF input signal 7123 . The RF input signal 7123 can be communicated to the BBS 7104 via the duplexer 7136 and the coax cable 7106 . In some aspects, the RF input signal 7123 can be a 60 GHz signal or another signal in a millimeter wave band including a 5G communication band.

In an example transmit operation, the switch 7134 can activate transmitter chain processing. The RFEM 7102 can receive a RF output signal 7131 from the BBS 7104 via the coax cable 7106 and the duplexer 7136 . The RF signal 7131 can be amplified by RF amplifier 7132 and then communicated to adder 7130 . The adder 7130 generates multiple copies of the amplified RF signal and communicates the signal copies to the plurality of phase shifters 7128 . The plurality of phase shifters 7128 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 7126 . The plurality of amplifiers 7126 generates a plurality of signals 7124 for transmission by the phased antenna array 7108 . In some aspects, the RFEMs 7138 - 7140 can be the same as RFEM 7102 .

Even though FIG. 71 does not provide details of the BBS 7104 , the BBS 7104 can be the same as BBS 6904 and can include the blocks illustrated in FIG. 70 . As seen in FIG. 70 , a single synthesizer 7028 is used within the BBS 6904 . By using a single BBS (e.g., 7104 ) that includes an LO generator (e.g., synthesizer 7028 which can include a RF synthesizer, an IF synthesizer, etc.) shared between the RFEMs, there is phase correlation between the LO frequencies generated by the LO generator within the single BBS and the outgoing RF signals communicated by the phased antenna arrays of the multiple RFEMs. In this regard, all of the signals transmitted by the phased antenna arrays of RFEMs 7102 , 7138 , . . . , 7140 will have the same phase.

Even though FIG. 69 , FIG. 70 , and FIG. 71 discloses the use of a single coax cable to connect the BBS with the RFEM, the disclosure is not limited in this regard and other types of connections can be used as well. For example, another type of a millimeter wave connection or cable can be used instead of the single coax cable. Other types of connections that can be used include semi-rigid cables, flexible cables of a flexible substrate, printed RF transmission lines on PCB, rigid flex board, and so forth. For example and in reference to FIG. 71 , a rigid flex board can be used in lieu of coax cable 7106 , 7144 , and 7146 , where the multiple RFEMs can be fed via RF lines that propagate from the main BBS 7104 to the RFEM's in different locations using flexible portion of the connection board (e.g., RF over flex portion of a rigid flex board). In this way, the RFEM can fold over and bend over in different areas in a system based on PC/mobile form factor or in a base station chassis.

Coaxial (coax) cables have been used as transmission lines for transmitting RF signals from the motherboard of a laptop to the hinged lid of the laptop, from whence the signal may be transmitted via the coax to an antenna or a phased antenna array in the laptop lid. The cable would proceed from a transceiver that includes a radio frequency integrated circuit (RFIC) on the motherboard, usually located below the keyboard, through a hole or tube in a hinge to the lid, and then on to an antenna or antenna array within the lid. However, this configuration has suffered from signal loss, especially by cable degradation over time. This signal loss will become exacerbated as frequency of operation increases. In some applications, laptops may have more than one frequency range, for example, Wi-Fi, WiGig, and 5G, at the same time, requiring more than one cable going through the hinge, which is an already dense environment. Consequently a need has arisen to ease the foregoing issues of one or more cables through a hinge, with the power loss occasioned by the cables particularly as frequencies of operation increase significantly.

In some aspects, using one or more waveguides, depending on the number of RF signal frequencies, as a transmission line, is an effective way to pass RF signals from the mother board to the lid through the hinge. In some aspects an optical fiber may be used, which can handle essentially any RF frequency range. In addition an optical fiber can transmit a plurality of frequency ranges at one time. An additional advantage is that optical fiber would suffer less degradation over time compared to coax cable. Using either waveguide or optical fiber as transmission lines will reduce or minimize the foregoing issues. In some aspects the above solutions can also be used to pass RF signals from the mother board of a tablet or a phone to the chassis of the tablet or phone.

In any of the above cases (laptop, tablet, phone), once the RF signal is passed from the RFIC of the dense device, an important second issue to be resolved is how to pass RF signals within the dense lid of the laptop, or the chassis of the tablet or phone. The issue of how to pass RF signals on or within the dense lid or chassis can be addressed, in some aspects, by use of a waveguide implemented in the metallic chassis. In some aspects, the waveguide can be implemented as a standard hollow-tube waveguide, or as a substrate integrated waveguide (SIW) on a PCB. At the same time, there may be loss of signal power by way of the above transmission lines, whether they be coax cable, waveguide or optical fiber.

A Radio Front End Module (RFEM), that includes amplification, can be coupled to the end of the waveguide or optical fiber prior to the one or more antennas to address these losses. The RF signal can then be transmitted to an antenna element or to a phased antenna array that may be within the lid. In some aspects that distribute the signal via a fiber optic line, the RF signal can be converted to an optical signal to enable transmission from the RFIC through the optical fiber line. Conversion from optical signals back to RF signals enables transmission through the RFEM and onto the antenna or antenna array.

FIG. 72 is an exploded view of a laptop computer illustrating waveguides for RF signals to reach the lid of the laptop computer, according to some aspects. The RF signal waveguides may be incorporated in the antenna array circuitry 330 of mmWave communication circuitry 300 shown in FIG. 3 A , although the RF signal waveguides are not limited to such. The exploded view 7200 illustrates laptop 7201 , with the keyboard illustrated symbolically at 7203 (but not shown) and the lid illustrated symbolically at 7205 . The exploded view of the lid 7205 A is a schematic of a waveguide transmission line in the laptop lid. An RF signal proceeds from a Medium Access Control (MAC) layer/Baseband (MAC BB) sub-system in an RFIC on the mother board of the laptop. The waveguide proceeds through a hole or tube in hinge 7207 , or is made as part of the hinge 7207 , where the waveguide 7207 A then proceeds inside the lid to a splitter/combiner 7209 to provide RF signals to a plurality of waveguides 7211 , 7213 , 7215 , 7217 to respective antennas or antenna arrays located in the lid outboard from waveguide exits 7219 , 7221 , 7223 , 7225 . In practice, there may be only a single frequency band, or there may be multiple frequency bands, generated by the RFIC (e.g., by using one or more LO signals). For example, frequency bands for Wi-Fi, WiGig or 5 M mmWave technology may be generated, according to some aspects.

FIG. 73 is an illustration of one or more coaxial cables proceeding from an RFIC of a laptop computer and entering through a hole in a hinge of the laptop, en route to the lid of the laptop, according to some aspects. In this illustration the laptop has the lid cover and the keyboard cover is removed. The RFIC can be located on a motherboard outboard from coax cables 7301 , in some aspects. Coax cables 7301 proceed from the RFIC to point 7301 A where they pass through hinge hole (or tube) 7303 en route to the laptop lid. In the illustration, two cables 7301 are shown for the case where two frequency bands are generated, according to some aspects. In some examples, one coax may be from a Wi-Fi frequency band RFIC, which in some implementations may have up to three coax cables for multiple-input multiple-output (MIMO) antenna mode. A second frequency band in the aspect under discussion may be at WiGig frequencies.

FIG. 74 is an illustration of one coaxial cable from a radio sub-system of a laptop computer, exiting a hole in a hinge of a laptop lid, en route to an antenna or antenna array in the lid, according to some aspects. Illustration 7400 shows a laptop lid hinged to the laptop. Coax cable 7401 has proceeded through hole 7403 in hinge 7403 A, en route to the antenna or antenna array in the lid of the laptop, which antenna array is outboard of point 7401 A, according to some aspects. The back side of the screen is illustrated at 7405 , with screw 7405 A being at one point at which the back side 7405 may be secured to the chassis of the laptop. The antennas used relate to the frequency band of operation. In the case of Wi-Fi or Long Term Evolution (LTE) the antennas may be passive individual antennas, in some aspects. In the case of WiGig or 5G frequency bands, the coax cables may be coupled to individual RFEM instances which are coupled to one or more antennas in other aspects, as discussed in additional detail below.

FIG. 75 is a schematic of transmission lines for signals from a motherboard of a laptop computer to the lid of the laptop, and to a radio front end module (RFEM), according to some aspects. Illustrated at 7500 is a schematic of below-the-keyboard laptop chassis 7502 and lid indicated generally at 7504 . The lid 7504 is hinged to chassis 7502 by hinges 7505 , 7507 . RFIC 7501 is connected to transmission line 7503 . Transmission line 7503 may be either a waveguide or optical fiber.

The transmission line 7503 can proceed through hinge 7505 , exiting the hinge. In aspects where a waveguide is the transmission line, the waveguide can be part of the hinge. Because the waveguide may be lossy, there will be a certain amount of signal attenuation as the signal proceeds along the waveguide or optical fiber 7509 . In cases where the transmission line 7509 is optical fiber, an optical signal to RF signal convertor would be placed at 7511 A so that RF signals would be available to RFEM 7511 . RFEM 7511 may include a power amplifier, and may be used to amplify the signal to account for the signal attenuation, according to some aspects.

On the RFIC side, if transmission line 7503 is an optical fiber line, then upon exit from RFIC 7501 , an RF signal to optical signal converter may be incorporated at 7501 A, according to some aspects. A laser may be used for this RF signal to optical signal conversion in some aspects. When the optical signal approaches RFEM 7511 A, the optical signal should be converted back to an RF signal at 7310 . A PIN diode or an Avalanche PIN diode can be placed at 7511 A and used for this optical signal to RF signal conversion in some aspects.

Another implementation for RF signal to optical signal conversion is RF Over Fiber sometimes called Radio over Fiber. Radio over Fiber (RoF) or RF over Fiber (RFoF) refers to a technology whereby light is modulated by a radio frequency signal and transmitted over an optical fiber link. Main technical advantages of using fiber optical links are lower transmission losses and reduced sensitivity to noise and electromagnetic interference compared to all-electrical signal transmission. In some aspects, the optical signal can pass data at essentially all frequencies, including Wi-Fi, LTE, 5G, and WiGig, among others.

In some aspects the conversion from optical signal to RF signal may be implemented by a PIN diode or an Avalanche PIN diode, which may be placed at 7511 A of FIG. 75 or at 7610 ′ and 7612 of FIG. 76 , as discussed below. If a laser were used for RF signal to optical signal conversion at 7501 A of FIG. 75 , then the converted output RF signal from the PIN diode or the Avalanche PIN diode at 7511 A may be digital bits. Therefore, a very fast optical interface can pass digital bits to an REFM. Consequently, the transceiver of the RFEM can be fed with digital electrical bits and the RFEM will operate to amplify the digital bits for ultimate radiation by the antennas as RF signals.

Alternatively, if RFoF is used for RF signal to optical conversion at 7501 A, the RF signal to optical signal conversion results in an optical signal modulated with the RF signal. In this case, the PIN diode or the Avalanche PIN diode conversion at 7511 A of FIG. 75 (or at 7610 ′ and 7612 of FIG. 76 , as the case may be), can then also generate the original RF signal from the RF modulated optical signal, and can pass the RF signal to the RFEM 7511 for processing.

FIG. 76 is a schematic of transmission lines for signals from a motherboard of a laptop computer to the lid of the laptop, and to a plurality of RFEMs 7611 and 7613 , according to some aspects. The schematic of FIG. 76 is similar to that of FIG. 75 except that two RFEMs are used. An optical signal to RF signal convertor such as discussed above may be used in two places, 7610 ′ and 7612 where the transmission line is optical fiber, according to some aspects.

If the two RFEMs 7611 and 7613 are working on the same frequency band, but only of them is active at a time, which is relevant both to 5G and to WiGig implementation, there need be only one optical signal to RF signal convertor, which may be placed at 7610 ′, according to some aspects. In this case, the two optical signal to RF signal convertors (at 7610 , 7612 ) would not be needed because of the fact that the two RFEMs 7611 , 7613 are working at the same frequency. This is an option that would provide better spatial coverage because the RFEM that provides the better coverage of the two would be active. This may be accomplished by the two RFEMs being algorithmically controlled based on feedback information from a receiving device or system to determine which RFEM provides the better coverage at a given time, according to some aspects.

On the other hand, if the two RFEMs 7611 , 7613 are operating in different frequency bands, for example one at 5G and one at WiGig, the two RFEMs would work at the same time. In this case there would be two optical signal to RF signal convertors discussed above, placed at 7610 ′ and 7612 respectively, in some aspects.

FIGS. 77 A and 77 B are illustrations of substrate integrated waveguides (SIW), according to some aspects. In FIG. 77 A, 7700 is a perspective view of an SIW with a coplanar transmission line connected to the SIW as an RF signal source, according to some aspects. The SIW itself may be made from a PCB such as FR4 or other suitable PCB. SIW 7700 has top 7701 and bottom 7703 and two lines of vias, one of them beginning with via 7705 and another beginning with via 7707 . The lines of vias are dense enough to function effectively as sides of the PCB that guide the RF signal in a desired direction, according to some aspects. Co-planar waveguide 7701 A includes a source of RF signals in one aspect, and signal transmission is in the direction of the arrow in the aspect under discussion.

FIG. 77 B is an illustration as an SIW with a micro strip feeding the SIW according to some aspects. SIW 7702 has top 7704 and a bottom (not shown) and two lines of vias. One of the lines of vias begins with via 7706 and another begins with via 7708 , where the lines of vias are dense enough to function effectively as sides of the PCB that guide the RF signal in a desired direction, according to some aspects. Fingers are implemented at 7708 and a microstrip line 7704 matches the fingers and includes a source of RF signals in some aspects. Signal transmission is in the direction of the arrow in the aspect under discussion. Those of ordinary skill in the art would recognize that the above two figures are examples only, and that other forms of SIWs may be used.

Distributed phased array systems (e.g., WiGig and 5G cellular systems) are currently used in laptops, tablets, smart phones, docking stations and other applications. Current distributed phased array systems used for WiGig and 5G communications are either super-heterodyne (dual conversion) or sliding-IF systems. In these systems, a MAC-PHY baseband sub-system receives or transmits an intermediate frequency (IF) signal, which necessitates the use of IF amplification stages, RF-IF mixers, high selectivity bandpass filters and other circuitry necessary for communicating IF signals between circuits, as well as up-conversion and down-conversion of the IF signals.

Data signals are often times communicated to a front-end module with a direct current (DC) power signal. Some of the data signals can be modulated near baseband and, due to the presence of low-frequency components in the signal, RF choke circuits are used at the front-end circuit to produce a clean DC power signal. The RF choke circuit, however, can be expensive and bulky. Additionally, when clock signals are communicated to the front-end module, clock signal components can leak from the communication medium, which can be a significant noise source in the communication system

FIG. 78 illustrates an example RF front-end module (RFEM) of a distributed phased array system 7800 with clock noise leakage reduction according to some aspects. The distributed phased array system 7800 may be incorporated in the digital baseband circuitry 310 , the transmit circuitry 315 , and the receive circuitry 320 of mmWave communication circuitry 300 shown in FIG. 3 A , although the distributed phased array system 7800 is not limited to such.

Referring to FIG. 78 , the RFEM 7802 is coupled to a baseband sub-system (BBS) 7804 via a single coax cable 7806 . The RFEM 7802 can include a phased antenna array 7808 , a RF receiver 7810 , a RF transmitter 7812 , a local oscillator (LO) generator 7844 , a clock despreader 7852 , a triplexer 7848 , and a transmit (TX)/receive (RX) switch 7840 . The RF receiver 7810 can include a plurality of power amplifiers 7816 , a plurality of phase shifters 7818 , a combiner 7820 , an RF amplifier 7822 , an LO amplifier 7826 , and a multiplier (or mixer) 7824 . The RF receiver 7810 can also include an IF amplifier 7842 . In some aspects, the IF amplifier 7842 can be part of the receiver 7810 or it can be implemented outside of the receiver 7810 .

The RF transmitter 7812 can include a multiplier (or mixer) 7838 , LO amplifier 7840 , a RF amplifier 7836 , a splitter 7834 , a plurality of phase shifters 7832 , and a plurality of amplifiers 7830 . The RF transmitter 7812 can also include an IF amplifier 7846 . In some aspects, the IF amplifier 7846 can be part of the transmitter 7812 or it can be implemented outside of the transmitter 7812 .

The BBS 7804 can be configured to generate one or more control signals for communication to the RFEM 7802 . Example control signals include power ON/OFF signals, transmit (TX) mode activation, receive (RX) mode activation, signal power UP or DOWN, system wake up signal, low-power activation signal, phase or gain adjustment signals, and so forth. Since the control signal is modulated near baseband prior to communication to the RFEM, this can result in a large low-frequency component in the signal. The large low-frequency component, in turn, results in large RF choke component at the RFEM to produce a clean DC power signal (which is communicated together with the control signal). Even though the figures illustrate control signals communicated from the BBS to the RFEM, the disclosure is not limited in this regard, and control signals may be communicated from the RFEM to the BBS. For example, the RFEM can send to the BBS control signals, such as power reading signals, temperature reading signals, command acknowledgement signals, and so forth.

In some aspects, reference clock signal leaks from the coax cable 7806 connecting the BBS 7804 and the RFEM 7802 can be reduced by modulating (e.g., using the clock spreader 7850 ) a control signal using the clock signal, and then communicating the modulated signal (from the BBS to the RFEM) in place of the clock signal. The RFEM can include a clock despreader 7852 , which can be used to recover the control signal and the clock signal. By communicating a modulated signal (in lieu of a separate control signal and a clock signal) the RF choke component requirements can be improved (e.g., a smaller inductor or ferrite bead is used in the RF choke) since the resulting modulated signal is further away from DC and does not include as many low-frequency components as the baseband-modulated control signal.

In an example receive operation, the switch 7840 can activate receiver chain processing. The antenna array 7808 can be used for receiving a plurality of signals 7814 . The received signals 7814 can be amplified by amplifiers 7816 and their phase can be adjusted by corresponding phase shifters 7818 . Each of the phase shifters 7818 can receive a separate phase adjustment signal (not illustrated in FIG. 78 ) in the form of a control signal (e.g., control signal 7860 generated by the clock despreader 7852 when dispreading the received modulated signal 7854 ) originating from a control circuitry (e.g., from a modem within the BBS 7804 ).

The individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 7808 . The phase adjusted signals at the output of the phase shifters 7818 can be combined by combiner 7820 and then amplified by the RF amplifier 7822 . The LO generator 7844 can generate an LO signal using a clock reference signal 7858 generated by the clock despreader 7852 using the modulated signal 7854 received from the BBS 7804 via the coax cable 7806 . The LO signal can be amplified by the amplifier 7826 and then multiplied with the output of amplifier 7822 using the multiplier 7824 in order to generate an IF input signal 7845 . The IF input signal 7845 can be amplified by amplifier 7842 and then communicated to the BBS 7804 via the triplexer 7848 and the coax cable 7806 as a data signal 7856 . In some aspects, the IF input signal 7845 can be centered around 10.56 GHz signal.

In an example transmit operation, the switch 7840 can activate transmitter chain processing. The BBS 7804 can modulate the control signal 7860 on the clock reference signal 7858 using the clock spreader 7850 , to generate the modulated signal 7854 . The modulated signal 7854 and an IF data signal 7856 can be communicated to the RFEM 7802 via the coax cable 7806 . The data signal 7856 can include an IF signal 7847 for transmission. The RFEM 7802 can receive the IF signal 7847 via the coax cable 7806 and the triplexer 7848 . The IF signal 7847 can be amplified by the IF amplifier 7846 and then communicated to multiplier 7838 . The multiplier 7838 can receive an up-conversion LO signal from the LO generator 7844 and the LO amplifier 7840 . The amplified LO signal is multiplied with the amplified received IF signal by the multiplier 7838 to generate an RF signal. The RF signal is then amplified by amplifier 7836 and communicated to splitter 7834 . The splitter 7834 generates multiple copies of the amplified signal and communicates signal copies to the plurality of phase shifters 7832 . The plurality of phase shifters 7832 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 7830 . The plurality of amplifiers 7830 generate a plurality of signals 7828 for transmission by the phased antenna array 7808 .

In some aspects, triplexers illustrated in the attached figures can also include a transmit/receive switch, which can be used to determine the signals to be multiplexed by the triplexers.

FIG. 79 illustrates a baseband sub-system (BBS) of a distributed phased array system with clock noise leakage reduction according to some aspects. Referring to FIG. 79 , the BBS 7804 can include a triplexer 7902 , an IF receiver 7904 , an IF transmitter 7906 , a modem 7924 , a crystal oscillator 7930 , a synthesizer 7928 , a divider 7926 , and a clock spreader 7850 . The synthesizer 7928 may include suitable circuitry, logic, interfaces and/or code and can use a signal from the crystal oscillator 7930 to generate a clock signal. The generated clock signal can be divided by the divider 7926 to generate an output clock reference signal 7858 . The output clock reference signal 7858 can be communicated to the clock spreader 7850 together with a control signal 7860 . The control signal 7860 can be generated by the modem 7924 and can be used to control one or more functionality of the communication system 7800 , such as functionalities of the RFEM 7802 .

Example functionalities that can be controlled using the control signal 7860 include activation of the transmission mode, activation of a reception mode, power up, power down, activate low power mode, circuit wake up, beam change signals, phase and/or gain adjustment, and so forth. The clock spreader 7850 may include suitable circuitry, logic, interfaces and/or code and can be configured to modulate the control signal 7860 on the clock reference signal 7858 to generate the modulated signal 7854 for transmission to the RFEM 7802 via the coax cable 7806 . In some aspects, the generated clock signal can be centered around a frequency of 1.32 GHz.

The IF receiver 8204 can include an IF amplifier 7908 , mixers 7910 , filters 7912 , and analog-to-digital conversion (ADC) blocks 7914 . The IF transmitter 7906 can include digital-to-analog conversion (DAC) blocks 7922 , filters 7920 , mixers 7918 , and IF amplifier 7916 .

In an example receive operation, an IF signal (e.g., 7845 received as data signal 7856 ) is received from the RFEM 7802 via the triplexer 7902 and is amplified by IF amplifier 7908 . The amplified IF signal can be down-converted to baseband signals by the mixers 7910 , then filtered by low-pass filters 7912 , and converted to a digital signal by the ADC blocks 7914 before being processed by the modem 7924 .

In an example transmit operation, a digital signal output by the modem 7924 can be converted to analog signals by the DAC blocks 7922 . The analog signals are then filtered by the low-pass filters 7920 and then up-converted to an IF signal by the mixers 7918 . The IF signal can be amplified by the IF amplifier 7916 , and then communicated to the RFEM 7802 via the triplexer 7848 and the single coax cable 7806 as a data signal 7856 , together with the modulated signal 7854 . In some aspects, the BBS 7804 can also communicate a DC power signal together with the data signal 7856 and the modulated signal 7854 to the RFEM 7802 .

FIG. 80 illustrates a frequency diagram of signals communicated between a RFEM and a BBS according to some aspects. Referring to FIG. 80 , the frequency diagram 8000 illustrates various signals, which can be communicated between the RFEM 7802 and the BBS 7804 via the single coax cable 7806 . For example, the BBS 7804 can communicate a DC power signal 8002 , a control signal 8004 , and the clock signal 8006 . Additionally, data signals 8010 can be communicated between the BBS 7804 and the RFEM 7802 .

For example, an IF data signal 7845 can be communicated from the RFEM 7802 to the BBS 7804 , and an IF data signal 7847 can be communicated from the BBS 7804 to the RFEM 7802 . The clock signal 8006 can be the same as the LO generation clock reference signal 7858 received by the RFEM 7802 from the BBS 7804 . In some aspects, the clock signal 8006 can be centered around a 1.32 GHz signal. In some aspects, the control signal 8004 can be communicated from the BBS 7804 to the RFEM 7802 and can indicate phase adjustment values for use by the phase shifters 7818 and the phase shifters 7832 . The control signal 8004 can indicate to the RFEM 7802 other control functions, such as power up, power down, increase or decrease transmit power, gain adjustment and other functionalities as mentioned herein above.

As seen in FIG. 80 , the signal spectrum of signals communicated between the RFEM 7802 and the BBS 7804 can include some undesirable signals, such as the clock harmonics 8008 as well as harmonics of the control signal 8004 . Since the control signal 8004 is modulated near baseband prior to communication to the RFEM, this can result in a large low-frequency component in the signal. The large low-frequency component, in turn, results in large RF choke component at the RFEM to produce a clean DC power signal 8002 (which is communicated together with the control signal). Additionally, the reference clock signal 8006 (as well as associated harmonics 8008 ) can leak from the coax cable connection 7806 , and can be a noise source in the platform. In some aspects, a clock spreader circuit 7850 and a clock despreader circuit 7852 can be used at the BBS 7804 and the RFEM 7802 respectively, to address the above-mentioned drawbacks associated with communication of separate control and clock signals on the coax cable 7806 .

FIG. 81 illustrates clock spreader and despreader circuits, which can be used in connection with clock noise leakage reduction according to some aspects. Referring to FIG. 81 , there is illustrated another view of the communication system 7800 that includes the BBS 7804 and the RFEM 7802 . More specifically, FIG. 81 illustrates a more detailed view of the clock spreader 7850 and the clock despreader 7852 .

As seen in FIG. 81 , the BBS 7804 can include transceiver 8120 and clock spreader 7850 . The transceiver 8120 can include all the blocks illustrated in FIG. 79 except the clock spreader 7850 . Similarly, the RFEM 7802 can include the clock despreader 7852 , the LO generator 7844 , a switch 8132 , and transceiver 8130 . The transceiver 8130 can include, for example, the receiver 7810 , the transmitter 7812 , the amplifiers 7842 and 7846 , and the triplexer 7848 illustrated in FIG. 78 .

The clock spreader 7850 can include a pulse shaper circuit 8106 and a modulator circuit 8102 . The pulse shaper circuit 8106 can be configured to receive the control signal 7860 and generate a band-limited control signal 7861 . In some aspects, the pulse shaper 8106 can attenuate one or more of the harmonics associated with control signal 7860 to generate the band-limited control signal 7861 . The modulator 8102 can include a multiplier 8104 , which can be used to receive the band-limited control signal 7861 as well as the clock reference signal 7858 , and to multiply them to generate the modulated signal 7854 .

In some aspects, the modulator 8102 can be one of a binary phase-shift keying (BPSK) modulator, a differential phase-shift keying (DPSK) modulator, a quadrature phase-shift keying (QPSK) modulator, a Gaussian frequency shift keying (GFSK) modulator, or another type of modulator. In some aspects, the modulator 8102 can be configured to spread the clock reference signal 7858 using a pseudorandom sequence to generate the modulated signal 7854 .

The modulated signal 7854 can be communicated (e.g., together with a DC power signal and an IF data signal) to the RFEM 7802 via the coax cable connection 7806 . The clock despreader 7852 within the RFEM 7802 can include a clock recovery circuit 8134 and a demodulator 8136 . The modulated signal 7854 can be communicated to both the clock recovery circuit 8134 and the demodulator 8136 . The clock recovery circuit 8134 can include a multiplier 8138 and a divider 8140 . The clock recovery circuit 8134 can use the modulated signal 7854 to recover the clock reference signal 7858 . The recovered clock reference signal can be communicated to the switch 8132 as well as to the demodulator 8136 . The demodulator 8136 can receive the modulated signal 7854 and use the clock reference signal 7858 to demodulate and recover the control signal 7860 . The control signal 7860 can be communicated to the switch 8132 . The switch 8132 can be configured to communicate the control signal 7860 and the reference clock signal 7858 to the transceiver 8130 , as well as to communicate the clock signal 7858 to the LO generator 7844 for generating up-conversion or down-conversion LO reference signals.

FIG. 82 illustrates a frequency diagram of signals communicated between a RFEM and a BBS using clock noise leakage reduction according to some aspects. Referring to FIG. 82 , there are illustrated frequency diagrams 8202 and 8210 illustrating communicated signals when clock noise leakage reduction is deactivated or activated. More specifically, diagram 8202 (which is similar to the signal diagram 8000 of FIG. 80 ) illustrates signals that can be communicated within communication system 7800 when clock noise leakage reduction is not active. As seen in diagram 8202 , a DC power signal 8203 , a control signal 8204 , a clock signal 8206 , as well as harmonics 8208 of the control signal 8204 can be communicated from the BBS to the RFEM when clock noise leakage reduction is not activated (e.g., clock spreader 7850 and clock despreader 7852 are not being used).

In an example when clock noise leakage reduction is activated and clock spreader 7850 and clock despreader 7852 are being used, the communicated signals are illustrated in diagram 8210 . More specifically, the control signal 8204 is modulated on the clock signal 8206 to generate the modulated signal 8212 , which is communicated (with harmonics 8214 ) from the BBS to the RFEM in lieu of separate signals 8204 and 8206 . As seen in diagram 8210 , the modulated signal 8212 is further away from the DC signal 8203 , which can be used to alleviate RF choke requirements at the RFEM (e.g., the RF choke can include smaller inductors or ferrite beads). Additional benefit is also achieved since a modulated signal 8212 is communicated instead of a single sine wave clock signal 8206 , which reduces noise leakage along the coax cable 7806 .

Distributed phased array systems (e.g., WiGig and 5G cellular systems) are currently used in laptops, tablets, smart phones, docking stations and other applications. Current distributed phased array systems used for WiGig and 5G communications are either super-heterodyne (dual conversion) or sliding-IF systems. In these systems, the MAC-PHY baseband sub-system receives or transmits an intermediate frequency (IF) signal, which necessitates the use of IF amplification stages, RF-IF mixers, high selectivity bandpass filters and other circuitry necessary for communicating IF signals between circuits, as well as up-conversion and down-conversion of the IF signals.

The additional circuitry for IF signal processing results in a larger front-end module, higher cost for the distributed phased array system, and lower system performance. Additionally, some mmWave and IF frequency processing performed in the baseband sub-system may not be desired for some system vendors. Furthermore, interactions between the IF circuits (especially the frequency source) and the high-power amplifiers can cause multiple kinds of interference that degrade system performance.

FIG. 83 illustrates an exemplary RF front-end module (RFEM) of a distributed phased array system with IF processing according to some aspects. The distributed phased array system may be incorporated in the digital baseband circuitry 310 , the transmit circuitry 315 , and the receive circuitry 320 of mmWave communication circuitry 300 shown in FIG. 3 A , although the distributed phased array system is not limited to such.

Referring to FIG. 83 , the RFEM 8302 is coupled to a baseband sub-system (BBS) 8304 via a single coax cable 8306 . The RFEM 8302 can include a phased antenna array 8308 , an RF receiver 8310 , an RF transmitter 8312 , a local oscillator (LO) generator 8344 , a triplexer 8348 , and a transmit (TX)/receive (RX) switch 8340 . The RF receiver 8310 can include a plurality of power amplifiers 8316 , a plurality of phase shifters 8318 , a combiner 8320 , an RF amplifier 8322 , an LO amplifier 8326 , and a mixer 8324 . The RF receiver 8310 can also include an IF amplifier 8342 .

The RF transmitter 8312 can include a mixer 8338 , LO amplifier 8340 , an RF amplifier 8336 , a splitter 8334 , a plurality of phase shifters 8332 , and a plurality of amplifiers 8330 . The RF transmitter 8312 can also include an IF amplifier 8346 .

In an example receive operation, the switch 8340 can activate receiver chain processing. The antenna array 8308 can be used for receiving a plurality of signals 8314 . The received signals 8314 can be amplified by amplifiers 8316 and their phase can be adjusted by corresponding phase shifters 8318 . Each of the phase shifters 8318 can receive a separate phase adjustment signal (not illustrated in FIG. 83 ) from a control circuitry (e.g., from a modem within the BBS 8304 ), where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 8308 . The phase adjusted signals at the output of the phase shifters 8318 can be combined by the combiner 8320 and then amplified by the RF amplifier 8322 . The LO generator 8344 can generate a LO signal using a clock frequency signal 8343 received from the BBS 8304 via the coax cable 8306 . The LO signal can be amplified by the amplifier 8326 and then multiplied with the output of amplifier 8322 using the mixer 8324 in order to generate an IF input signal 8345 . The IF input signal 8345 can be amplified by amplifier 8342 and then communicated to the BBS 8304 via the triplexer 8348 and the coax cable 8306 . In some aspects, the IF input signal 8345 can be centered around a 10.56 GHz signal.

In an example transmit operation, the switch 8340 can activate transmitter chain processing. The RFEM 8302 can receive an IF signal 8347 from the BBS 8304 via the coax cable 8306 and the triplexer 8348 . The IF signal 8347 can be amplified by IF amplifier 8346 and then communicated to the mixer 8338 . The mixer 8338 can receive an up-conversion LO signal from the LO generator 8344 and the LO amplifier 8340 . The amplified LO signal is multiplied with the amplified received IF signal by the mixer 8338 to generate an RF signal. The RF signal is then amplified by amplifier 8336 and communicated to the splitter 8334 . The splitter 8334 generates multiple copies of the amplified signal and communicates signal copies to the plurality of phase shifters 8332 . The plurality of phase shifters 8332 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 8330 . The plurality of amplifiers 8330 generates a plurality of signals 8328 for transmission by the phased antenna array 8308 .

FIG. 84 illustrates a baseband sub-system (BBS) of the distributed phased array system of FIG. 83 according to some aspects. Referring to FIG. 84 , the BBS 8304 can include a triplexer 8402 , an IF receiver 8404 , an IF transmitter 8406 , a modem 8424 , a crystal oscillator 8430 , a synthesizer 8428 , and a divider 8426 . The synthesizer 8428 may include suitable circuitry, logic, interfaces and/or code and can use a signal from the crystal oscillator 8430 to generate a clock signal. The generated clock signal can be divided by the divider 8426 to generate an output clock reference signal 8432 for communication to the RFEM 8302 . In some aspects, the generated clock reference signal 8432 can be centered around a frequency of 1.32 GHz.

The IF receiver 8404 can include an IF amplifier 8408 , mixers 8410 , filters (e.g., low-pass filters) 8412 , and analog-to-digital conversion (ADC) blocks 8414 . The IF transmitter 8406 can include digital-to-analog conversion (DAC) blocks 8422 , filters 8420 , mixers 8418 , and IF amplifier 8416 .

In an example receive operation, an IF signal (e.g., 8345 ) is received from the RFEM 8302 via the triplexer 8402 and is amplified by IF amplifier 8408 . The amplified IF signal can be down-converted to baseband signals by the mixers 8410 , then filtered by low-pass filters 8412 , and converted to a digital signal by the ADC blocks 8414 before being processed by the modem 8424 .

In an example transmit operation, a digital signal output by the modem 8424 can be converted to analog signals by the DAC blocks 8422 . The analog signals are then filtered by the low-pass filters 8420 and then up-converted to an IF signal by the mixers 8418 . The IF signal can be amplified by the IF amplifier 8416 , and then communicated to the RFEM 8302 via the triplexer 8402 and the single coax cable 8306 .

FIG. 85 illustrates a multi-band distributed phased array system with IF processing within the RFEMs according to some aspects. Referring to FIG. 85 , the RFEMs 8502 , . . . , 8504 are coupled to a baseband sub-system (BBS) 8506 via corresponding connections (e.g., coax cables 8552 , . . . , 8554 respectively). In some aspects, each of the RFEMs 8502 , . . . , 8504 can be configured for reception and transmission of wireless signals in a specific band (e.g., a 28 GHz band, a 39 GHz band, a 60 GHz ISM band such as WiGig or a 5G communication band). Even though description of the functionalities of RFEM 8502 are provided below, the additional RFEMs (e.g., RFEM 8504 ) can be configured in a similar fashion.

The RFEM 8502 can include a phased antenna array 8508 , an RF receiver 8510 , an RF transmitter 8512 , a local oscillator (LO) generator 8542 , a triplexer 8550 , and a transmit (TX)/receive (RX) switch 8548 . The RF receiver 8510 can include a plurality of power amplifiers 8516 , a plurality of phase shifters 8518 , a combiner 8520 , an RF amplifier 8522 , an LO amplifier 8526 , and a mixer 8524 . The RF receiver 8510 can also include an IF amplifier 8544 .

The RF transmitter 8512 can include a mixer 8538 , LO amplifier 8540 , an RF amplifier 8536 , a splitter 8534 , a plurality of phase shifters 8532 , and a plurality of amplifiers 8530 . The RF transmitter 8312 can also include an IF amplifier 8546 .

In an example receive operation, the switch 8548 can activate receiver chain processing. The antenna array 8508 can be used for receiving a plurality of signals 8514 . The received signals 8514 can be amplified by amplifiers 8516 and their phase can be adjusted by corresponding phase shifters 8518 . Each of the phase shifters 8518 can receive a separate phase adjustment signal (not illustrated in FIG. 85 ) from a control circuitry (e.g., from a modem within the BBS 8506 ), where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 8508 . The phase adjusted signals at the output of the phase shifters 8518 can be combined by the combiner 8520 and then amplified by the RF amplifier 8522 . The LO generator 8542 can generate a LO signal using a clock frequency signal received from the BBS 8506 via the coax cable 8552 . The LO signal can be amplified by the amplifier 8526 and then multiplied with the output of amplifier 8522 using the mixer 8524 in order to generate an IF input signal. The IF input signal can be amplified by amplifier 8544 and then communicated to the BBS 8506 via the triplexer 8550 and the coax cable 8552 . In some aspects, the IF input signal can be a 10.56 GHz signal.

In an example transmit operation, the switch 8548 can activate transmitter chain processing. The RFEM 8502 can receive an IF signal from the BBS 8506 via the coax cable 8552 and the triplexer 8550 . The IF signal can be amplified by IF amplifier 8546 and then communicated to the mixer 8538 . The mixer 8538 can receive an up-conversion LO signal from the LO generator 8542 and the LO amplifier 8540 . The amplified LO signal is multiplied with the amplified received IF signal by the mixer 8538 to generate an RF signal. The RF signal is then amplified by amplifier 8536 and communicated to the splitter 8534 . The splitter 8534 generates multiple copies of the amplified signal and communicates signal copies to the plurality of phase shifters 8532 . The plurality of phase shifters 8532 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 8530 . The plurality of amplifiers 8530 generates a plurality of signals 8528 for transmission by the phased antenna array 8508 .

FIG. 86 illustrates a distributed phased array system with an RFEM coupled to a BBS via a single coax cable for communicating RF signals according to some aspects. Referring to FIG. 86 , the distributed phased array communication system 8600 can include RFEM 8602 coupled to a baseband sub-system (BBS) 8604 via a single coax cable 8606 . The RFEM 8602 can include a phased antenna array 8608 , an RF receiver 8610 , an RF transmitter 8612 , a duplexer 8636 , and a transmit (TX)/receive (RX) switch 8634 . The RF receiver 8610 can include a plurality of power amplifiers 8616 , a plurality of phase shifters 8618 , a combiner 8620 , and an RF amplifier 8622 . The RF transmitter 8612 can include an RF amplifier 8632 , a splitter 8630 , a plurality of phase shifters 8628 , and a plurality of amplifiers 8626 .

In an example receive operation, the switch 8634 can activate receiver chain processing. The antenna array 8608 can be used for receiving a plurality of signals 8614 . The received signals 8614 can be amplified by amplifiers 8616 and their phase can be adjusted by corresponding phase shifters 8618 . Each of the phase shifters 8618 can receive a separate phase adjustment signal (not illustrated in FIG. 86 ) from a control circuitry (e.g., from a modem within the BBS 8604 ), where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 8608 . The phase adjusted signals at the output of the phase shifters 8618 can be combined by the combiner 8620 and then amplified by the RF amplifier 8622 to generate an RF input signal 8623 . The RF input signal 8623 can be communicated to the BBS 8604 via the duplexer 8636 and the coax cable 8606 . In some aspects, the RF input signal 8623 can be a 60 GHz signal or another signal in a millimeter wave band including a 5G communication band. In some aspects, the RFEM 8602 can include an adaptive matching block 8638 for impedance matching prior to communication of signals via the coax cable 8606 , as explained herein below.

In an example transmit operation, the switch 8634 can activate transmitter chain processing. The RFEM 8602 can receive an RF output signal 8631 from the BBS 8604 via the coax cable 8606 and the duplexer 8636 . The RF signal 8631 can be amplified by RF amplifier 8632 and then communicated to the splitter 8630 . The splitter 8630 can generate multiple copies of the amplified RF signal and communicate the signal copies to the plurality of phase shifters 8628 . The plurality of phase shifters 8628 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 8626 . The plurality of amplifiers 8626 generates a plurality of signals 8624 for transmission by the phased antenna array 8608 .

FIG. 87 illustrates a more detailed diagram of the BBS of FIG. 86 according to some aspects. Referring to FIG. 87 , the BBS 8604 can include a duplexer 8702 , an RF receiver 8704 , an RF transmitter 8706 , a modem 8724 , a crystal oscillator 8730 , a synthesizer 8728 , and a divider 8726 . The synthesizer 8728 may include suitable circuitry, logic, interfaces and/or code and can use a signal from the crystal oscillator 8730 to generate a clock signal, such as signal 8732 . The generated clock signal 8732 can be used by the RF receiver 8704 to down-convert a received signal using the mixers 8710 . The generated clock signal 8732 can also be used by the RF transmitter 8706 to up-convert a signal using the mixers 8718 .

The clock signal 8732 can also be divided by the divider 8726 to generate a second clock signal 8734 . The generated second clock signal 8734 can be used by the RF receiver 8704 to down-convert a received signal using the mixers 8710 . The generated second clock signal 8734 can also be used by the RF transmitter 8706 to up convert a signal using the mixers 8718 . As seen in FIG. 87 , two separate clock signals 8734 and 8732 can be generated by the synthesizer 8728 and divider 8726 for purposes of performing multiple down-conversion or up-conversion schemes, if necessary in some aspects.

One or both of the two clock signals 8734 and 8732 can be used for down-conversion of RF signals into baseband using one or more intermediate IF stages or, in some instances, conversion from RF to baseband without an intermediate IF stage conversion. Similarly, one or both of the clock signals 8734 and 8732 can be used for up conversion of a baseband signal into an RF signal using one or more intermediate IF stages or, in some instances, conversion from baseband to RF without an intermediate IF stage conversion.

The RF receiver 8704 can include an RF amplifier 8708 , mixers 8710 , filters 8712 , and analog-to-digital conversion (ADC) blocks 8714 . The RF transmitter 8706 can include digital-to-analog conversion (DAC) blocks 8722 , filters 8720 , mixers 8718 , and an RF amplifier 8716 .

In an example receive operation, an RF signal (e.g., 8623 ) is received from the RFEM 8602 via the single coax 8606 and the duplexer 8702 , and is amplified by RF amplifier 8708 . The amplified RF signal can be down-converted to baseband signals by the mixers 8710 , then filtered by low-pass filters 8712 , and converted to a digital signal by the ADC blocks 8714 before being processed by the modem 8724 .

In an example transmit operation, a digital signal output by the modem 8724 can be converted to analog signals by the DAC blocks 8722 . The analog signals are then filtered by the low-pass filters 8720 and then up-converted to an RF signal by the mixers 8718 . The RF signal can be amplified by the RF amplifier 8716 , and then communicated to the RFEM 8602 (e.g., as signal 8631 ) via the duplexer 8702 and the single coax cable 8606 .

In some aspects, the coax cable 8606 can be used for communication of DC power signals (e.g., from the BBS 8604 to the RFEM 8602 ), control signals and RF data signals that received or transmitted by the phased array antenna elements 8608 . The control signals can include phase adjustment signals, power up signals, power down signals, and other control signals communicated from the BBS 8604 to the RFEM 8602 . In some aspects, control signals can include phase adjustment request signals or other data request signals communicated from the RFEM 8602 to the BBS 8604 . In this regard, a direct conversion scheme can be used in connection with a distributed phased array system, where the RFEM and the BBS are coupled via a single coax cable.

In some aspects, the control signal can be used for controlling the RFEM operation (e.g., controlling output power levels, AGC, ON/OFF, etc.). Additionally, the control link between the RFEM and the BBS can be bi-directional, and can be used for BBS-to-RFEM commands and for RFEM-to-BBS telemetry transfer (e.g., PA power detectors reading, ACK after a control command reception, temperature detector reading, etc.).

In some aspects, different types of coax cables (e.g., 8606 ) can be used in connection with a distributed phased array communication system that communicate RF over the coax. For example, high quality coaxial cable, a semi-rigid cable, or a flexible semi-rigid cable can be used as cable 8606 , which will allow for high frequency communication of RF signals with reasonable loss.

In another example, a lower cost coax cable can be used as coax 8606 , which can result in matching (S11) and high loss (S21) issues with high RF frequency communications. These drawbacks can be improved via system design changes, such as adaptive cable matching improvements, robust RX and TX line-ups, and RX and TX non-linearity distortion cancellation.

RF signal communication over a cable can be associated with high losses and matching issues. Due to the high frequency associated with RF cable communication, the variation of the cable matching can be high and unexpected, which affects the power loss between the cable and the load. In an example and in order to overcome these drawbacks, an adaptive impedance matching circuitry (e.g., 8638 and 8736 ) can be used in the RFEM 8602 and the BBS 8604 , as seen in FIGS. 86 - 87 .

In some aspects, higher signal loss associated with the coax cable can be addressed by adding additional gain amplification/adjustment stages (not illustrated in the figures) (e.g., before the cable 8606 and the adaptive matching 8638 within the RFEM 8602 ), which can ensure that a potential high signal loss of a coax cable would not degrade the SNR of the communicated RF signal.

In some aspects, additional gain stages in the RX and TX line-up may lead to non-linearity distortion. However, these signal distortions can be compensated via digital mechanisms, such as pre-distortion adjustment circuitry in the TX path or post-distortion adjustment circuitry in the RX path (not illustrated in the figures).

FIG. 88 illustrates an exemplary distributed phased array system supporting multiple communication bands using multiple RFEMs coupled to a single BBS according to some aspects. Referring to FIG. 88 , the distributed phased array communication system 8800 can be used to implement a multi-band system. More specifically, multiple RFEMs ( 8802 , . . . , 8840 ) can be used with a single BBS ( 8604 ), with each RFEM including a phased antenna array for processing wireless signals in a specific communication band. The RFEMs 8802 , . . . , 8840 can be coupled to the BBS 8804 via corresponding single coax cables 8806 , . . . , 8807 .

Referring to FIG. 88 , the distributed phased array communication system 8800 can include RFEM 8802 coupled to the BBS 8804 via a single coax cable 8806 . The RFEM 8802 can include a phased antenna array 8808 , an RF receiver 8810 , an RF transmitter 8812 , a duplexer 8836 , and a transmit (TX)/receive (RX) switch 8834 . The RF receiver 8810 can include a plurality of power amplifiers 8816 , a plurality of phase shifters 8818 , a combiner 8820 , and an RF amplifier 8822 . The RF transmitter 8812 can include an RF amplifier 8832 , a splitter 8830 , a plurality of phase shifters 8828 , and a plurality of amplifiers 8826 .

In an example receive operation, the switch 8834 can activate receiver chain processing. The antenna array 8808 can be used for receiving a plurality of signals 8814 . The received signals 8814 can be amplified by amplifiers 8816 and their phase can be adjusted by corresponding phase shifters 8818 . Each of the phase shifters 8818 can receive a separate phase adjustment signal (not illustrated in FIG. 88 ) from a control circuitry (e.g., from a modem within the BBS 8804 ), where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 8808 . The phase adjusted signals at the output of the phase shifters 8818 can be combined by the combiner 8820 and then amplified by the RF amplifier 8822 to generate an RF input signal 8823 . The RF input signal 8823 can be communicated to the BBS 8804 via the duplexer 8836 and the coax cable 8806 . In some aspects, the RF input signal 8823 can be a 60 GHz signal or another signal in a millimeter wave band, including a 5G communication band.

In an example transmit operation, the switch 8834 can activate transmitter chain processing. The RFEM 8802 can receive an RF output signal 8831 from the BBS 8804 via the coax cable 8806 and the duplexer 8836 . The RF signal 8831 can be amplified by RF amplifier 8832 and then communicated to the splitter 8830 . The splitter 8830 can generate multiple copies of the amplified RF signal, and communicate the signal copies to the plurality of phase shifters 8828 . The plurality of phase shifters 8828 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 8826 . The plurality of amplifiers 8826 can generate a plurality of signals 8824 for transmission by the phased antenna array 8808 . In some aspects, the remaining RFEMs within the system 8800 can be the same as RFEM 8802 .

Even though FIG. 86 , FIG. 87 , and FIG. 88 disclose the use of a single coax cable to connect the BBS with the RFEM, the disclosure is not limited in this regard and other types of connections can be used as well. For example, another type of a millimeter wave connection or cable can be used instead of the single coax cable. Other types of connections that can be used include semi-rigid cables, flexible cables of a flexible substrate, printed RF transmission lines on PCB, rigid flex board, and so forth. For example and in reference to FIG. 88 , a rigid flex board can be used in lieu of coax cables 8806 , . . . , 8807 , where the multiple RFEMs can be fed via RF lines that propagate from the main BBS 8804 to the RFEM's in different locations using flexible portion of the connection board (e.g., RF over flex portion of a rigid flex board). In this way, the RFEM can fold over and bend over in different areas in a system based on PC/mobile form factor or in a base station chassis.

FIG. 89 illustrates a more detailed diagram of the BBS of FIG. 88 according to some aspects. Referring to FIG. 89 , the BBS 8804 can include a receiver 8904 , a transmitter 8908 , triplexers 8902 and 8906 , a modem 8934 , synthesizers 8948 , 8950 , and 8952 , a down-conversion block 8936 , and an up-conversion block 8942 . In some aspects, the mixer 8910 and amplifier 8912 can form a down-conversion block (such as 8936 ), which can be separate from the receiver 8904 . In some aspects, the mixer 8924 and amplifier 8922 can form an up-conversion block (such as 8942 ), which can be separate from the transmitter 8908 . The down-conversion block 8936 and the up-conversion block 8942 can be used for processing receive or transmit signals associated with the RFEM 8840 . Additional up-conversion or down-conversion blocks can be used within the BBS 8804 in order to process signals associated with additional RFEMs.

The synthesizers 8950 , 8952 , and 8948 may include suitable circuitry, logic, interfaces and/or code and can use a signal from the crystal oscillator 8948 to generate clock signals. In some aspects, the first synthesizer 8952 can generate an LO signal to down-convert an RF signal in a first frequency band (e.g., an RF signal in the millimeter wave band received from the RFEM 8802 ) to an IF signal. In some aspects, the second synthesizer 8948 can generate an LO signal to down-convert an RF signal in a second frequency band (e.g., an RF signal in the millimeter wave band received from the RFEM 8840 ) to an IF signal at the same IF frequency as associated with the synthesizer 8952 . In some aspects, the synthesizer 8950 can be configured to generate an LO signal, which can be used by the mixers 8916 to down-convert an IF signal to baseband, or by the mixers 8928 to up convert a baseband signal to an IF signal.

The receiver 8904 can include a mixer 8910 , an LO amplifier 8912 , an IF amplifier 8914 , mixers 8916 , filters (e.g., low-pass filters) 8918 , and analog-to-digital conversion (ADC) blocks 8920 . The transmitter 8908 can include digital-to-analog conversion (DAC) blocks 8932 , filters 8930 , mixers 8928 , an IF amplifier 8926 , a mixer 8924 , and an LO amplifier 8922 . The down-conversion block 8936 for the second RFEM can include a mixer 8938 and an LO amplifier 8940 . The up-conversion block 8942 for the second RFEM can include a mixer 8946 and an LO amplifier 8944 .

In an example receive operation associated with RFEM 8802 , an RF signal is received from the RFEM 8802 via the triplexer 8902 . The received RF signal is down-converted to an IF signal by the mixers 8910 using an LO signal generated by synthesizer 8952 . The IF signal is amplified by IF amplifier 8914 . The amplified IF signal can be down-converted to baseband signals by the mixers 8916 using an LO signal generated by synthesizer 8950 . The baseband signal is then filtered by low-pass filters 8918 , and converted to a digital signal by the ADC blocks 8920 before being processed by the modem 8934 .

In an example transmit operation associated with RFEM 8802 , a digital signal output by the modem 8934 can be converted to analog signals by the DAC blocks 8932 . The analog signals are then filtered by the low-pass filters 8930 and then up-converted to an IF signal by the mixers 8928 using an LO signal generated by synthesizer 8950 . The IF signal can be amplified by the IF amplifier 8926 , and then up-converted to an RF signal using the mixers 8924 and an LO signal generated by synthesizer 8952 . The RF signal is then communicated to the RFEM 8802 via the triplexer 8902 and the single coax cable 8806 .

In an example receive operation associated with RFEM 8840 , an RF signal is received from the RFEM 8840 via the triplexer 8906 . The received RF signal is down-converted to an IF signal by the mixer 8938 using an LO signal generated by synthesizer 8948 . The IF signal is amplified by IF amplifier 8914 . The amplified IF signal can be down-converted to baseband signals by the mixers 8916 using an LO signal generated by synthesizer 8950 . The baseband signal is then filtered by low-pass filters 8918 , and converted to a digital signal by the ADC blocks 8920 before being processed by the modem 8934 .

In an example transmit operation associated with RFEM 8840 , a digital signal output by the modem 8934 can be converted to analog signals by the DAC blocks 8932 . The analog signals are then filtered by the low-pass filters 8930 and then up-converted to an IF signal by the mixers 8928 using an LO signal generated by synthesizer 8950 . The IF signal can be amplified by the IF amplifier 8926 , and then up-converted to an RF signal using the mixer 8946 and an LO signal generated by synthesizer 8948 . The RF signal is then communicated to the RFEM 8840 via the triplexer 8906 and the single coax cable 8807 .

Even though BBS 8804 is illustrated in FIG. 89 as having only two triplexers and two separate up-conversion and down-conversion chains associated with RFEMs 8802 and 8840 , the disclosure is not limited in this regard. More specifically, the BBS 8804 can include additional up-conversion and down-conversion chains for processing signals in other wireless bands serviced by additional RFEMs.

As explained herein, the communication architecture solution described in connection with FIGS. 83 - 85 uses IF signals passed over a coaxial cable, which lends itself to modularity, but may need additional circuitry (synthesizer circuits, reference generation and recovery, IF amplifiers, mixers, and a more complicated triplexer due to a tighter frequency plan), as well as a higher number of signals (e.g., reference frequency for the synthesizer and control signals) on the RFEM. Since in small platforms (especially mobile phone platforms), area and volume near the platform edge can be expensive (a lot of competing antennas and protocols for a limited volume, especially when platforms are becoming thinner and thinner), this added content may result in difficulty with implementation and processing efficiency.

The communication architecture solution described in connection with FIGS. 86 - 89 is an alternative solution for reducing circuit complexity. More specifically and as seen in FIGS. 86 - 89 , IF and synthesizer content is removed from the RFEM, thereby significantly reducing the silicon area and solution volume around the antenna. However, the solution of FIGS. 86 - 89 may have some drawbacks connected with modularity. For example, for any band that support is needed, a new BBS chip (for specific RF and IF frequencies) may be needed. This can be a drawback because some BBSs can include wireless band processing that is not required by some system vendors, or it does not include a specific band processing functionality required by other vendors.

In some aspects, a companion chip solution can be introduced and implemented within a distributed phased array communication system. The companion chip solution is illustrated herein in reference to FIGS. 90 - 92 . More specifically, the RFEM is based on RFoC processing (similar to the RFEMs in FIGS. 86 - 89 ), and the BBS is configured for processing IF signals, which can keep the BBS the same in different distributed phased array communication systems. The companion chip is introduced as a link between the RFEM and the BBS, and can be configured for RF-to-IF signal processing associated with a specific wireless band. In this regard, area and volume at the platform edge are reduced and the BBS can be kept identical for multiple communication systems (with a different companion chip introduced in different communication systems based on the processing band requirements). By using a companion chip, both modularity and minimal volume at the platform edge can be achieved.

As used herein, the term “companion chip” is used interchangeably with the term supplemental intermediate frequency sub-system (SIFS).

FIG. 90 illustrates an exemplary distributed phased array system including RFEM, a companion chip and a BBS, with IF processing offloaded to the companion chip according to some aspects. Referring to FIG. 90 , the distributed phased array communication system 9000 can include RFEM 9002 , a companion chip 9040 , and a baseband sub-system (BBS) 9004 . The RFEM 9002 is coupled to the companion chip 9040 via a single coax cable 9042 . The companion chip 9040 is coupled with the BBS 9004 via connection 9006 . In some aspects, the connection 9006 can be PCB connection traces (e.g., as indicated with 9122 and 9124 in FIG. 91 ).

The RFEM 9002 can include a phased antenna array 9008 , an RF receiver 9010 , an RF transmitter 9012 , a duplexer 9036 , and a transmit (TX)/receive (RX) switch 9034 . The RF receiver 9010 can include a plurality of power amplifiers 9016 , a plurality of phase shifters 9018 , a combiner 9020 , and an RF amplifier 9022 . The RF transmitter 9012 can include an RF amplifier 9032 , a splitter 9030 , a plurality of phase shifters 9028 , and a plurality of amplifiers 9026 .

In an example receive operation, the switch 9034 can activate receiver chain processing. The antenna array 9008 can be used for receiving a plurality of signals 9014 . The received signals 9014 can be amplified by amplifiers 9016 and their phase can be adjusted by corresponding phase shifters 9018 . Each of the phase shifters 9018 can receive a separate phase adjustment signal (not illustrated in FIG. 90 ) from a control circuitry (e.g., from a modem within the BBS 9004 ), where the individual phase adjustment signals can be based on desired signal directionality when processing signals received via the phased antenna array 9008 .

The phase adjusted signals at the output of the phase shifters 9018 can be combined by the combiner 9020 and then amplified by the RF amplifier 9022 to generate an RF input signal 9023 . The RF input signal 9023 can be communicated to the companion chip 9040 via the duplexer 9036 and the coax cable 9042 . In some aspects, the RF input signal 9023 can be a 60 GHz signal or another signal in a millimeter wave band including a 5G communication band. In some aspects, the RFEM 9002 can include an adaptive matching block 9038 for impedance matching prior to communication of signals via the coax cable 9042 , as explained herein below.

In an example transmit operation, the switch 9034 can activate transmitter chain processing. The BBS 9004 can generate a baseband signal, which can be converted to an IF signal within the BBS 9004 . The IF signal can be communicated to the companion chip 9040 via connection 9006 , where it can be converted to an RF output signal 9031 . The RFEM 9002 can receive the RF output signal 9031 from the companion chip 9040 via the coax cable 9042 and the duplexer 9036 .

The RF output signal 9031 can be amplified by RF amplifier 9032 and then communicated to the splitter 9030 . The splitter 9030 can generate multiple copies of the amplified RF signal and communicate the signal copies to the plurality of phase shifters 9028 . The plurality of phase shifters 9028 can apply different phase adjustment signals to generate a plurality of phase adjusted signals, which can be amplified by the plurality of amplifiers 9026 . The plurality of amplifiers 9026 generates a plurality of signals 9024 for transmission by the phased antenna array 9008 .

FIG. 91 illustrates a more detailed diagram of the companion chip and the BBS of FIG. 90 according to some aspects. Referring to FIG. 91 , the companion chip 9040 can include a duplexer 9102 , a receiver 9104 , transmitter 9106 , and a LO synthesizer 9108 . The receiver 9104 can include a mixer 9110 , an LO amplifier 9112 , and an IF amplifier 9104 . The transmitter 9106 can include a mixer 9118 , an LO amplifier 9116 , and an IF amplifier 9120 .

The BBS 9004 can include an RF receiver 9126 , an RF transmitter 9128 , a modem 9130 , a crystal oscillator 9136 , a synthesizer 9134 , and a divider 9132 . The synthesizer 9134 may include suitable circuitry, logic, interfaces and/or code and can use a signal from the crystal oscillator 9136 to generate a clock signal, such as signal 9135 . The generated clock signal 9135 can be used by the RF receiver 9126 to down-convert a received IF signal (from the companion chip 9040 ) using the mixers 9140 . The generated clock signal 9135 can also be used by the RF transmitter 9128 to up-convert a baseband signal into an IF signal using the mixers 9148 .

In some aspects, the LO signal 9135 can be divided by divider 9132 to generate a clock reference signal 9133 . The clock reference signal 9133 can be communicated to the companion chip 9040 and used by the synthesizer 9108 to generate an LO signal 9154 used for down-converting an RF signal (e.g., 9023 ) into an IF signal, or for up converting an IF signal into an RF signal (e.g., 9031 ).

The RF receiver 9126 can include an IF amplifier 9138 , mixers 9140 , filters 9142 , and analog-to-digital conversion (ADC) blocks 9144 . The RF transmitter 9128 can include digital-to-analog conversion (DAC) blocks 9152 , filters 9150 , mixers 9148 , and an IF amplifier 9146 .

In an example receive operation, an RF signal (e.g., 9023 ) is received by the companion chip 9040 from the RFEM 9002 via the single coax 9042 and the duplexer 9102 . The RF signal 9023 is down-converted by the receiver 9104 to generate an IF signal 9156 . More specifically, the RF signal 9023 is down-converted by the mixer 9110 using an LO reference signal 9154 amplified by amplifier 9112 . The down-converted signal is amplified by amplifier 9114 to generate the IF signal 9156 . The IF signal 9156 is communicated to the BBS 9004 via connection 9006 (e.g., board traces 9122 ) for additional processing by the receiver 9126 . Initially, the IF signal 9156 is amplified by the IF amplifier 9138 . The amplified IF signal can be down-converted to baseband signals by the mixers 9140 , then filtered by low-pass filters 9142 , and converted to a digital signal by the ADC blocks 9144 before being processed by the modem 9130 . In some aspects, there may be included TX/RX switches at both input/output sides of the companion chip 9040 and the BBS 9004 , so that a single signal (e.g., a combined signal) can be communicated between sub-systems 9040 and 9004 . In this case, a single set of board traces can be used (e.g., only 9122 ) instead of multiple sets.

In an example transmit operation, a digital signal output by the modem 9130 can be converted to analog signals by the DAC blocks 9152 . The analog signals are then filtered by the low-pass filters 9150 and up-converted to an IF signal by the mixers 9148 . The IF signal can be amplified by the IF amplifier 9146 to generate an IF signal 9158 . The IF signal 9158 is communicated to the companion chip 9040 via the connection 9006 (e.g., board traces 9124 ). At the companion chip 9040 , the IF signal 9158 is initially amplified by amplifier 9120 within transmitter 9106 , and is then up-converted by mixer 9118 using the LO signal 9154 amplified by amplifier 9116 . The mixer 9118 generates an RF output signal 9031 , which is communicated to the RFEM 9002 via the duplexer 9102 and the coax cable 9042 .

In some aspects, the coax cable 9042 can be used for communication of DC power signals (e.g., from the BBS 9004 to the RFEM 9002 ), control signals and RF data signals that are received or transmitted by the phased array antenna elements 9008 . The control signals can include phase adjustment signals, power up signals, power down signals, and other control signals communicated from the BBS 9004 to the RFEM 9002 and/or the companion chip 9040 . In some aspects, control signals can include phase adjustment request signals or other data request signals communicated from the RFEM 9002 to the BBS 9004 via the companion chip 9040 . In this regard, a direct conversion scheme can be used in connection with a distributed phased array system, where the RFEM and the BBS are coupled via a single coax cable.

In some aspects, the control signal can be used for controlling the RFEM operation (e.g., controlling output power levels, AGC, ON/OFF, etc.). Additionally, the control link between the RFEM and the BBS can be bi-directional, and can be used for BBS-to-RFEM commands and for RFEM-to-BBS telemetry transfer (e.g., PA power detectors reading, ACK after a control command reception, temperature detector reading, etc.).

FIG. 92 illustrates a multi-band distributed phased array system with IF processing within the companion chip according to some aspects. Referring to FIG. 92 , the distributed phased array communication system 9200 can be used to implement a multi-band system. More specifically, multiple RFEMs ( 9202 , . . . , 9204 ) can be used with a single companion chip 9206 and a single BBS 9208 , with each RFEM including a phased antenna array for processing wireless signals in a specific communication band. The RFEMs 9202 , . . . , 9204 can be coupled to the companion chip 9206 via corresponding single coax cables 9210 , . . . , 9212 .

Referring to FIG. 92 , the companion chip 9206 can include multiple processing chains, each chain being associated with a separate RFEM. More specifically, a first processing chain within the companion chip 9206 can be associated with the RFEM 9202 and can include duplexer 9216 , IF receiver 9218 , LO generator 9222 , and IF transmitter 9220 . A second processing chain within the companion chip 9206 can be associated with the RFEM 9204 and can include duplexer 9236 , IF receiver 9238 , LO generator 9242 , and IF transmitter 9240 .

The BBS 9208 can include a receiver 9260 , a transmitter 9262 , a modem 9264 , an oscillator 9270 , a synthesizer 9268 , and a divider 9266 . The synthesizer 9268 may include suitable circuitry, logic, interfaces and/or code and can use a signal from the crystal oscillator 9270 to generate clock signals. In some aspects, the synthesizer 9268 can generate an LO signal used by the mixers 9274 to down-convert an IF signal 9258 , or used by the mixers 9282 to up-convert a baseband signal into an IF signal for amplification by amplifier 9280 . In some aspects, the synthesizer 9268 can generate an LO signal, which can be divided by divider 9266 to generate a clock reference signal 9267 . The clock reference signal can be communicated via the board traces 9214 to the companion chip 9206 for use by the synthesizer's 9222 and 9242 in generating the corresponding LO signals 9223 and 9243 .

The receiver 9260 can include an IF amplifier 9272 , mixers 9274 , filters (e.g., low-pass filters) 9276 , and analog-to-digital conversion (ADC) blocks 9278 . The transmitter 9262 can include digital-to-analog conversion (DAC) blocks 9286 , filters 9284 , mixers 9282 , and an IF amplifier 9280 .

In an example receive operation associated with RFEM 9202 , an RF signal is received at the companion chip 9206 from the RFEM 9202 via the coax cable 9210 and the duplexer 9216 . The received RF signal is down-converted to an IF signal by the mixer 9224 using an LO signal 9223 generated by synthesizer 9222 . The IF signal is amplified by IF amplifier 9228 . The amplified IF signal 9258 is transmitted to the BBS 9208 via the board traces 9214 for further processing by the receiver 9260 . At the receiver 9260 , the IF signal 9258 is initially amplified by amplifier 9272 , and down-converted to baseband signals by the mixers 9274 using an LO signal generated by the synthesizer 9268 . The baseband signal is then filtered by low-pass filters 9276 , and converted to a digital signal by the ADC blocks 9278 before being processed by the modem 9264 .

In an example transmit operation associated with RFEM 9202 , a digital signal output by the modem 9264 can be converted to analog signals by the DAC blocks 9286 . The analog signals are then filtered by the low-pass filters 9284 and then up-converted to an IF signal by the mixers 9282 using an LO signal generated by the synthesizer 9268 . The IF signal can be amplified by the IF amplifier 8926 to generate an amplified IF signal 9256 . The IF signal 9256 is communicated to the companion chip 9206 via the board traces 9214 , for further processing by the IF transmitter 9220 . Within the transmitter 9220 , the IF signal 9256 is amplified by amplifier 9234 and up-converted to an RF signal by mixer 9232 using LO signal 9223 amplified by amplifier 9230 . The RF signal is communicated to RFEM 9202 via the duplexer 9216 and the coax cable 9210 , for further processing and transmission by the RFEM antenna array. In some aspects, TX/RX switches can be used in both the companion chip 9206 and the BBS 9208 so that a single set of board traces can be used to communicate a single signal (which can be a combined signal) at any given time.

In an example receive operation associated with RFEM 9204 , an RF signal is received at the companion chip 9206 from the RFEM 9204 via the coax cable 9212 and the duplexer 9236 . The received RF signal is down-converted to an IF signal by the mixer 9244 using an LO signal 9243 generated by the synthesizer 9242 . The IF signal is amplified by IF amplifier 9248 . The amplified IF signal 9258 is transmitted to the BBS 9208 via the board traces 9214 for further processing by the receiver 9260 . At the receiver 9260 , the IF signal 9258 is initially amplified by amplifier 9272 , and down-converted to baseband signals by the mixers 9274 using an LO signal generated by the synthesizer 9268 . The baseband signal is then filtered by low-pass filters 9276 , and converted to a digital signal by the ADC blocks 9278 before being processed by the modem 9264 .

In an example transmit operation associated with RFEM 9202 , a digital signal output by the modem 9264 can be converted to analog signals by the DAC blocks 9286 . The analog signals are then filtered by the low-pass filters 9284 and then up-converted to an IF signal by the mixers 9282 using an LO signal generated by the synthesizer 9268 . The IF signal can be amplified by the IF amplifier 8926 to generate an amplified IF signal 9256 . The IF signal 9256 is communicated to the companion chip 9206 via the board traces 9214 , for further processing by the IF transmitter 9240 . Within the transmitter 9240 , the IF signal 9256 is amplified by amplifier 9254 and up-converted to an RF signal by mixer 9252 using LO signal 9243 amplified by amplifier 9250 . The RF signal is communicated to RFEM 9204 via the duplexer 9236 and the coax cable 9212 , for further processing and transmission by the RFEM antenna array.

Even though the companion chip 9206 is illustrated in FIG. 92 as having only two duplexers and two separate processing chains (with a receiver and a transmitter in each processing chain) associated with RFEMs 9202 and 9204 , the disclosure is not limited in this regard. More specifically, the companion chip 9206 can include additional processing chains for processing signals in other wireless bands serviced by additional RFEMs.

Even though FIGS. 91 - 92 discuss sub-systems 9108 , 9134 , 9222 , 9242 , and 9268 as LO generators, these sub-systems can also include other types of frequency sources (e.g., frequency multipliers, etc.).

Even though FIGS. 83 - 92 illustrate a direct connection between triplexers (or duplexers) and receiver and/or transmitter and/or frequency sources, the disclosure is not limited in this regard and corresponding TX/RX switches may be used so that one only combined signal can be communicated to the triplexres (or duplexers). For example and in reference to FIG. 83 , there can be a TX/RX switch between the triplexer 8348 and the LO generator (or frequency source) 8344 , allowing for only TX or RX signals to be communicated at any single time via the triplexers 8348 . Similar TX/RX switches can be used in connection with triplexres/duplexers 8402 , 8550 , 8636 , 8702 , 8836 , 8902 , 8906 , 9036 , 9102 , 9216 , and 9236 .

RF communication systems often times utilize sub-systems (e.g., voltage controlled oscillators (VCOs), power amplifiers, transceivers, modems, and so forth) that are formed on a semiconductor die. However, on-chip integrated devices can include metal stacks and metal stacks associated with any process node, especially advanced process nodes, have poor quality factors associated with their passive elements. In this regard, overall power combining efficiency, especially for large-scale power combiners implemented on chip, can be low.

FIG. 93 illustrates an exemplary on-chip implementation of a two-way power combiner according to some aspects. Referring to FIG. 93 , there is illustrated a two-way power combiner 9300 , which can include power amplifiers 9302 and 9304 coupled to a resistor 9306 . The two-way power combiner may be incorporated in the RF circuitry 325 of mmWave communication circuitry 300 shown in FIG. 3 A , although the two-way power combiner 9300 is not limited to such. Additionally, power amplifier 9302 is coupled to a transmission line 9308 and power amplifier 9304 is coupled to a transmission line 9310 . The transmission lines 9308 and 9310 can be quarter wavelength transmission lines. The outputs of both transmission lines 9308 and 9310 can be combined together and terminate at antenna 9312 . As seen in FIG. 93 , the two-way power combiner 9300 is entirely implemented within a semiconductor die, or chip 9320 . The chip 9320 can be packaged together with a PCB substrate 9330 . The antenna 9312 can be implemented on the PCB substrate 9330 , and can include a phased antenna array, for example.

FIG. 94 illustrates an exemplary on-chip implementation of a large scale power combiner according to some aspects. Referring to FIG. 94 , there is illustrated a power combiner 9412 coupled to a plurality of power amplifiers 9406 , 9408 , . . . , 9410 . The power amplifier outputs can be coupled to inputs of the power combiner 9412 . The power combiner 9412 can be coupled to more than two power amplifiers and, therefore, can be referred to as a large-scale power combiner.

The power combiner 9412 can include cascading connections of transmission lines and resistances in a plurality of combining stages, with a decreasing number of outputs (the last combining stage having a single output). For example, power amplifiers 9406 and 9408 can be coupled to transmission lines 9414 and 9416 , respectively. The outputs of the power amplifiers 9406 and 9408 can be coupled by resistance 9436 . The outputs of the transmission lines 9414 and 9416 are combined into a single output 9422 , which is communicated to a subsequent combining stage. Similarly, power amplifier 9410 and a neighboring power amplifier (not illustrated in FIG. 94 ) are coupled to transmission lines 9418 and 9420 , as well as resistance 9438 . The outputs of transmission lines 9418 and 9420 are combined into a single output 9424 , which is communicated to the subsequent combining stage.

This process of combining outputs of previous stages and generating a decreasing number of inputs to subsequent combining stages continues until the last two transmission lines 9426 and 9428 . The inputs to transmission lines 9426 and 9428 are coupled via resistance 9440 , and the outputs of transmission lines 9426 and 9428 are combined into a single output 9430 of the power combiner 9412 . The output signal 9430 of the power combiner 9412 is communicated to antenna 9434 via a connection terminal 9432 . As seen in FIG. 94 , the power amplifiers 9406 - 9410 and the power combiner 9412 are implemented within a semiconductor die, or chip 9402 . The chip 9402 can be packaged together with a PCB substrate 9404 . In some aspects, the connection terminal 9432 can be one of a plurality of solder balls used to connect the chip 9402 with the PCB substrate 9404 .

FIG. 95 illustrates an exemplary on-chip implementation of an impedance transformation network according to some aspects. Referring to FIG. 95 , there is illustrated a power amplifier 9506 coupled to an antenna 9512 via an impedance transformation network 9508 . The impedance transformation network 9508 may include suitable circuitry, logic, interfaces and/or code and can be configured to match an impedance at the output of the power amplifier 9506 with an impedance at the input of the antenna 9512 . The impedance transformation network 9508 can be coupled to the antenna 9512 via a connection terminal 9510 .

In some aspects, the connection terminal 9510 can be used for coupling testing or measurement equipment to the power amplifier 9506 . Testing or measurement equipment can be associated with a 50 ohm resistance, which may be too high for the power amplifier 9506 . The impedance transformation network 9508 can be used to couple the power amplifier 9506 and the testing equipment at connection terminal 9510 and adjust the impedance accordingly. As seen in FIG. 95 , the power amplifier 9506 and the impedance transformation network 9508 are implemented within a semiconductor die, or chip 9502 . The chip 9502 can be packaged together with a PCB substrate 9504 . In some aspects, the connection terminal 9510 can be one of a plurality of solder balls used to connect the chip 9502 with the PCB substrate 9504 .

As seen in FIG. 93 , FIG. 94 , and FIG. 95 , power amplifiers, power combiners, and impedance transformation networks are implemented on chip. However, on-chip power combining and impedance transformation can be lossy due to poor quality of passives and lossy silicon substrate, degrading overall transmission efficiency. Such losses can increase quickly with higher levels of combining and/or steep impedance transformations. Lossy power combining and impedance transformation can be further exacerbated for advanced technology nodes with poor silicon metallization. In some aspects, lossy power combining and impedance transformation can be improved by implementing power combining an impedance transformation networks on the PCB substrate associated with the semiconductor die. In this regard, on package losses can be significantly lowered for power combining. This can provide significant efficiency enhancements and can be well-suited for large-scale power combining, especially for architectures using quarter wave transmission lines or multiple transmission lines. Example aspects where impedance transformation networks and power combining are implemented on the PCB substrate are illustrated herein below in reference to FIG. 96 , FIG. 97 , FIG. 98 , and FIG. 99 .

FIG. 96 illustrates an exemplary on-package implementation of a two-way power combiner according to some aspects. Referring to FIG. 96 , there is illustrated a two-way power combiner 9600 , which can include power amplifiers 9602 and 9604 coupled to a resistor 9606 . Additionally, power amplifier 9602 is coupled to a transmission line 9608 , and power amplifier 9604 is coupled to a transmission line 9610 . The transmission lines 9608 and 9610 can be quarter wavelength transmission lines. The outputs of both transmission lines 9608 and 9610 can be combined together and terminate at antenna 9612 .

As seen in FIG. 96 , the power amplifiers 9602 and 9604 can be implemented within a semiconductor die, or chip 9620 . The chip 9620 can be packaged together with a PCB substrate 9630 . The resistor 9606 , the transmission lines 9608 and 9610 , and antenna 9312 can be implemented on the PCB substrate 9630 . The transmission lines 9608 and 9610 and the resistor 9606 can be coupled to the power amplifiers 9602 and 9604 via connection terminals 9614 and 9616 . In some aspects, the connection terminals 9614 and 9616 can be one of a plurality of solder balls used to connect the chip 9620 with the PCB substrate 9630 .

FIG. 97 illustrates an exemplary on-package implementation of a large scale power combiner according to some aspects. Referring to FIG. 97 , there is illustrated a power combiner 9712 coupled to a plurality of power amplifiers 9706 , 9708 , . . . , 9710 . The power amplifier outputs can be coupled to inputs of the power combiner 9712 . The power combiner 9712 can be coupled to more than two power amplifiers and, therefore, can be referred to as a large-scale power combiner. In some aspects, the power combiner 9712 can be a N:1 RF power combiner.

The power combiner 9712 can include cascading connections of transmission lines and resistances in a plurality of combining stages, with a decreasing number of outputs (the last combining stage having a single output). For example, power amplifiers 9706 and 9708 can be coupled to transmission lines 9714 and 9716 , respectively. The outputs of the power amplifiers 9706 and 9708 can be coupled by resistance 9740 . The outputs of the transmission lines 9714 and 9716 are combined into a single output 9722 , which is communicated to a subsequent combining stage. Similarly, power amplifier 9710 and a neighboring power amplifier (not illustrated in FIG. 97 ) are coupled to transmission lines 9718 and 9720 , as well as resistance 9742 . The outputs of transmission lines 9718 and 9720 are combined into a single output 9724 , which is communicated to the subsequent combining stage.

This process of combining outputs of previous stages and generating a decreasing number of inputs two subsequent combining stages continues until the last two transmission lines 9726 and 9728 . The inputs to transmission lines 9726 and 9728 are coupled via resistance 9744 , and the outputs of transmission lines 9726 and 9728 are combined into a single output 9730 of the power combiner 9712 . The output signal 9730 of the power combiner 9712 is communicated to antenna 9732 .

As seen in FIG. 94 , the power amplifiers 9706 - 9710 are implemented within a semiconductor die, or chip 9702 . The chip 9702 can be packaged together with a PCB substrate 9704 . The outputs of power amplifiers 9706 - 9710 can be coupled to corresponding transmission lines of the power combiner 9712 via connection terminal's 9734 , 9736 , . . . , 9738 . In some aspects, the connection terminals 9734 - 9738 can be a plurality of solder balls used to connect the chip 9702 with the PCB substrate 9704 .

In some aspects, the power combiner 9712 , the power amplifiers 9706 - 9710 , and/or the antenna 9732 can be part of a wireless transceiver. The wireless transceiver can be used to receive and transmit signals compliant with one or more wireless protocols, such as Wireless Gigabit Alliance (WiGig) protocol or a 5G protocol.

FIG. 98 illustrates an exemplary on-package implementation of an impedance transformation network according to some aspects. Referring to FIG. 98 , there is illustrated a power amplifier 9806 coupled to an antenna 9812 via an impedance transformation network 9808 . The impedance transformation network 9808 may include suitable circuitry, logic, interfaces and/or code and can be configured to match an impedance at the output of the power amplifier 9806 with an impedance at the input of the antenna 9812 . The impedance transformation network 9808 can be coupled to the power amplifier 9806 via a connection terminal 9810 . In some aspects, the connection terminal 9810 can be used for coupling testing or measurement equipment to the power amplifier 9806 . Testing or measurement equipment can be associated with a 50 ohm resistance, which may be too high for the power amplifier 9806 . The impedance transformation network 9808 can be used to couple the power amplifier 9806 and the testing equipment at connection terminal 9810 and adjust the impedance accordingly.

As seen in FIG. 98 , the power amplifier 9806 is implemented within a semiconductor die, or chip 9802 . The chip 9802 can be packaged together with a PCB substrate 9804 . The impedance transformation network 9808 and the antenna 9812 can be implemented within the PCB substrate 9804 . In some aspects, the connection terminal 9810 can be one of a plurality of solder balls used to connect the chip 9802 with the PCB substrate 9804 .

FIG. 99 illustrates an exemplary on-package implementation of a Doherty power amplifier according to some aspects. Referring to FIG. 99 , the Doherty power amplifier 9900 can include a carrier power amplifier 9906 and a peaking power amplifier 9908 . A signal input terminal 9922 can be directly coupled to an input of the carrier power amplifier 9906 . The signal input terminal 9922 can also be coupled to an input of the peaking power amplifier 9908 via a quarter wavelength transmission line 9910 . An output of the carrier power amplifier 9906 can be coupled to the antenna 9920 via offset transmission line 9912 as well as quarter wavelength transmission lines 9916 and 9918 . The output of the peaking amplifier 9908 can be coupled to the antenna 9920 via an offset transmission line 9914 and a quarter wavelength transmission line 9918 . A combined output signal 9924 at the output of the transmission line 9918 can be communicated to antenna 9920 for transmission.

As seen in FIG. 99 , the carrier power amplifier 9906 , the peaking power amplifier 9908 , and the quarter wavelength transmission line 9910 can be implemented within a semiconductor die, or chip 9902 . The chip 9902 can be packaged together with a PCB substrate 9904 . Transmission lines 9912 , 9914 , 9916 , and 9918 , as well as antenna 9920 , can be implemented within the PCB substrate 9904 . In this regard, by implementing multiple long transmission lines on the PCB substrate 9904 , the efficiency of the Doherty power amplifier 9900 can be improved.

Microwave antenna sub-systems that operate in the mmWave frequency range are extremely small, in the micron range. Consequently it is important to discover ways to reduce the size of antennas and of radio sub-systems, particularly thickness, for use in mobile devices where space is at a premium because of chassis size requirements and because of the dense packaging of components and antennas. At the same time, thermal, electrical and mechanical overlay issues should be addressed and reduced. Cost improvement is also a major consideration. The overlay of components, antennas and antenna sub-systems on top of each other will reduce both size and thickness of the sub-system. Use of overmold with interconnects in overmold is another concept that will allow antennas to be located on the sides of a sub-system, and provide thermal and mechanical improvement over competing technologies.

FIG. 100 A is a side view of an unmolded stacked package-on-package embedded die radio system using a connector, according to some aspects. The embedded die radio system may be incorporated in the antenna array circuitry 330 of mmWave communication circuitry 300 shown in FIG. 3 A , although the embedded die radio system is not limited to such. The aspect includes unmolded stacked package-on-package embedded die 10000 including unmolded package 10005 and package 10007 . Package 10005 may include a laminated structure such as a PCB, within which is embedded RFIC 10006 . As used in this context, “unmolded” means that the die 10006 is not enveloped in a mold or encapsulate. The dimensions illustrated for the z-height of the various parts of the packages are for example purposes only, and serve to illustrate the extremely small dimensions that are worked with when volume of a mobile device in which the packages find use is very restricted.

In addition, the first few microns at the top and bottom of PCB 10005 can be pre-impregnation (PrePreg) layers which may be before the core of the PCB within which the RFIC is embedded. PrePreg can be used thanks to its very thin thickness. The PrePreg can be very thin, for example 25 um or 30 um. PrePreg may be an epoxy material, although it can also be a laminate material, for example Copper Clad Laminate (CCL). The technology is not limited to organic polymer based laminates but also ceramic based inorganic layers.

As used in the antenna substrate industry, “core” can mean the internal part of a substrate that is thicker than, and that can be more rigid than, other areas of the substrate, such as PrePreg. Package 10005 is unmolded in that it is a laminar substrate such as a PCB with no encapsulate within the package. Shield 10001 is on top of package 10005 to shield components 10003 from RFI/EMI. Connector 10023 may connect one or more of the packages to the outside world. In some aspects connector 10023 provides intermediate frequency (IF) signals for transmission by the system. Package 10005 includes RFIC die 10006 which provides feeding for the various antennas and antenna arrays, discussed below, by way of traces and vias as appropriate, according to some aspects.

While one RFIC die 10006 is illustrated, those of ordinary skill in the art would recognize that more than one RFIC die can be provided, to operate in one or more frequency bands. In other words there may be at least one RFIC die in aspects.

The packages illustrated can include antennas and antenna arrays of many different configurations, frequencies of operation, and bandwidths, according to some aspects. In FIG. 100 A antenna structures 10009 , 10011 , 10013 , 10015 , and 10019 are illustrated. These can be single antennas in side view, or antenna arrays, such as 1×N, 2×N, . . . , N×N element arrays looking into the page of the figure. In one example, antenna 10009 can be a dual patch antenna with a distance d 2 , in this aspect of 10065 microns between patch antenna elements 10010 and 10012 , and another dimension d 1 between patch antenna element 10010 and ground. Depending on the distances d 1 and d 2 , the bandwidth of the antenna will vary because of the varying volume of the patch antenna. The designation d 1 and d 2 can be seen more clearly in FIG. 100 B .

FIG. 100 B is a side view of a dual patch antenna, according to some aspects. In the figure, P 1 is a first element of a dual patch antenna and P 2 is a second, or driven, element of a dual patch antenna. It is seen that d 2 is the distance between P 1 and P 2 and d 1 is the distance between P 1 and ground plane GND. For a given distance d 1 between P 1 and GND, varying the distance d 2 between P 1 and P 2 increases the volume of the antenna.

In some aspects, the bandwidth varies based on the variation of the volume of the antenna which, in this aspect, is a function of the varying distance d 2 . This is seen in FIG. 1000 . FIG. 1000 is a simulated graph of return loss of the dual patch antenna of FIG. 100 B as the volume of the antenna is increased, according to some aspects, and illustrates the variation of bandwidth as the volume of the antenna varies. The bandwidth is measured by varying d 2 in this aspect. Bandwidth, illustrated as the width of the −10 dB return loss graph in the simulation of FIG. 1000 , increases as d 2 increases, for a given d 1 dimension between P 1 and GND.

As will be discussed below, the PCB 10005 has a laminar structure illustrated in this aspect as levels L 1 through L 6 . Because of the various levels, the antenna elements such as 10010 , 10012 can be placed at various distances d 2 between dual patch antenna elements, and because of the multiplicity of levels the distance d 1 between patch antenna element 10010 and GND can also be set at various distances, resulting in a choice of bandwidths as may be needed for a given design. Stated another way, the distance between dual patch antenna elements 10010 and 10012 is not limited to 10065 microns but can be set at any of several distances because of the densely packed laminate levels available. This is the same with the distance between dual patch antenna element 10010 and ground plane 10014 , setting up an ability to measure the bandwidth as illustrated in FIG. 1000 . However, the levels L 1 -L 6 are only one of many aspects. Other aspects may have many more very densely packed layers, far more than the six layers L 1 -L 6 illustrated, and these very densely packed layers can be used for various functions as needed.

Continuing with the description of FIG. 100 A, 10024 can in some aspects be an antenna or an antenna array such as the 1×N, 2×N, . . . , N×N element arrays discussed briefly above. In some aspects, 10024 can be a self-standing antenna configured by means of a surface mounted device (SMD), which is sometimes called surface mounted technology (SMT). In some aspects, if there is not sufficient height for a needed antenna or antenna array within the PCB 10005 , the antenna or antenna array 10010 , 10012 can be configured with antenna element 10012 placed on the top of the PCB 10005 , for example, to provided needed volume, according to some aspects.

In another example, dual patch antenna element 10012 can be placed on top of surface mounted device 10024 instead of on top of PCB 10005 , to provide the antenna or antenna array with additional height which, in some aspects, will provide increased volume and improved bandwidth as discussed above.

Another example can be seen at antenna 10015 . In this example, antenna (or antenna array, as discussed above) 10015 includes antenna patch 10018 within the substrate 10005 , which, as discussed above, can be a complex and very densely packed substrate, and dual patch element 10017 can be on a second antenna board 10007 . In some aspects antenna board 10007 can be a dielectric, a ceramic, a PCB, or the like, which can also be a densely packed laminar substrate much like PCB 10005 . Consequently, the antenna function can be apportioned between or among more than one antenna board resulting on a package-on-package configuration. Therefore, if there is not enough z-height on one media, then part of the antenna can be implemented on a second media, such as 10007 , to provide the desired z-height in order to obtain the volume to provide the desired parameters such as, in some aspects, bandwidth, lower loss, and the like. In other words, given the extremely small dimensions of the thickness of a substrate due, in some instances, to form factor requirements for operation at mmWave frequencies, antenna elements (and discreet components) can be placed on one or more additional media which, in some aspects, can be placed on top and/or bottom of PCB 10005 , on the sides of PCB 10005 , and in various additional configurations, resulting in additional substrate thickness and increased bandwidth as needed.

Similarly, antenna functions can likewise be split between or among different antenna boards, for example PCB 10005 , which can be considered the main media, and antenna board 10007 , which can be considered a secondary media. Further, such media above or below, or in the side of, the substrate can be used for various functions, such as grounding, shielding, feeds, and the like.

Further, there can be more than one medium 10024 on top of PCB 10005 . There can be a multiplicity of antenna media on top of the PCB 10005 , each providing part or all of the antennas or antenna arrays as discussed above. The same is true of placement of antenna media below or on the side of PCB 10005 . Further, the secondary media can be used for parasitic elements in order to improve the gain or shape the pattern of the antennas as needed.

Antennas 10011 , 10013 , 10015 , and 10019 can be other antennas or antenna arrays configured on antenna board 10007 and fed from RFIC die 10006 . Also illustrated are vias 10020 , 10022 . There may be many vias in some aspects. Generally, the thicker the substrate 10005 , the greater diameter of the via 10020 , 10022 . In some aspects where ultra-thin substrates are needed, the vias can be of a much smaller diameter, as discussed below for other aspects. Vias such as 10028 may be connected to the RFIC die 10006 by solder connections such as 10027 . The vias may be connected by one or more horizontal layers 10030 for connection to components elsewhere within the radio sub-system, where the horizontal layer 10030 is viewed looking into the page.

FIG. 101 A is an illustration of the unmolded stacked package-on-package embedded die radio system using a flex interconnect, according to some aspects. FIG. 101 B is a side view of the unmolded stacked package-on-package embedded die radio system using a flex interconnect where the flex interconnect is shown in photographic representation, according to some aspects. FIG. 101 A is substantially the same as FIG. 100 A with a difference being that there is no connector 10023 in FIG. 101 A . Instead flex interconnect 10026 is used to connect one PCB to a second PCB, where the second PCB may have a connector to outside the PCBs. Flex connector 10026 may be connected to the RFIC die 10006 by appropriate internal traces of PCB 10005 , or by appropriate internal traces and one or more vias. The flex interconnect may be connected to the PCT by solder, by crimping, or by other processes, and may be similarly connected to the second PCB in some aspects.

FIG. 102 is a side view of a molded stacked package-on-package embedded die radio system, according to some aspects. In FIG. 102 package 10200 includes a substrate including level 10201 , such as an antenna board such as a PCB, level 10203 , which is a mold or encapsulate, and level 10205 which includes an antenna board such as a PCB, according to some aspects. Levels 10201 may include conductive levels 10207 such as traces; level 10203 may include conductive levels such as 10209 and vias such as 10219 , 10219 A, often called “through-mold vias”; and level 10205 may include conductive levels 10211 connected by solder connection to conductive levels 10209 .

The conductive levels and vias of package 10200 are configurable to feed the various antennas and other components from dies 10206 , 10208 , in some aspects. Although conductive levels 10207 and 10211 are illustrated as short horizontal layers in FIG. 102 , in practice they can be longer conductive layers such as 10309 , 10311 in FIG. 103 or in various layer configurations such as 10307 , 10311 A of FIG. 103 , or essentially completely across a substrate such as illustrated at 10502 in substrate 10501 , or 10511 in substrate 10505 of FIG. 105 , according to various aspects.

In some aspects the conductive levels 10207 , 10211 may be made using redistribution layers (RDL) discussed below with respect to FIG. 104 . Vias (or through-mold vias in molded packages) may be made by copper studs, by lasers piercing the mold or other layers, and conductive ink, or other means.

Through the use of vias, conductive layers, and/or RDLs, the die(s) are able to connect very quickly to antennas and antenna arrays on any side of the package which, in some aspects may be antennas embodied on or within SMDs 10216 , 10218 , 10220 . Because of densely packed vias, and densely packed horizontal layers, the dies may connect to antennas or antenna arrays on substrates 10201 , 10205 with little or essentially no fan-out of the feed structure.

Further, the through-mold vias such as 10219 , 10219 A may be configured in trenches of densely packed vias connected to metallized layers (only layer 10209 illustrated here, but the top of vias such as 10219 or 10219 A may be connected to a metallized layer atop the vias (now shown)) around the die or dies to form a Faraday cage to shield the dies and other components from RFI and EMI, in some aspects. The vias can be very small vias such as single posts. When using package on package with high density interconnects between the packages such as 10219 , 10219 A (through mold vias), one can build the packages separately and use disparate materials tailored for bottom die versus another die on top or below it. It also improves yield since individual dies can be tested in their respective packages before stacking them.

It is also important to understand that the mold may be eliminated completely if needed and one can replace through mold vias with solder balls that are connected to the top package and act as the vertical interconnect. In the aspect of FIG. 102 , two or more dies 10206 , 10208 may be included within the substrate and affixed by contacts such as solder bumps which may be copper filler, solder contacts such as 10210 , or which may be LGA/VGA pads or, in some aspects, even a package.

Also illustrated are discreet elements 10212 , 10214 , in some aspects. Dies 10206 , 10208 may be any type of die such as flip-chip die, wafer level Chip Scale Package (CSP), wire-bondable die, and the like.

Alternatively, a single die may be used. SMD antennas such as 10216 , 10218 , 10220 may be configured on a first side of the substrate while SMD antennas 10216 A, 10218 A, 10220 A may be configured on the opposite side of the substrate, in some aspects. In other aspects, the antennas may be configured on the substrate instead of on or within SMDs. The foregoing antennas may be the same type of antennas as those described with respect to FIG. 100 A and in some aspects may be on or within SMDs. Further, the antennas 10216 , 10218 , 10220 may be configured as an antenna array. Further, antennas such as any or all of the foregoing antennas may be embodied on or within an SMD such as discussed with respect to antenna (or antenna arrays) 10024 of FIG. 100 A ,

Also configured on one or both sides (such as 10201 , 10205 of the package 10200 may be discreet components 10222 , 10224 , and 10222 A, 10224 A. Further, systems 10221 , 10221 A, sometimes called a system in a package (SIP), or a package, bet may be configured on top (such as atop 10201 ) and/or on bottom (such as at the bottom of 10205 ) and/or sides of the package 10200 , in some aspects, providing a package-on-package configuration. A SIP 10221 , 10221 A may be a system much like the package that includes levels 10201 , 10203 , 10205 that SIPs 10221 , 10221 A are configured upon. SIPs 10221 , 10221 A may be stacked on and physically connected to the package in several ways.

Further dies 10206 , 10208 may be connected to the substrate 10203 by suitable contacts illustrated at 10226 , in some aspects. Such suitable contacts may include copper filler, solder bumps, or even a package. Contacts 10226 may be very small connections within the body of the package-on-package aspect. Such system configurations illustrate package-on package configuration.

Further, one or more dies of each package is configured to operate at the same frequency or at different frequencies, such as one die operating at 5G frequencies and a second die operating at WiGig frequencies, because the density within the packages as described is so high.

Further, the antennas/antenna arrays of the package-on-package aspect may radiate in any of a number of directions, or essentially in every direction, as may be needed, for example, because of the orientation of the mobile device. In other words, antennas, and antenna arrays, can be placed all over a package 10200 , meaning in essentially every desired direction of the package by stacking and physically connecting packages 10221 , 10221 A on the top, bottom, and sides of package 10200 , or in combinations thereof, as desired, and in antenna and antenna array configurations on or within packages 10221 , 10221 A as desired, according to some aspects.

In addition to the foregoing, the package 10200 may be soldered onto yet another board (not shown) by solder balls 10213 , 10215 , which are illustrated as larger than solder ball or contacts 10226 because while solder balls 10226 are within the package-on-package aspect, and can be very small and very tightly spaced, solder balls 10213 , 10215 are connections “to the outside world,” according to some aspects.

For example, the board that package 10200 is further soldered onto, by way of solder balls 10213 , 10215 , may be the host board for a phone, tablet, mobile device, or other end user equipment, according to some aspects. A primary difference between FIGS. 100 A and 102 is that the dies of FIG. 102 are enveloped by mold which protects and strengthens the configuration of the dies within the substrate.

An advantage of the molded aspect is that embedded dies in the unmolded substrate of FIG. 100 A are difficult to manufacture in high volume. A molded substrate configuration is more compatible to high volume manufacture, due, as discussed above, to improved yield since individual dies can be tested in their respective packages before stacking them.

Additionally, in a molded configuration components like 10212 , 10214 can easily be configured within the molded substrate. The embodied die of FIG. 100 A is often specific to embedding only a single die, according to some aspects.

Further, the molded configuration allows many more dense layers than the unmolded configuration. In the embedded die of FIG. 100 A , every component is connected as one system. If one part, such as one via, fails, the entire system within the substrate fails.

In the molded configuration FIG. 102 on the other hand, the substrate itself can be made separately, the layers connecting the dies can be connected separately, and the system is not connected together until the final step, where the final step may be soldering all parts together. In the aspect of FIG. 100 A there is no solder internally, the system being included of copper vias most or all of which may be assembled at the same time. Stated another way, the process of building a molded stacked package is very different from building an unmolded package.

Studs are placed or plated onto the bottom layer of the top package and these can be plated to a high aspect ratio and very small diameters. Then the top and bottom packages are connected using solder or thermo-mechanical compression. The overmold may be liquid, is injected and then flows and covers the gaps. This is a higher density and higher yielding process than an unmolded package.

FIG. 103 is a side view of a molded package-on-package embedded die radio system showing additional detail, according to some aspects. The levels A thought G include the individual component technologies indicated in Table 1, in some aspects.

In FIG. 103 , element 10326 may be a connector a signal source off the package. Also illustrated is antenna element or antenna array 10324 , as the case may be, which may be a surface mounted device antenna or array. Antenna elements include via 10322 that is fed by die 10306 by way of appropriate ones of the illustrated horizontal substrate conductive layers such as 10329 . The die, and the vias discussed below, may be encapsulated by mold 10332 . Trace or horizontal layers 10329 may be connected to die 10306 (connection not shown) for the purpose of feeding antenna or antenna array 10324 also as discussed in additional detail below.

As mentioned previously, the SMD may be part of an array of antenna elements such as 10322 , looking into the page of the drawing, according to some aspects. The density of the horizontal conductive levels and vertical vias, discussed below, enables connection of the die to via 10322 effectively making surface mounted device 10324 essentially a vertical patch antenna in some aspects. The via 10322 including the part within SMD 10324 together provide the desired length for resonance purposes. In some aspects, via 10322 may be a fraction of the antenna length needed for the frequency of operations, and the rest of the needed length may be a trace (not shown) configured on top of the SMD 10324 . Needed contact can be achieved using solder, in some aspects. Consequently, antennas 10322 , and also 10318 , 10320 , discussed below, illustrate advantageous use of the z-height of the package as part of an antenna or antenna array.

An easy implementation to manufacture is a vertical monopole or dipole on or within the SMD. Another implementation may be a patch antenna that is plated on edges of the SMD and the mold that have been discussed above. The availability of such dense horizontal conductive layers and vias as illustrated in levels B and E (the conductive layers can be both horizontal to the figure, and also into the page of the drawing of the figure) gives the flexibility of a multiplicity of interconnections, both horizontal and vertical (vertical such as by vias in some aspects), and provides the ability to configure a vertical patch antenna, a vertical meandering antenna, a vertical spiral antenna, and similar antennas, according to some aspects.

Antenna elements (or antenna arrays looking into the page of the drawing) 10318 , 10320 may be configured on or within an SMD 10324 and include a through mold via 10322 , in some aspects. Several such through mold vias are illustrated in the drawing, only one of which is enumerated, here as 10325 . In FIG. 103 , element 10325 may be a solder ball or other conductive element such as a plated stud that the mold fills around the configuration. Via 10325 may be part of an antenna element such as connected vias 10321 , 10323 , 10325 , 10327 , where via 10321 is within SMD 10320 and may, in some aspects, have a trace substantially perpendicular to vias 10321 , 10323 , 10325 , 10327 depending on the need for additional antenna length for resonance purposes.

The antenna(s) may be connected by a horizontal conductive layer 10331 to die 10306 (connection not shown but in practice 10331 may be a connection to die 10306 ). Discreet elements 10328 may be included and may be shielded from RFI/EMI by shield 10330 , in some aspects. Antennas or antenna array 10318 are similar to or the same as shown at 10320 , and may be connected to the die in a manner similar to that discussed for 10320 . Similarly, items 10318 A, 10320 A, are SMD antennas similar to 10318 , 10320 , and may be fed by die 10306 in a similar manner as SMD antennas 10318 , 10320 . In some aspects, items 10318 , 10320 , 10324 may be configured on antenna boards (not shown) as antenna arrays, looking into the page of the figure. The same situation can apply to SMDs 10318 A, 10320 A. Consequently, the combination Levels B, C, and E of FIG. 103 , and antenna boards on which 10318 , 10320 , 10324 are configured, in accordance with the aspect under discussion, include a package-on-package configuration. In some aspects the above antenna elements may proceed through the relevant one of the antenna boards into or through the SMD 10318 , 10320 , 10324 , or 10318 ′, 10320 ′, 10324 ′, as the case may be.

FIG. 104 is a side view of a package-on-package embedded die radio system using redistribution layers, according to some aspects. Substrate 10400 includes alphabetized levels A through F, each of which may include the material and/or components indicated in Table 2 below, some or all of which may be in various aspects, according to the design at hand.

Substrate 10400 includes at least one embedded die 10406 in level D, which may be wafer level packaging, with very thin conductive layers to redistribute signals from the die to multiple packages in some aspects. Such very thin conductive layers used for redistribution may be called redistribution layers (RDL). Further, for example on top of substrate 10419 , one or more antennas may be on or within one or more surface mounted devices such as 10416 and fed from die 10406 through the interconnects 10421 , 10423 , 10425 and vias (not shown) available in the substrate, as discussed above, as well by the RDLs that in some aspects may connect with such vias.

Die 10406 may be encapsulated by mold 10418 , for example, by a flow process as discussed above. Various antennas may be on or within level A as discussed above with respect to other figures. Level A may also be used for SIPs to result in a package-on-package system, according to some aspects. Further, discreet components 10428 may be on or within level A and may be shielded from RFI/EMI by shield 10430 as may be desired, in some aspects. Other components such as 10432 may not require shielding and may be outside of any shield that may be provided in an aspect.

Additionally, redistribution layers (RDL), which make connections available at different layers, are seen in the figure. Two of the RDLs are illustrated at 10407 , 10409 , but as Table 2 indicates, they can be at top and bottom of layer D, and in numbers as desired, in some aspects. Horizontal layers such as 10415 are seen in the mold Level D with very high density and, as explained above, may provide additional connectivity between layers and connectivity with the die 10406 , in some aspects.

Further, the RLDs may provide vertical connectivity between horizontal layers as at 10413 - 10413 ′ where 10413 is a vertical connection of the RDL. In this regard, the aspect enables placing conductive horizontal layers such as 10413 ′ in the mold at very high density.

The RDLs may be printed directly on the silicon die, shown for example at 10410 , in some aspects, which makes them ultra high density for redistribution of signals from the die 10306 to antennas on antenna arrays. In the RDL configuration described there need not be bumps of solder ball vias such as 10325 of FIG. 103 . The die 10406 is left as is, and RDLs are used for signal distribution, which provides a major advantage.

Redistribution layers may be made using polymer and material that is spin coated on top of each other and are very thin. This allows very fine pitch vias and very fine via diameters. The RDLs, such as 10407 , 10409 may be soldered via solder LGA/VGA pads, or other solder contacts 10440 , 10442 , . . . , 10440 , to antenna board 10412 , in some aspects. Antenna board 10412 may be part of another substrate and is stacked upon and physically connected to substrate 10400 in a package-on-package configuration. While no antennas are illustrated on antenna board 10412 , such antennas may be similar to the antennas on package 10007 of FIG. 100 A and antennas 10216 ′, 10218 ′, 10220 ′ of FIG. 102 , and antennas of other figures.

FIG. 105 is a side view of a molded stacked package-on-package embedded die radio system with recesses in the molded layers to gain height in the z-direction, according to some aspects. Substrate 10500 of FIG. 105 is similar to package 10200 of FIG. 102 .

In some aspects, materials 10501 , 10503 , 10505 may be the same or similar to materials 10201 , 10203 , 10205 in FIG. 102 . Antennas 10516 , 10516 ′, 10516 ″ and discreet components 10528 , 10528 ′ may be configured on or within a first parallel layer of layer 10501 , which may be a substrate layer. Similarly antennas and discreet components may be configured on or within a third parallel layer 10505 , which may be a substrate layer. In some aspects, SIP 10521 may be in physical contact with and connected to level 10505 , the combination of levels 10501 , 10503 , 10505 and SIP 10521 including a package-on-package configuration.

Densely packed conductive horizontal layers, two of which are enumerated 10510 , 10512 , may be configured in layers 10501 , 10505 . However, unlike FIG. 102 , there may be no or few conductive horizontal layers in mold layer 10503 , according to some aspects. FIG. 105 illustrates connector 10526 which, in some aspects, may be placed in a recess 10527 in material 10501 to adjust z-height as may be needed in some aspects. FIG. 105 illustrates a single die 10506 , instead of multiple dies 10206 , 10208 of FIG. 102 , according to the aspect under discussion. Those of ordinary skill in the art would recognize that some or all of the components of FIG. 102 and FIG. 105 may be present in any given aspect, according to the requirements of the solution desired, and that some aspects may include a plurality of embedded dies. Mold 10524 may encapsulate die 10506 and vias 10514 . No, or few, horizontal interconnection layers are in the mold. Interconnection may be by RDLs (not shown in FIG. 105 but as illustrated in FIG. 103 in some aspects.)

FIG. 106 is a side view of the molded stacked package-on-package embedded die radio system. As discussed above, vias such as 10606 may surround the die as a trench and provide Faraday cage shielding. If additional shielding is desired, or if vias may not be available in dense enough form, a mechanical shield 10602 may be include for RFI/EMI shielding and for heat spreading, according to some aspects. Molded substrate 10600 of FIG. 106 includes mold 10624 and materials 10601 , 10603 , 10605 that are similar to or the same as materials 10501 , 10503 , 10505 of FIG. 105 . Mechanical shield 10602 may be soldered to the package, according to some aspects. The soldered shield illustrates the ability to solder within the core of the substrate that will ultimately be encapsulated in a mold, the solder function being a function that is difficult for mass manufacturing in an unmolded shield. Die 10606 is soldered by solder balls 10608 to the “roof” surface of the volume 10603 that will ultimately be encapsulated by a mold material, according to some aspects.

FIG. 107 is a perspective view of a stacked ultra-thin system in a package radio system with laterally placed antennas or antenna arrays, according to some aspects. Estimated parameters of one aspect of the system of FIG. 107 are seen in Table 3 below, for some aspects.

In FIG. 107 , package 10700 includes an ultra-thin application including a shielded die 10706 , shielded by mechanical shield 10709 below the substrate 10701 , 10703 , 10705 , sometimes called a coreless substrate. In some aspects, coreless substrates use only PrePregs that are laminate on a sacrificial material during manufacturing. Hence the rigidity is present because of a rigid sacrificial material. In core based substrates, discussed above, the core (which is not sacrificial) provides the rigidity and hence is thicker.

As used in this context “coreless” means a very thin substrate, unlike a core (which includes a much thicker substrate). Material 10701 , 10703 , 10705 may form layers of a coreless or core based substrate. Material 10704 is thicker because antennas need more volume for performance. In some aspects materials 10701 , 10703 , 10705 may be ultra-thin PrePregs, according to some aspects.

A Package 10700 further may include connector 10707 and components 10710 , which are shielded by mechanical shield 10708 in some aspects. The elements on top and bottom of the substrate take up most of the Z-dimension and the X-dimension such that in the aspect under discussion there is little room for placement of antennas. Consequently, antennas may be located laterally as at 10702 , according to some aspects, on both sides of the substrate by use of antenna boards 10704 , 10704 ′, which may be surface mounted devices, according to some aspects.

The antennas may be an antenna array including antenna elements 10714 - 10714 ′, 10716 - 10716 ′, and 10718 - 10718 ′ configured on SMD 10704 above the substrate, and antenna an antenna array including antenna elements 10722 - 10722 ′, 10724 - 10724 ′, and 10726 - 10726 ′ configured on SMD 10704 ′ below the substrate. Placing the antennas adjacent an ultra-then substrate provides additional room for X-Y and Z dimensions, which increases volume, leading to better bandwidth and gain and less loss, as discussed above.

While 2×4 arrays are illustrated, those of ordinary skill in the art would understand that an N×M array may be configured on top, bottom or sides of the substrate, according to the desired solution. In some aspects, when antenna arrays are located on top, bottom and along the sides of the SMD, radiation direction may be controlled in any of a number of directions depending on algorithmic control of antenna firing and antenna polarity.

Examples of an ultra-thin application could be antennas needed for very thin regions, like GOOGLE™ GLASS™, a thin head set, a very thin tablet, and the like, where available real estate may be so thin that it may be highly unlikely that the available real estate will be used for antennas. In such an environment, antennas could be placed adjacent the package as discussed above, and could yield an omnidirectional antenna, not only due to antenna type or placement, but also because of the sequence of firing of the antennas.

The antennas and the arrays would be fed by die 10706 , and an additional advantage of the ultra-thin coreless substrate is that for thinner materials higher density lines and vias can be used (not shown due to space limitations) as illustrated and discussed above. For example, thick materials usually require a larger via because of the thickness that has to be traversed, as can be seen by vias 10020 and 10022 of FIG. 100 A , and vias 10219 , 10219 ′ of FIG. 102 . On the other hand, nearly hair size diameter vias can be embodied in ultra-thin coreless substrates because of the much shorter distances needed to be traversed by the via.

FIGS. 108 A through 108 C illustrate an embedded die package, according to some aspects. When working at Wi-Fi frequencies, such as 2.4 GHz, 3.6 GHz, 4.9 GHz, 5 GHz, and 5.9 GHz frequency bands, dimensions of the die, feedlines, and antennas will be much larger than when operating at WiGig or 5G mmWave frequency bands in the sixty GHz or other WiGig ranges discussed above. Power losses sustained by dimensions or feedlines at Wi-Fi frequencies become very substantially greater, and in some aspects essentially intolerable, when operating at WiGig or 5G mmWave frequencies.

Consequently, reducing the size of the die substantially by incorporating into the die primarily only the electronic functions needed for a small group of “dedicated” antenna arrays located very close to the reduced function die can result in very short feed line interconnects and therefore less power loss. In other words, the size and shape of the die would be set primarily by the number, and the electronic signal requirements, of dedicated antennas the die services. In some aspects the electronic signal requirements may include signals at one or more polarities, signals in one or more frequency ranges, signals of one or more amplitudes, or signals of a given power, among other signal parameters.

As mentioned, this reduced function enables reduction in size of the die, which in turn enables the die to be placed very, very close to the dedicated antenna, or group of antennas, that use those electronic signals. This results in shorter feedline routing and commensurately lower power loss. In some aspects a large die is reduced to a series very small dies each of which then feeds a dedicated antenna or dedicated antenna array on top and/or bottom of a substrate, resulting in very close, and therefore very short and low-loss interconnects. In some aspects, this can be done by embedding the die in a substrate at a location of the substrate that is physically very close to the antenna arrays that use the limited electronic function of the die.

One such aspect is seen in FIG. 108 A wherein a plurality of dies are embedded in a substrate above and below the antennas that use the respective functions of the particular dies, according to some aspects. In FIG. 108 A die 10809 and associated discreet components such as at 10810 are embedded in package 10801 , according to some aspects. Antennas 10803 and 10811 are configured at the top and bottom of substrate 10801 inasmuch as the antennas need to transmit in an appropriate direction depending on the orientation of the mobile device in which the package resides.

Because of the proximity of the die and the antennas, very short feed mechanisms (not shown in this figure) interconnect the die and the antennas 10803 and 10811 . Further, if space conditions require, one die can be configured to feed antennas (or antenna arrays) on one side of the substrate while a second die can be configured to feed second antennas (or antenna arrays), on the other side of the substrate, and the two sets of antennas or antenna arrays can be algorithmically driven by an appropriate control program.

For example, in FIG. 108 A , die 10809 may drive antennas(s) 10803 while die 10809 ′ may drive antenna(s) 10811 ′ in an a